coreboot February 2013

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New patch to review for coreboot: 2034c33 exynos/snow: Configure UART peripheral in console initialization.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2315 -gerrit commit 2034c33b1db1b402ead9a133c791cccc52f79320 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Feb 7 19:30:40 2013 +0800 exynos/snow: Configure UART peripheral in console initialization. For Exynos platforms, the UART component on pinmux must be first selected and configured. This should be done as part of UART console initialized. In current implementation, the device index is hard-coded as UART3 while the base port can be assigned to different device in KConfig. This will be fixed later. Verified to work on armv7/snow. Change-Id: Ie63e76e2dac09fec1132573d1b0027fce55333a1 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/uart.c | 3 +++ src/mainboard/google/snow/bootblock.c | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index dacdc10..3e80017 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -121,6 +121,9 @@ static void exynos5_init_dev(void) // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); struct s5p_uart *uart = (struct s5p_uart *)base_port; + // TODO initialize with correct peripheral id by base_port. + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index be5a99f..0bee055 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,7 +42,6 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__);

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Patch set updated for coreboot: 77710f5 armv7/snow: Simplify bootblock.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2308 -gerrit commit 77710f5a8e9731d4d2450ee2a6be1a234c1464bf Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Feb 7 13:22:29 2013 +0800 armv7/snow: Simplify bootblock. I2C, power, and max77686 are not always required in bootblock stage. We only need SPI and clock to load romstage. Change-Id: Ic863e222871a157ba4279a673775b1e18c6eac0d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 11 ++++------- src/cpu/samsung/s5p-common/Makefile.inc | 1 - src/drivers/maxim/max77686/Makefile.inc | 1 - src/mainboard/google/snow/Makefile.inc | 4 ---- src/mainboard/google/snow/bootblock.c | 21 --------------------- src/mainboard/google/snow/romstage.c | 10 +++++++++- 6 files changed, 13 insertions(+), 35 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 7e11536..3aff95c 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,14 +3,11 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -# Clock init is done in bootblock to support UART output for -# debugging. We may add a Kconfig option to disable clock init -# in the bootblock and try moving it entirely into romstage. -bootblock-y += clock_init.c +# clock and clock_init are included for SPI to work. bootblock-y += clock.c -bootblock-y += pinmux.c -bootblock-y += power.c -bootblock-y += soc.c +bootblock-y += clock_init.c +bootblock-$(CONFIG_EARLY_CONSOLE) += pinmux.c +bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index 621576d..0f4200c 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,5 +1,4 @@ bootblock-y += pwm.c -bootblock-y += s3c24x0_i2c.c bootblock-y += s5p_gpio.c bootblock-y += timer.c diff --git a/src/drivers/maxim/max77686/Makefile.inc b/src/drivers/maxim/max77686/Makefile.inc index 097b291..a5d7b90 100644 --- a/src/drivers/maxim/max77686/Makefile.inc +++ b/src/drivers/maxim/max77686/Makefile.inc @@ -17,6 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -bootblock-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c romstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c ramstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 04bf543..b56a1a4 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,10 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# needed for system_clock_init() -bootblock-y += mainboard.c -bootblock-y += memory.c - romstage-y += mainboard.c romstage-y += memory.c romstage-y += romstage.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 0bee055..b220112 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,32 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <arch/io.h> -#include <device/i2c.h> -#include <cpu/samsung/exynos5250/clk.h> -#include <cpu/samsung/exynos5250/dmc.h> -#include <cpu/samsung/exynos5250/periph.h> -#include <cpu/samsung/exynos5250/clock_init.h> -#include <src/cpu/samsung/exynos5250/power.h> -#include <drivers/maxim/max77686/max77686.h> #include <console/console.h> -#define I2C0_BASE 0x12c60000 - void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - struct mem_timings *mem; - struct arm_clk_ratios *arm_ratios; - - i2c_set_early_reg(I2C0_BASE); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - power_init(); - mem = get_mem_timings(); - arm_ratios = get_arm_clk_ratios(); - system_clock_init(mem, arm_ratios); - console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index b8e5116..c96dc2b 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -24,6 +24,7 @@ #include <cbfs.h> #include <common.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/setup.h> @@ -47,9 +48,10 @@ static int board_wakeup_permitted(void) void main(void) { - struct mem_timings *mem; int ret; void *entry; + struct mem_timings *mem; + struct arm_clk_ratios *arm_ratios; console_init(); printk(BIOS_INFO, "hello from romstage\n"); @@ -59,6 +61,12 @@ void main(void) printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); while(1); } + arm_ratios = get_arm_clk_ratios(); + system_clock_init(mem, arm_ratios); + + /* Re-initialize console in case clock is changed. */ + console_init(); + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", mem->mem_manuf, mem->mem_type,

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Patch set updated for coreboot: 61eceae armv7: Use same console initialization procedure for all ARM stages
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2301 -gerrit commit 61eceaea681580196d4b526b5d0f5fec69e70e83 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 22:01:18 2013 +0800 armv7: Use same console initialization procedure for all ARM stages Use same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> ... console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages. Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 9 ++-- src/arch/armv7/bootblock_simple.c | 2 + src/arch/armv7/include/common.h | 13 ------ src/arch/armv7/lib/Makefile.inc | 6 +-- src/arch/armv7/lib/early_console.c | 81 +++++++++++++++++++++++++++++++++ src/arch/armv7/lib/romstage_console.c | 73 ----------------------------- src/cpu/samsung/exynos5-common/uart.h | 2 - src/cpu/samsung/exynos5250/Makefile.inc | 13 ++---- src/cpu/samsung/exynos5250/uart.c | 4 +- src/include/uart.h | 5 +- src/mainboard/google/snow/bootblock.c | 12 ++--- src/mainboard/google/snow/ramstage.c | 4 +- 12 files changed, 102 insertions(+), 122 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 7d02e7c..0471b94 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -223,17 +223,18 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \ + -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ + $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index fe2662e..0132b87 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -23,6 +23,7 @@ #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> +#include <console/console.h> #include "stages.c" @@ -46,6 +47,7 @@ void main(void) bootblock_mainboard_init(); } + console_init(); printk(BIOS_INFO, "hello from bootblock\n"); printk(BIOS_INFO, "bootblock main(): loading romstage\n"); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index d95a74d..d8698db 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -422,19 +422,6 @@ int strcmp_compar(const void *, const void *); /* lib/time.c */ void udelay (unsigned long); -#if 0 -/* lib/vsprintf.c */ -ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2), noreturn)); -int sprintf(char * buf, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); -int vsprintf(char *buf, const char *fmt, va_list args); -#endif - /* lib/strmhz.c */ char * strmhz(char *buf, unsigned long hz); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 343e9f8..048e071 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,14 +1,12 @@ bootblock-y += syslib.c -bootblock-y += romstage_console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += romstage_console.c romstage-y += syslib.c - -#ramstage-y += printk_init.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c ramstage-y += div64.S diff --git a/src/arch/armv7/lib/early_console.c b/src/arch/armv7/lib/early_console.c new file mode 100644 index 0000000..68e81c6 --- /dev/null +++ b/src/arch/armv7/lib/early_console.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif +} + +static void _console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + _console_tx_flush(); + + return i; +} diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c deleted file mode 100644 index b0ac34e..0000000 --- a/src/arch/armv7/lib/romstage_console.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> -// TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_CONSOLE_SERIAL -#include <uart.h> -#endif -#if CONFIG_USBDEBUG -#include <usbdebug.h> -#endif - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_byte(byte); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_CBMEM - cbmemc_tx_byte(byte); -#endif -} - -static void _console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_flush(); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_flush(0); -#endif -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h index 52da62d..350e224 100644 --- a/src/cpu/samsung/exynos5-common/uart.h +++ b/src/cpu/samsung/exynos5-common/uart.h @@ -52,6 +52,4 @@ static inline int s5p_uart_divslot(void) return 0; } -void uart_init(void); - #endif diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e2033ff..7e11536 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,7 +11,7 @@ bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += power.c bootblock-y += soc.c -bootblock-y += uart.c +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c @@ -19,23 +19,18 @@ romstage-y += exynos_cache.c romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c -romstage-y += uart.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -#ramstage-y += clock.c -#ramstage-y += clock_init.c -#ramstage-y += power.c -#ramstage-y += uart.c -#ramstage-y += pinmux.c -##ramstage-y += tzpc_init.c +#ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c -ramstage-y += uart.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3126d7a..dacdc10 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,6 +28,8 @@ #include <console/console.h> /* for __console definition */ #include <cpu/samsung/exynos5-common/exynos5-common.h> +#include <cpu/samsung/exynos5-common/uart.h> +#include <cpu/samsung/exynos5250/uart.h> #include <cpu/samsung/exynos5250/clk.h> #define RX_FIFO_COUNT_MASK 0xff @@ -188,7 +190,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -#if !defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) +#if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, diff --git a/src/include/uart.h b/src/include/uart.h index e424496..ca5191e 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,14 +30,11 @@ #include <uart8250.h> #endif -#if CONFIG_CPU_SAMSUNG_EXYNOS5 -#include <cpu/samsung/exynos5-common/uart.h> -#endif - #if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); +void uart_init(void); #endif #endif /* UART_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index ff5e4a0..be5a99f 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,12 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> -#include <cbfs.h> -#include <uart.h> -#include <console/console.h> #include <device/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -30,9 +26,9 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <src/cpu/samsung/exynos5250/power.h> #include <drivers/maxim/max77686/max77686.h> +#include <console/console.h> #define I2C0_BASE 0x12c60000 -#endif void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) @@ -46,10 +42,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - -#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - uart_init(); + + console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); -#endif } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 50050d3..f9d9c96 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -24,9 +24,7 @@ void main(void) // volatile unsigned long *pshold = (unsigned long *)0x1004330c; // *pshold &= ~0x100; /* shut down */ - /* FIXME: console_init() seems to cause things to die... Maybe - we need to reset our stack pointer? */ -// console_init(); + console_init(); printk(BIOS_INFO, "hello from ramstage\n"); while (1); }

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Patch set updated for coreboot: dba6c3e console: Always allow setting "EARLY_CONSOLE" configuration.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2307 -gerrit commit dba6c3edf452d2958aad6b44aab937f0c6c4e00e Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Feb 7 13:41:56 2013 +0800 console: Always allow setting "EARLY_CONSOLE" configuration. Early console should always be allowed to be turned on / off (for generating production and debug versions), and should not be enforced by "select" Kconfig rule. A new "DEFAULT_EARLY_CONSOLE" is introduced for devices to select if they prefer early console output by default. Verified Kconfig value on qemu/x86 (default y by CACHE_AS_RAM), snow/x86 (default y by EXYNOS5 config), and intel/jarrell (default n). Change-Id: Ib1cc76d4ec115a302b95e7317224f1a40d1ab035 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/console/Kconfig | 6 +++++- src/cpu/Kconfig | 2 +- src/cpu/samsung/Kconfig | 4 +--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index e57d568..7fbed4a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,8 +1,12 @@ menu "Console" +config DEFAULT_EARLY_CONSOLE + bool + default n + config EARLY_CONSOLE bool "Enable early (pre-RAM) console output." - default n + default DEFAULT_EARLY_CONSOLE help Use console during early (pre-RAM) boot stages diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c2c3816..f60ffe7 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,7 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_CONSOLE + select DEFAULT_EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index c905b2a..c2ee5b4 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -6,9 +6,7 @@ config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS select HAVE_UART_SPECIAL - # TODO remove EARLY_CONSOLE when we can run ramstage without early UART - # init. - select EARLY_CONSOLE + select DEFAULT_EARLY_CONSOLE bool default n

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Advice
by aidas karpavicius 07 Feb '13

07 Feb '13

Hello, Id like my pc to boot straight to linux distro without grub or lilo. But if I wanted I could change to boot to windows. But my knowledge in hardware and c is beginner to intermediate. And my mb isnt supported asus p5n-e sli. So im not sure should I even attempt to try and get it done? Thanks, aidas

2 1

Patch set updated for coreboot: 2c163ee armv7/snow: Simplify bootblock.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2308 -gerrit commit 2c163ee172674709fbb9a0f4b522744c4f615515 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Feb 7 13:22:29 2013 +0800 armv7/snow: Simplify bootblock. I2C, power, and max77686 are not required for bootblock to initialize. We only need SPI and clock to load romstage. Change-Id: Ic863e222871a157ba4279a673775b1e18c6eac0d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 11 ++++------- src/cpu/samsung/exynos5250/uart.c | 4 ++++ src/cpu/samsung/s5p-common/Makefile.inc | 1 - src/drivers/maxim/max77686/Makefile.inc | 1 - src/mainboard/google/snow/Makefile.inc | 4 ---- src/mainboard/google/snow/bootblock.c | 22 ---------------------- src/mainboard/google/snow/romstage.c | 15 ++++++++++++--- 7 files changed, 20 insertions(+), 38 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 7e11536..3aff95c 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,14 +3,11 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -# Clock init is done in bootblock to support UART output for -# debugging. We may add a Kconfig option to disable clock init -# in the bootblock and try moving it entirely into romstage. -bootblock-y += clock_init.c +# clock and clock_init are included for SPI to work. bootblock-y += clock.c -bootblock-y += pinmux.c -bootblock-y += power.c -bootblock-y += soc.c +bootblock-y += clock_init.c +bootblock-$(CONFIG_EARLY_CONSOLE) += pinmux.c +bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index dacdc10..a6ff139 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -121,6 +121,10 @@ static void exynos5_init_dev(void) // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); struct s5p_uart *uart = (struct s5p_uart *)base_port; + // TODO setup pinmux properly by dev_index and base_port, or move this + // to console driver. + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index 621576d..0f4200c 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,5 +1,4 @@ bootblock-y += pwm.c -bootblock-y += s3c24x0_i2c.c bootblock-y += s5p_gpio.c bootblock-y += timer.c diff --git a/src/drivers/maxim/max77686/Makefile.inc b/src/drivers/maxim/max77686/Makefile.inc index 097b291..a5d7b90 100644 --- a/src/drivers/maxim/max77686/Makefile.inc +++ b/src/drivers/maxim/max77686/Makefile.inc @@ -17,6 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -bootblock-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c romstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c ramstage-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686.c diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 04bf543..b56a1a4 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,10 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# needed for system_clock_init() -bootblock-y += mainboard.c -bootblock-y += memory.c - romstage-y += mainboard.c romstage-y += memory.c romstage-y += romstage.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index be5a99f..b220112 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,33 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <arch/io.h> -#include <device/i2c.h> -#include <cpu/samsung/exynos5250/clk.h> -#include <cpu/samsung/exynos5250/dmc.h> -#include <cpu/samsung/exynos5250/periph.h> -#include <cpu/samsung/exynos5250/clock_init.h> -#include <src/cpu/samsung/exynos5250/power.h> -#include <drivers/maxim/max77686/max77686.h> #include <console/console.h> -#define I2C0_BASE 0x12c60000 - void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { - struct mem_timings *mem; - struct arm_clk_ratios *arm_ratios; - - i2c_set_early_reg(I2C0_BASE); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - power_init(); - mem = get_mem_timings(); - arm_ratios = get_arm_clk_ratios(); - system_clock_init(mem, arm_ratios); - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index b8e5116..20f4e81 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -24,6 +24,8 @@ #include <cbfs.h> #include <common.h> +#include <arch/hlt.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/setup.h> @@ -47,9 +49,10 @@ static int board_wakeup_permitted(void) void main(void) { - struct mem_timings *mem; int ret; void *entry; + struct mem_timings *mem; + struct arm_clk_ratios *arm_ratios; console_init(); printk(BIOS_INFO, "hello from romstage\n"); @@ -57,8 +60,14 @@ void main(void) mem = get_mem_timings(); if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); - while(1); + hlt(); } + arm_ratios = get_arm_clk_ratios(); + system_clock_init(mem, arm_ratios); + + /* Re-initialize console in case clock is changed. */ + console_init(); + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", mem->mem_manuf, mem->mem_type, @@ -69,7 +78,7 @@ void main(void) if (ret) { printk(BIOS_ERR, "Memory controller init failed, err: %x\n", ret); - while(1); + hlt(); } printk(BIOS_INFO, "ddr3_init done\n");

1 0

Patch set updated for coreboot: bacef77 armv7: Use same console initialization procedure for all ARM stages
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2301 -gerrit commit bacef772a106e6f7c6be6fc5cc1057280211312b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 22:01:18 2013 +0800 armv7: Use same console initialization procedure for all ARM stages Uses same console initialization procedure for all ARM stages (bootblock, romstage, and ramstage): #include <console/console.h> console_init() ... printk(level, format, ...) Verified to boot on armv7/snow with console messages in all stages (bootblock, romstage, ramstage). Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 9 ++-- src/arch/armv7/bootblock_simple.c | 2 + src/arch/armv7/include/common.h | 13 ------ src/arch/armv7/lib/Makefile.inc | 6 +-- src/arch/armv7/lib/early_console.c | 81 +++++++++++++++++++++++++++++++++ src/arch/armv7/lib/romstage_console.c | 73 ----------------------------- src/cpu/samsung/exynos5-common/uart.h | 2 - src/cpu/samsung/exynos5250/Makefile.inc | 13 ++---- src/cpu/samsung/exynos5250/uart.c | 4 +- src/include/uart.h | 5 +- src/mainboard/google/snow/bootblock.c | 12 ++--- src/mainboard/google/snow/ramstage.c | 4 +- 12 files changed, 102 insertions(+), 122 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 7d02e7c..0471b94 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -223,17 +223,18 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \ + -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ + $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index fe2662e..0132b87 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -23,6 +23,7 @@ #include <arch/hlt.h> #include <arch/stages.h> #include <cbfs.h> +#include <console/console.h> #include "stages.c" @@ -46,6 +47,7 @@ void main(void) bootblock_mainboard_init(); } + console_init(); printk(BIOS_INFO, "hello from bootblock\n"); printk(BIOS_INFO, "bootblock main(): loading romstage\n"); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index d95a74d..d8698db 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -422,19 +422,6 @@ int strcmp_compar(const void *, const void *); /* lib/time.c */ void udelay (unsigned long); -#if 0 -/* lib/vsprintf.c */ -ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2), noreturn)); -int sprintf(char * buf, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); -int vsprintf(char *buf, const char *fmt, va_list args); -#endif - /* lib/strmhz.c */ char * strmhz(char *buf, unsigned long hz); diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 343e9f8..048e071 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,14 +1,12 @@ bootblock-y += syslib.c -bootblock-y += romstage_console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c romstage-y += div64.S -romstage-y += romstage_console.c romstage-y += syslib.c - -#ramstage-y += printk_init.c +romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c ramstage-y += div64.S diff --git a/src/arch/armv7/lib/early_console.c b/src/arch/armv7/lib/early_console.c new file mode 100644 index 0000000..68e81c6 --- /dev/null +++ b/src/arch/armv7/lib/early_console.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif +} + +static void _console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + _console_tx_flush(); + + return i; +} diff --git a/src/arch/armv7/lib/romstage_console.c b/src/arch/armv7/lib/romstage_console.c deleted file mode 100644 index b0ac34e..0000000 --- a/src/arch/armv7/lib/romstage_console.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/vtxprintf.h> -// TODO Unify with x86 (CONFIG_CONSOLE_SERIAL8250) -#if CONFIG_CONSOLE_SERIAL -#include <uart.h> -#endif -#if CONFIG_USBDEBUG -#include <usbdebug.h> -#endif - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_byte(byte); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_CBMEM - cbmemc_tx_byte(byte); -#endif -} - -static void _console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL_UART - uart_tx_flush(); -#endif -#if CONFIG_USBDEBUG - usbdebug_tx_flush(0); -#endif -} - -int do_printk(int msg_level, const char *fmt, ...) -{ - va_list args; - int i; - - if (msg_level > console_loglevel) { - return 0; - } - - va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); - va_end(args); - - _console_tx_flush(); - - return i; -} diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h index 52da62d..350e224 100644 --- a/src/cpu/samsung/exynos5-common/uart.h +++ b/src/cpu/samsung/exynos5-common/uart.h @@ -52,6 +52,4 @@ static inline int s5p_uart_divslot(void) return 0; } -void uart_init(void); - #endif diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index e2033ff..7e11536 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,7 +11,7 @@ bootblock-y += clock.c bootblock-y += pinmux.c bootblock-y += power.c bootblock-y += soc.c -bootblock-y += uart.c +bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c @@ -19,23 +19,18 @@ romstage-y += exynos_cache.c romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c -romstage-y += uart.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -#ramstage-y += clock.c -#ramstage-y += clock_init.c -#ramstage-y += power.c -#ramstage-y += uart.c -#ramstage-y += pinmux.c -##ramstage-y += tzpc_init.c +#ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c -ramstage-y += uart.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3126d7a..dacdc10 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,6 +28,8 @@ #include <console/console.h> /* for __console definition */ #include <cpu/samsung/exynos5-common/exynos5-common.h> +#include <cpu/samsung/exynos5-common/uart.h> +#include <cpu/samsung/exynos5250/uart.h> #include <cpu/samsung/exynos5250/clk.h> #define RX_FIFO_COUNT_MASK 0xff @@ -188,7 +190,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -#if !defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) +#if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, diff --git a/src/include/uart.h b/src/include/uart.h index e424496..ca5191e 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -30,14 +30,11 @@ #include <uart8250.h> #endif -#if CONFIG_CPU_SAMSUNG_EXYNOS5 -#include <cpu/samsung/exynos5-common/uart.h> -#endif - #if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); +void uart_init(void); #endif #endif /* UART_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index ff5e4a0..be5a99f 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,12 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_EARLY_CONSOLE #include <types.h> #include <arch/io.h> -#include <cbfs.h> -#include <uart.h> -#include <console/console.h> #include <device/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> @@ -30,9 +26,9 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <src/cpu/samsung/exynos5250/power.h> #include <drivers/maxim/max77686/max77686.h> +#include <console/console.h> #define I2C0_BASE 0x12c60000 -#endif void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) @@ -46,10 +42,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - -#if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - uart_init(); + + console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); -#endif } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 50050d3..f9d9c96 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -24,9 +24,7 @@ void main(void) // volatile unsigned long *pshold = (unsigned long *)0x1004330c; // *pshold &= ~0x100; /* shut down */ - /* FIXME: console_init() seems to cause things to die... Maybe - we need to reset our stack pointer? */ -// console_init(); + console_init(); printk(BIOS_INFO, "hello from ramstage\n"); while (1); }

1 0

Patch set updated for coreboot: 8ca59b3 console: Only print romstage messages with EARLY_CONSOLE enabled.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2300 -gerrit commit 8ca59b3bb6ce791404d465fadda841ef1c93697b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 21:51:15 2013 +0800 console: Only print romstage messages with EARLY_CONSOLE enabled. Revise console source file dependency (especially for EARLY_CONSOLE) and interpret printk/console_init according to EARLY_CONSOLE setting (no-ops if EARLY_CONSOLE is not defined). Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly stops romstage messages on x86/qemu (armv7/snow needs more changes to work). Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/x86/lib/Makefile.inc | 2 +- src/console/Makefile.inc | 9 ++++----- src/console/console.c | 6 ++++-- src/include/console/console.h | 11 +++++++++++ src/include/uart.h | 4 ++-- 5 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index f4dc8b8..49d7e9e 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -10,7 +10,7 @@ ramstage-y += memcpy.c ramstage-y += ebda.c ramstage-y += rom_media.c -romstage-y += romstage_console.c +romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 8e6037a..9499180 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,14 +9,13 @@ smm-y += printk.c smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c -romstage-y += vtxprintf.c -romstage-$(CONFIG_EARLY_CONSOLE) += console.c +romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +romstage-y += console.c romstage-y += post.c romstage-y += die.c -# TODO Add vtxprintf.c only when early console is required. -bootblock-y += vtxprintf.c -bootblock-$(CONFIG_EARLY_CONSOLE) += console.c +bootblock-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +bootblock-y += console.c bootblock-y += die.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c diff --git a/src/console/console.c b/src/console/console.c index d4b4b88..aec711b 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,10 +99,10 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined -#include <uart.h> - void console_init(void) { +#if CONFIG_EARLY_CONSOLE + #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); @@ -127,5 +127,7 @@ void console_init(void) COREBOOT_BUILD " starting...\n"; print_info(console_test); + +#endif /* CONFIG_EARLY_CONSOLE */ } #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index edd49e0..496571b 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -74,6 +74,15 @@ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +#if defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE + +static inline void printk(int LEVEL, const char *fmt, ...); +static inline void printk(int LEVEL, const char *fmt, ...) { + /* Do nothing. */ +} + +#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ + #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS /* We saw some strange effects in the past like coreboot crashing while * disabling cache as ram for a maximum console log level of 6 and above while @@ -109,6 +118,8 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, } while(0) #endif +#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ + #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) #define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) diff --git a/src/include/uart.h b/src/include/uart.h index 2a72575..e424496 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -26,7 +26,7 @@ #ifndef UART_H #define UART_H -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -34,7 +34,7 @@ #include <cpu/samsung/exynos5-common/uart.h> #endif -#ifndef __ROMCC__ +#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void);

1 0

Patch set updated for coreboot: cff87d2 console: Always allow setting "EARLY_CONSOLE" configuration.
by Hung-Te Lin 07 Feb '13

07 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2307 -gerrit commit cff87d2ebdec88743db2dc988d0a65092db79f79 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Feb 7 13:41:56 2013 +0800 console: Always allow setting "EARLY_CONSOLE" configuration. Early console should always be allowed to be turned on / off (for generating production and debug versions), not enforced by "select" Kconfig rule. A new "DEFAULT_EARLY_CONSOLE" is introduced for devices to select if they prefer early console output by default. Verified Kconfig value on qemu/x86 (default y by CACHE_AS_RAM), snow/x86 (default y by EXYNOS5 config), and intel/jarrell (default n). Change-Id: Ib1cc76d4ec115a302b95e7317224f1a40d1ab035 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/console/Kconfig | 6 +++++- src/cpu/Kconfig | 2 +- src/cpu/samsung/Kconfig | 4 +--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index e57d568..7fbed4a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,8 +1,12 @@ menu "Console" +config DEFAULT_EARLY_CONSOLE + bool + default n + config EARLY_CONSOLE bool "Enable early (pre-RAM) console output." - default n + default DEFAULT_EARLY_CONSOLE help Use console during early (pre-RAM) boot stages diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c2c3816..f60ffe7 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,7 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_CONSOLE + select DEFAULT_EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index c905b2a..c2ee5b4 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -6,9 +6,7 @@ config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS select HAVE_UART_SPECIAL - # TODO remove EARLY_CONSOLE when we can run ramstage without early UART - # init. - select EARLY_CONSOLE + select DEFAULT_EARLY_CONSOLE bool default n

1 0

New patch to review for coreboot: 47bc079 spi.h: Rename the spi.h to spi-generic.h
by Zheng Bao 07 Feb '13

07 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2309 -gerrit commit 47bc0798c515a9b6611a7b619c5f7f5849075552 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Feb 7 17:30:23 2013 +0800 spi.h: Rename the spi.h to spi-generic.h Since there are and will be other files in nb/sb folders, we change the general spi.h to a file name which is not easy to be duplicated. Change-Id: I6548a81206caa608369be044747bde31e2b08d1a Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 2 +- src/drivers/elog/elog.c | 2 +- src/drivers/spi/spi_flash.c | 2 +- src/include/spi-generic.h | 204 +++++++++++++++++++++++++++ src/include/spi.h | 204 --------------------------- src/include/spi_flash.h | 2 +- src/northbridge/intel/sandybridge/mrccache.c | 2 +- src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/intel/bd82x6x/finalize.c | 2 +- src/southbridge/intel/bd82x6x/spi.c | 2 +- 12 files changed, 214 insertions(+), 214 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 42e950f..dd90184 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -41,7 +41,7 @@ #include "agesawrapper.h" #ifndef __PRE_RAM__ -#include <spi.h> +#include <spi-generic.h> #include <spi_flash.h> #endif diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index e6baace..1a794d9 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> #include <smbios.h> -#include <spi.h> +#include <spi-generic.h> #include <spi_flash.h> #include <stdint.h> #include <string.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 6b658f8..d1a9504 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -9,7 +9,7 @@ #include <stdlib.h> #include <string.h> -#include <spi.h> +#include <spi-generic.h> #include <spi_flash.h> #include <delay.h> #ifdef __SMM__ diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h new file mode 100644 index 0000000..d394531 --- /dev/null +++ b/src/include/spi-generic.h @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPI_H_ +#define _SPI_H_ + +#include <stdint.h> + +/* Controller-specific definitions: */ + +/* SPI mode flags */ +#define SPI_CPHA 0x01 /* clock phase */ +#define SPI_CPOL 0x02 /* clock polarity */ +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH 0x04 /* CS active high */ +#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ +#define SPI_3WIRE 0x10 /* SI/SO signals shared */ +#define SPI_LOOP 0x20 /* loopback mode */ + +/* SPI transfer flags */ +#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ +#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ + +/* SPI opcodes */ +#define SPI_OPCODE_WREN 0x06 +#define SPI_OPCODE_FAST_READ 0x0b + +#define SPI_READ_FLAG 0x01 +#define SPI_WRITE_FLAG 0x02 + +/*----------------------------------------------------------------------- + * Representation of a SPI slave, i.e. what we're communicating with. + * + * Drivers are expected to extend this with controller-specific data. + * + * bus: ID of the bus that the slave is attached to. + * cs: ID of the chip select connected to the slave. + * rw: Read or Write flag + */ +struct spi_slave { + unsigned int bus; + unsigned int cs; + unsigned int rw; +}; + +/*----------------------------------------------------------------------- + * Initialization, must be called once on start up. + * + */ +void spi_init(void); + +/*----------------------------------------------------------------------- + * Set up communications parameters for a SPI slave. + * + * This must be called once for each slave. Note that this function + * usually doesn't touch any actual hardware, it only initializes the + * contents of spi_slave so that the hardware can be easily + * initialized later. + * + * bus: Bus ID of the slave chip. + * cs: Chip select ID of the slave chip on the specified bus. + * max_hz: Maximum SCK rate in Hz. + * mode: Clock polarity, clock phase and other parameters. + * + * Returns: A spi_slave reference that can be used in subsequent SPI + * calls, or NULL if one or more of the parameters are not supported. + */ +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); + +/*----------------------------------------------------------------------- + * Claim the bus and prepare it for communication with a given slave. + * + * This must be called before doing any transfers with a SPI slave. It + * will enable and initialize any SPI hardware as necessary, and make + * sure that the SCK line is in the correct idle state. It is not + * allowed to claim the same bus for several slaves without releasing + * the bus in between. + * + * slave: The SPI slave + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ +int spi_claim_bus(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Release the SPI bus + * + * This must be called once for every call to spi_claim_bus() after + * all transfers have finished. It may disable any SPI hardware as + * appropriate. + * + * slave: The SPI slave + */ +void spi_release_bus(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks + * "bitlen" bits in the SPI MISO port. That's just the way SPI works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that "dout" + * and "din" can point to the same memory location, in which case the + * input data overwrites the output data (since both are buffered by + * temporary variables, this is OK). + * + * spi_xfer() interface: + * slave: The SPI slave which will be sending/receiving the data. + * dout: Pointer to a string of bits to send out. The bits are + * held in a byte array and are sent MSB first. + * bitsout: How many bits to write. + * din: Pointer to a string of bits that will be filled in. + * bitsin: How many bits to read. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, + void *din, unsigned int bitsin); + +/*----------------------------------------------------------------------- + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs); + +/*----------------------------------------------------------------------- + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Set transfer speed. + * This sets a new speed to be applied for next spi_xfer(). + * slave: The SPI slave + * hz: The transfer speed + */ +void spi_set_speed(struct spi_slave *slave, uint32_t hz); + +/*----------------------------------------------------------------------- + * Write 8 bits, then read 8 bits. + * slave: The SPI slave we're communicating with + * byte: Byte to be written + * + * Returns: The value that was read, or a negative value on error. + * + * TODO: This function probably shouldn't be inlined. + */ +static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) +{ + unsigned char dout[2]; + unsigned char din[2]; + int ret; + + dout[0] = byte; + dout[1] = 0; + + ret = spi_xfer(slave, dout, 16, din, 16); + return ret < 0 ? ret : din[1]; +} + +#endif /* _SPI_H_ */ diff --git a/src/include/spi.h b/src/include/spi.h deleted file mode 100644 index d394531..0000000 --- a/src/include/spi.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPI_H_ -#define _SPI_H_ - -#include <stdint.h> - -/* Controller-specific definitions: */ - -/* SPI mode flags */ -#define SPI_CPHA 0x01 /* clock phase */ -#define SPI_CPOL 0x02 /* clock polarity */ -#define SPI_MODE_0 (0|0) /* (original MicroWire) */ -#define SPI_MODE_1 (0|SPI_CPHA) -#define SPI_MODE_2 (SPI_CPOL|0) -#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) -#define SPI_CS_HIGH 0x04 /* CS active high */ -#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ -#define SPI_3WIRE 0x10 /* SI/SO signals shared */ -#define SPI_LOOP 0x20 /* loopback mode */ - -/* SPI transfer flags */ -#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ -#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ - -/* SPI opcodes */ -#define SPI_OPCODE_WREN 0x06 -#define SPI_OPCODE_FAST_READ 0x0b - -#define SPI_READ_FLAG 0x01 -#define SPI_WRITE_FLAG 0x02 - -/*----------------------------------------------------------------------- - * Representation of a SPI slave, i.e. what we're communicating with. - * - * Drivers are expected to extend this with controller-specific data. - * - * bus: ID of the bus that the slave is attached to. - * cs: ID of the chip select connected to the slave. - * rw: Read or Write flag - */ -struct spi_slave { - unsigned int bus; - unsigned int cs; - unsigned int rw; -}; - -/*----------------------------------------------------------------------- - * Initialization, must be called once on start up. - * - */ -void spi_init(void); - -/*----------------------------------------------------------------------- - * Set up communications parameters for a SPI slave. - * - * This must be called once for each slave. Note that this function - * usually doesn't touch any actual hardware, it only initializes the - * contents of spi_slave so that the hardware can be easily - * initialized later. - * - * bus: Bus ID of the slave chip. - * cs: Chip select ID of the slave chip on the specified bus. - * max_hz: Maximum SCK rate in Hz. - * mode: Clock polarity, clock phase and other parameters. - * - * Returns: A spi_slave reference that can be used in subsequent SPI - * calls, or NULL if one or more of the parameters are not supported. - */ -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); - -/*----------------------------------------------------------------------- - * Claim the bus and prepare it for communication with a given slave. - * - * This must be called before doing any transfers with a SPI slave. It - * will enable and initialize any SPI hardware as necessary, and make - * sure that the SCK line is in the correct idle state. It is not - * allowed to claim the same bus for several slaves without releasing - * the bus in between. - * - * slave: The SPI slave - * - * Returns: 0 if the bus was claimed successfully, or a negative value - * if it wasn't. - */ -int spi_claim_bus(struct spi_slave *slave); - -/*----------------------------------------------------------------------- - * Release the SPI bus - * - * This must be called once for every call to spi_claim_bus() after - * all transfers have finished. It may disable any SPI hardware as - * appropriate. - * - * slave: The SPI slave - */ -void spi_release_bus(struct spi_slave *slave); - -/*----------------------------------------------------------------------- - * SPI transfer - * - * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks - * "bitlen" bits in the SPI MISO port. That's just the way SPI works. - * - * The source of the outgoing bits is the "dout" parameter and the - * destination of the input bits is the "din" parameter. Note that "dout" - * and "din" can point to the same memory location, in which case the - * input data overwrites the output data (since both are buffered by - * temporary variables, this is OK). - * - * spi_xfer() interface: - * slave: The SPI slave which will be sending/receiving the data. - * dout: Pointer to a string of bits to send out. The bits are - * held in a byte array and are sent MSB first. - * bitsout: How many bits to write. - * din: Pointer to a string of bits that will be filled in. - * bitsin: How many bits to read. - * - * Returns: 0 on success, not 0 on failure - */ -int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, - void *din, unsigned int bitsin); - -/*----------------------------------------------------------------------- - * Determine if a SPI chipselect is valid. - * This function is provided by the board if the low-level SPI driver - * needs it to determine if a given chipselect is actually valid. - * - * Returns: 1 if bus:cs identifies a valid chip on this board, 0 - * otherwise. - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs); - -/*----------------------------------------------------------------------- - * Activate a SPI chipselect. - * This function is provided by the board code when using a driver - * that can't control its chipselects automatically (e.g. - * common/soft_spi.c). When called, it should activate the chip select - * to the device identified by "slave". - */ -void spi_cs_activate(struct spi_slave *slave); - -/*----------------------------------------------------------------------- - * Deactivate a SPI chipselect. - * This function is provided by the board code when using a driver - * that can't control its chipselects automatically (e.g. - * common/soft_spi.c). When called, it should deactivate the chip - * select to the device identified by "slave". - */ -void spi_cs_deactivate(struct spi_slave *slave); - -/*----------------------------------------------------------------------- - * Set transfer speed. - * This sets a new speed to be applied for next spi_xfer(). - * slave: The SPI slave - * hz: The transfer speed - */ -void spi_set_speed(struct spi_slave *slave, uint32_t hz); - -/*----------------------------------------------------------------------- - * Write 8 bits, then read 8 bits. - * slave: The SPI slave we're communicating with - * byte: Byte to be written - * - * Returns: The value that was read, or a negative value on error. - * - * TODO: This function probably shouldn't be inlined. - */ -static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) -{ - unsigned char dout[2]; - unsigned char din[2]; - int ret; - - dout[0] = byte; - dout[1] = 0; - - ret = spi_xfer(slave, dout, 16, din, 16); - return ret < 0 ? ret : din[1]; -} - -#endif /* _SPI_H_ */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index b84bd96..6fd9f13 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -26,7 +26,7 @@ #include <stdint.h> #include <stddef.h> #include <console/console.h> -#include <spi.h> +#include <spi-generic.h> /** * container_of - cast a member of a structure out to the containing structure diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 30d28ad..ea3b38d 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -26,7 +26,7 @@ #include <cbmem.h> #include "pei_data.h" #include "sandybridge.h" -#include <spi.h> +#include <spi-generic.h> #include <spi_flash.h> #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index aebe4b5..dabf8b7 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -20,7 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> -#include <spi.h> +#include <spi-generic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 1966eb4..a8c3b61 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -163,7 +163,7 @@ typedef union _PCI_ADDR { #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" #if CONFIG_HAVE_ACPI_RESUME -#include "spi.h" +#include <spi-generic.h> #endif #define BIOSRAM_INDEX 0xcd4 diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 46cc741..d4b80f9 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -20,7 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> -#include <spi.h> +#include <spi-generic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 4a4f021..f627972 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -23,7 +23,7 @@ #include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" -#include "spi.h" +#include <spi-generic.h> void intel_pch_finalize_smm(void) { diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 05649fc..4303dd0 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -29,7 +29,7 @@ #include <console/console.h> #include <device/pci_ids.h> -#include <spi.h> +#include <spi-generic.h> #define min(a, b) ((a)<(b)?(a):(b))

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coreboot February 2013