coreboot February 2013

coreboot@coreboot.org

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790 discussions

Patch set updated for coreboot: 2ba0a70 crossgcc: Save the script itself when cross build is over.
by Zheng Bao 06 Feb '13

06 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2247 -gerrit commit 2ba0a707295e6ac144c1aec0ca5c92b06089297e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Wed Feb 6 17:06:34 2013 +0800 crossgcc: Save the script itself when cross build is over. In case that the new toolchains don't work well, we can trace back and reproduce the old tools by checking the xgcc folder. It is useful when my team members need to get my old toolchains on their own host machines. Change-Id: I54e4bc6afcfbbf622165af6eae27bbb6efc2e8cc Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/crossgcc/buildgcc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c69e7cd..9e9229a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -595,6 +595,8 @@ test -r $IASL_DIR/generate/unix/.failed && printf "${RED}failed${NC}\n" || \ test -r $IASL_DIR/generate/unix/.failed && exit 1 fi +cp $0 $DESTDIR$TARGETDIR/$0.commit.`git describe` + if [ $SAVETEMPS -eq 0 ]; then printf "Cleaning up... " rm -rf ${GMP_DIR} build-gmp

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New patch to review for coreboot: 76150be armv7: Prevent CBFS data overlapping bootblock.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2295 -gerrit commit 76150be9534747d0d7df44d679eed9ffc1a67375 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 12:41:49 2013 +0800 armv7: Prevent CBFS data overlapping bootblock. For arm/snow, current bootblock is larger than previously assigned CBFS offset and will fail to boot. To prevent this happening again in future, cbfstool now checks if CBFS will overlap bootblock. A sample error message: E: Bootblock (0x0+0x71d4) overlap CBFS data (0x5000) E: Failed to create build/coreboot.pre1.tmp. arm/snow offset is also enlarged and moved to Kconfig variable. Change-Id: I4556aef27ff716556040312ae8ccb78078abc82d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 6 ++++-- src/cpu/samsung/exynos5250/Kconfig | 5 +++++ util/cbfstool/cbfs_image.c | 6 ++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index f2f4a47..7d02e7c 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -45,10 +45,12 @@ prebuild-files = \ $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -# TODO Change -b, -H, -o to Kconfig variables. +# TODO Change -b to Kconfig variable. $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ - -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 -H 0x2040 -o 0x5000 + -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \ + -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ + -o $(CONFIG_CBFS_ROM_OFFSET) $(prebuild-files) true mv $@.tmp $@ else diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 477ee51..6a09d88 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -48,6 +48,11 @@ config ROMSTAGE_SIZE hex default 0x10000 +config CBFS_ROM_OFFSET + # Calculated by BL1 + max bootblock size. + hex "offset of CBFS data in ROM" + default 0x0A000 + # TODO Change this to some better address not overlapping bootblock when # cbfstool supports creating header in arbitrary location. config CBFS_HEADER_ROM_OFFSET diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index b7c6ee5..5c2ac26 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -174,6 +174,12 @@ int cbfs_image_create(struct cbfs_image *image, bootblock_offset, bootblock->size, size); return -1; } + if (entries_offset > bootblock_offset && + entries_offset < bootblock->size) { + ERROR("Bootblock (0x%x+0x%zx) overlap CBFS data (0x%x)\n", + bootblock_offset, bootblock->size, entries_offset); + return -1; + } memcpy(image->buffer.data + bootblock_offset, bootblock->data, bootblock->size);

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New patch to review for coreboot: 61ca34c cbfs: Revise debug messages.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2294 -gerrit commit 61ca34ca885b28bd22dad4e98776d55d0f7ca880 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 12:25:27 2013 +0800 cbfs: Revise debug messages. Some variables are using incorrect data type in debug messages. Also corrects a typo (extra 'x'). Change-Id: Ia3014ea018f8c1e4733c54a7d9ee196d0437cfbb Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/lib/cbfs.c | 6 +++--- src/lib/cbfs_core.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 4702f1e..bfdab6c 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -177,8 +177,8 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, struct cbfs_media *media, size_t offset, size_t count) { void *address = buffer->buffer + buffer->allocated;; - DEBUG("simple_buffer_map(offset=%d, count=%d): " - "allocated=%d, size=%d, last_allocate=%d\n", + DEBUG("simple_buffer_map(offset=%zd, count=%zd): " + "allocated=%zd, size=%zd, last_allocate=%zd\n", offset, count, buffer->allocated, buffer->size, buffer->last_allocate); if (buffer->allocated + count >= buffer->size) @@ -198,7 +198,7 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, // TODO Add simple buffer management so we can free more than last // allocated one. DEBUG("simple_buffer_unmap(address=0x%p): " - "allocated=%d, size=%d, last_allocate=%d\n", + "allocated=%zd, size=%zd, last_allocate=%zd\n", address, buffer->allocated, buffer->size, buffer->last_allocate); if ((buffer->buffer + buffer->allocated - buffer->last_allocate) == diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 6e4f489..42b8c09 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -132,7 +132,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) uint32_t new_align = align; if (offset % align) new_align += align - (offset % align); - ERROR("ERROR: No file header found at 0x%xx - " + ERROR("ERROR: No file header found at 0x%x - " "try next aligned address: 0x%x.\n", offset, offset + new_align); offset += new_align;

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Patch set updated for coreboot: dde8521 cbfs: Fix CBFS max size calculation.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2292 -gerrit commit dde852182905579a420a8055a248acf5a7bc55ae Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 12:11:57 2013 +0800 cbfs: Fix CBFS max size calculation. For x86, the old CBFS search behavior was to bypass bootblock and we should keep that. This will speed up searching if a file does not exist in CBFS. For arm, the size in header is correct now so we can remove the hack by CONFIG_ROM_SIZE. Change-Id: I541961bc4dd083a583f8a80b69e293694fb055ef Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/lib/cbfs_core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 6e4f489..1fd004f 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -116,12 +116,12 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) align = ntohl(header->align); romsize = ntohl(header->romsize); - // TODO header->romsize seems broken now on ARM. Remove this when it's - // fixed. -#if defined(CONFIG_ARCH_ARMV7) && CONFIG_ARCH_ARMV7 - romsize = CONFIG_ROM_SIZE; + // TODO Add a "size" in CBFS header for a platform independent way to + // determine the end of CBFS data. +#if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 + romsize -= htonl(header->bootblocksize); #endif - DEBUG("offset: 0x%x, align: %d, romsize: %d\n", offset, align, romsize); + DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); LOG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media);

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New patch to review for coreboot: 2a29e77 AMD Fam14 - Fix warnings
by Martin Roth 06 Feb '13

06 Feb '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2293 -gerrit commit 2a29e779732b0e8f9672bfc5fc44e69a8208ace2 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Feb 5 21:06:21 2013 -0700 AMD Fam14 - Fix warnings Added casts and a couple of #ifdefs to fix the warnings in the vendorcode/amd/agesa/f14 codebase. This will allow us to re-enable 'all warnings being treated as errors' in boards such as Persimmon that are using this code. That change will follow. Verified on persimmon. Change-Id: I1671b191c72dfc1d63ada41126ae3418bc8f86ae Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/vendorcode/amd/agesa/f14/AGESA.h | 4 ++++ .../amd/agesa/f14/Legacy/Proc/hobTransfer.c | 6 +++--- .../amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 4 ++-- .../amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c | 19 ++++++++++--------- 5 files changed, 20 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 511be69..5eaa638 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -1129,8 +1129,12 @@ typedef enum { ///< CPU MSR Register definitions ------------------------------------------ #define SYS_CFG 0xC0010010 +#ifndef TOP_MEM #define TOP_MEM 0xC001001A +#endif +#ifndef TOP_MEM2 #define TOP_MEM2 0xC001001D +#endif #define HWCR 0xC0010015 #define NB_CFG 0xC001001F diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c index d3987fb..bb23204 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c @@ -216,7 +216,7 @@ CopyHeapToTempRamAtPost ( HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - BaseAddressInTempMem = (UINT8 *) (UserOptions.CfgHeapDramAddress); + BaseAddressInTempMem = (UINT8 *) (intptr_t) (UserOptions.CfgHeapDramAddress); HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); @@ -369,7 +369,7 @@ CopyHeapToMainRamAtPost ( HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; } // if address of heap in temp memory is above 1M, then we must used one variable MTRR. - if (StdHeader->HeapBasePtr >= 0x100000) { + if (StdHeader->HeapBasePtr >= (void *) 0x100000) { // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); @@ -378,7 +378,7 @@ CopyHeapToMainRamAtPost ( HeapRamVariableMtrr--) { LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == ((UINT64)(StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) && + if ((VariableMtrrBase == ((UINT64) (intptr_t) (StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) && (VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { break; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c index 40c395d..0b9b9c6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c @@ -860,7 +860,7 @@ ApUtilSetupIdtForHlt ( DescSize = 8; } - HandlerOffset = (UINT64)&NmiHandler; + HandlerOffset = (UINT64) (intptr_t) &NmiHandler; NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF); NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF); GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); @@ -869,7 +869,7 @@ ApUtilSetupIdtForHlt ( NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32); NmiIdtDescPtr->Rsvd64 = 0; IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1); - IdtInfo.Base = (UINT64) NmiIdtDescPtr - (DescSize * 2); + IdtInfo.Base = (UINT64) (intptr_t) NmiIdtDescPtr - (DescSize * 2); SetIdtr (&IdtInfo , StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c index 4116a6e..bc15447 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c @@ -208,7 +208,7 @@ LoadMicrocode ( PATCH_LOADER PatchLoaderMsr; // Load microcode patch into CPU - PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr; + PatchLoaderMsr.RawData = (UINT64) (intptr_t) MicrocodePatchPtr; PatchLoaderMsr.BitFields.SBZ = 0; LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c index 57e1838..f6b409f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c @@ -164,7 +164,8 @@ HeapManagerInit ( LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) { LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { + if (((UINT64) (intptr_t) MsrData & CacheInfoPtr->HeapBaseMask) == + ((UINT64) (intptr_t) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) { // This is not a bug, there are multiple premem basic entry points, // and each will call heap init to make sure create struct will succeed. @@ -180,7 +181,7 @@ HeapManagerInit ( } // Set variable MTRR base and mask - MsrData = ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); + MsrData = ((UINT64) (intptr_t)HeapBufferPtr & CacheInfoPtr->HeapBaseMask); MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; MsrData |= 0x06; @@ -666,34 +667,34 @@ VOID // Firstly, we try to see if heap is in cache BaseAddress = HeapGetCurrentBase (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) && (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) && (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) { // Secondly, we try to see if heap is in temp memory BaseAddress = UserOptions.CfgHeapDramAddress; - HeapManager = (HEAP_MANAGER *) BaseAddress; + HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // Thirdly, we try to see if heap in main memory // by locating with external buffer manager (IBV) AgesaBuffer.StdHeader = *StdHeader; AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) { - BaseAddress = (UINT64) AgesaBuffer.BufferPointer; - HeapManager = (HEAP_MANAGER *) BaseAddress; + BaseAddress = (UINT64) (intptr_t) AgesaBuffer.BufferPointer; + HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress; if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { // No valid heap signature ever found, return a NULL pointer - BaseAddress = NULL; + BaseAddress = (UINT64) (intptr_t) NULL; } } else { // No heap buffer is allocated by external manager (IBV), return a NULL pointer - BaseAddress = NULL; + BaseAddress = (UINT64) (intptr_t) NULL; } } } - return BaseAddress; + return (void *) (intptr_t) BaseAddress; } /*---------------------------------------------------------------------------------------

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New patch to review for coreboot: bb5780d cbfs: Fix CBFS max size calculation.
by Hung-Te Lin 06 Feb '13

06 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2292 -gerrit commit bb5780da0d2fa7ef3b2ffa90a0aa88b85f6d023c Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Feb 6 12:11:57 2013 +0800 cbfs: Fix CBFS max size calculation. The old CBFS search behavior was to bypass bootblock, and we should keep that. This will speed up searching if a file does not exist in CBFS. Change-Id: I541961bc4dd083a583f8a80b69e293694fb055ef Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/lib/cbfs_core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 6e4f489..1fd004f 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -116,12 +116,12 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) align = ntohl(header->align); romsize = ntohl(header->romsize); - // TODO header->romsize seems broken now on ARM. Remove this when it's - // fixed. -#if defined(CONFIG_ARCH_ARMV7) && CONFIG_ARCH_ARMV7 - romsize = CONFIG_ROM_SIZE; + // TODO Add a "size" in CBFS header for a platform independent way to + // determine the end of CBFS data. +#if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 + romsize -= htonl(header->bootblocksize); #endif - DEBUG("offset: 0x%x, align: %d, romsize: %d\n", offset, align, romsize); + DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); LOG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media);

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Patch merged into coreboot/master: d87d639 replace uchar and uint with standard types in generic i2c header
by gerrit＠coreboot.org 06 Feb '13

06 Feb '13

the following patch was just integrated into master: commit d87d639e262544ec0b4f2fc06fa7d43e217c8333 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Feb 5 15:17:56 2013 -0800 replace uchar and uint with standard types in generic i2c header Change-Id: Ie72985bb5291bcef2e837a2f4f2ec929a0c086ce Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Feb 6 01:03:42 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Feb 6 02:11:38 2013, giving +2 See http://review.coreboot.org/2290 for details. -gerrit

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Patch merged into coreboot/master: 0d4f97e exynos/snow: Move core/memory clock-related and board ID code
by gerrit＠coreboot.org 06 Feb '13

06 Feb '13

the following patch was just integrated into master: commit 0d4f97e27045209fdb9af452b013a6cfaebcaebc Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 18:09:58 2013 -0800 exynos/snow: Move core/memory clock-related and board ID code This patch moves ARM core and DRAM timing functions around to simplify the dependencies for system_clock_init(). The original code was architected such that the system_clock_init() function called other functions to obtain core and memory timings. Due to the way memory timing information must be obtained on Snow, which entails decoding platform-specific board straps, the bottom- up approach resulted in having the low-level clock init code implicitly depend on board and vendor-specific info: main() ->system_clock_init() -> get_arm_ratios() -> CPU-specific code -> clock_get_mem_timings() -> board_get_revision() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table ...then proceed to init clocks ...come back to main() The new approach gathers all board and vendor-specific info in a more appropriate location and passes it into system_clock_init(): main() -> get_arm_ratios() -> CPU-specific code -> get_mem_timings() -> board_get_config() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table -> system_clock_init() ...back to main() Change-Id: Ie237ebff76fc2d8a4d2f4577a226ac3909e4d4e8 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2271 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Feb 6 00:56:25 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Feb 6 02:11:14 2013, giving +2 See http://review.coreboot.org/2271 for details. -gerrit

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New patch to review for coreboot: 56ebe77 snow: remove dead code from bootblock
by David Hendricks 05 Feb '13

05 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2291 -gerrit commit 56ebe779e9c770995268a8cf739ffa2d509014ad Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Feb 5 15:24:54 2013 -0800 snow: remove dead code from bootblock This attempts to clean out some dead code which was copy + pasted into Snow's bootblock.c file, along with some unnecessary headers. Since the max77686 driver and vtxprintf are not built when bootblock-y is set, those will remain for now. Change-Id: If9f157a52395a047c249a2a6385e0e8ddf310e59 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 94 ++++------------------------------- 1 file changed, 9 insertions(+), 85 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 90a2de1..b29af1b 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -17,90 +17,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> #include <types.h> -#include <assert.h> -#include <arch/armv7/include/common.h> #include <arch/io.h> -#include "cpu/samsung/exynos5250/clk.h" -#include "cpu/samsung/exynos5250/cpu.h" -#include "cpu/samsung/exynos5250/dmc.h" -#include "cpu/samsung/exynos5250/gpio.h" -#include "cpu/samsung/exynos5250/periph.h" -#include "cpu/samsung/exynos5250/setup.h" -#include "cpu/samsung/exynos5250/clock_init.h" -#include "cpu/samsung/s5p-common/gpio.h" -#include "cpu/samsung/s5p-common/s3c24x0_i2c.h" -#include "cpu/samsung/exynos5-common/spi.h" - -#include <device/i2c.h> -#include <drivers/maxim/max77686/max77686.h> +#include <cbfs.h> #include <uart.h> - #include <console/console.h> -#include <cbfs.h> - -#define EXYNOS5_CLOCK_BASE 0x10010000 - -#define CONFIG_SYS_CLK_FREQ 24000000 - -void puts(const char *s); -void puts(const char *s) -{ - int n = 0; - - while (*s) { - if (*s == '\n') { - uart_tx_byte(0xd); /* CR */ - } - - uart_tx_byte(*s++); - n++; - } -} - -static void do_serial(void) -{ - //exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - gpio_set_pull(GPIO_A14, EXYNOS_GPIO_PULL_NONE); - gpio_cfg_pin(GPIO_A15, EXYNOS_GPIO_FUNC(0x2)); - - uart_init(); -} +#include <device/i2c.h> +#include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/dmc.h> +#include <cpu/samsung/exynos5250/periph.h> +#include <cpu/samsung/exynos5250/clock_init.h> +#include <drivers/maxim/max77686/max77686.h> #define I2C0_BASE 0x12c60000 -void do_barriers(void); -void do_barriers(void) -{ - /* - * The reason we don't write out the instructions dsb/isb/sev: - * While ARM Cortex-A8 supports ARM v7 instruction set (-march=armv7a), - * we compile with -march=armv5 to allow more compilers to work. - * For U-Boot code this has no performance impact. - */ - __asm__ __volatile__( -#if defined(__thumb__) - ".hword 0xF3BF, 0x8F4F\n" /* dsb; darn -march=armv5 */ - ".hword 0xF3BF, 0x8F6F\n" /* isb; darn -march=armv5 */ - ".hword 0xBF40\n" /* sev; darn -march=armv5 */ -#else - ".word 0xF57FF04F\n" /* dsb; darn -march=armv5 */ - ".word 0xF57FF06F\n" /* isb; darn -march=armv5 */ - ".word 0xE320F004\n" /* sev; darn -march=armv5 */ -#endif - ); -} - -/* is this right? meh, it seems to work well enough... */ -void my_udelay(unsigned int n); -void my_udelay(unsigned int n) -{ - n *= 1000; - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (n):"0"(n)); -} - /* * Max77686 parameters values * see max77686.h for parameters details @@ -359,13 +289,6 @@ static void power_init(void) #define is_digit isdigit #define isxdigit(c) (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || ((c) >= 'A' && (c) <= 'F')) -void __div0 (void); -void __div0 (void) -{ - puts("divide by zero detected"); - while(1) ; -} - static int skip_atoi(const char **s) { int i=0; @@ -649,7 +572,8 @@ void bootblock_mainboard_init(void) mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); - do_serial(); + exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + uart_init(); printk(BIOS_INFO, "%s: UART initialized\n", __func__); #if 0

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New patch to review for coreboot: c3f4f59 replace uchar and uint with standard types in generic i2c header
by David Hendricks 05 Feb '13

05 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2290 -gerrit commit c3f4f59e1fa7be4e7cd4f255ccb20c609bba5d14 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Feb 5 15:17:56 2013 -0800 replace uchar and uint with standard types in generic i2c header Change-Id: Ie72985bb5291bcef2e837a2f4f2ec929a0c086ce Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/device/i2c.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index f1275e3..bd6dd0c 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -116,8 +116,8 @@ void i2c_board_late_init(void); #if defined(CONFIG_I2C_MUX) typedef struct _mux { - uchar chip; - uchar channel; + unsigned char chip; + unsigned char channel; char *name; struct _mux *next; } I2C_MUX; @@ -129,16 +129,16 @@ typedef struct _mux_device { } I2C_MUX_DEVICE; I2C_MUX_DEVICE *i2c_mux_search_device(int id); -I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf); +I2C_MUX_DEVICE *i2c_mux_ident_muxstring (unsigned char *buf); int i2x_mux_select_mux(int bus); -int i2c_mux_ident_muxstring_f (uchar *buf); +int i2c_mux_ident_muxstring_f (unsigned char *buf); #endif /* * Probe the given I2C chip address. Returns 0 if a chip responded, * not 0 on failure. */ -int i2c_probe(uchar chip); +int i2c_probe(unsigned char chip); /* * Read/Write interface: @@ -152,8 +152,10 @@ int i2c_probe(uchar chip); * * Returns: 0 on success, not 0 on failure */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_read(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +int i2c_write(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); /* * Utility routines to read/write registers.

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coreboot February 2013