coreboot February 2013

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Patch merged into coreboot/master: 4c2aafe exynos: de-duplicate UART header content
by gerrit＠coreboot.org 05 Feb '13

05 Feb '13

the following patch was just integrated into master: commit 4c2aafe586d5214409b4de0affb5f743477d2f1c Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 4 20:40:47 2013 -0800 exynos: de-duplicate UART header content Some header content got duplicated during the initial porting effort. This moves generic UART header stuff to exynos5-common and leaves exynos5250 #defines in the AP-specific UART header. Change-Id: Ifb6289d7b9dc26c76ae4dfcf511590b3885715a3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2285 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue Feb 5 23:28:45 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 5 23:30:48 2013, giving +2 See http://review.coreboot.org/2285 for details. -gerrit

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New patch to review for coreboot: 2a32142 snow: use bootblock build class for UART code
by David Hendricks 05 Feb '13

05 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2286 -gerrit commit 2a32142abe1ab0bae18441d6b9dc2a1ffc8ce9f3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 4 20:42:12 2013 -0800 snow: use bootblock build class for UART code This gets rid of a bunch of copy + pasted code from Exynos UART files. Change-Id: I9fbb6d79a40a338c9fdecd495544ff207909fd37 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 2 + src/cpu/samsung/exynos5250/uart.c | 2 +- src/mainboard/google/snow/bootblock.c | 127 ++------------------------------ 3 files changed, 8 insertions(+), 123 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 3dcf461..39e1c7e 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -8,6 +8,8 @@ # in the bootblock and try moving it entirely into romstage. bootblock-y += clock_init.c bootblock-y += clock.c +bootblock-y += soc.c +bootblock-y += uart.c romstage-y += clock.c romstage-y += clock_init.c diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index b219f48..f3ee081 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -188,7 +188,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -#ifndef __PRE_RAM__ +#if !defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) static const struct console_driver exynos5_uart_console __console = { .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 58d347d..2855ddb 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -32,10 +32,10 @@ #include "cpu/samsung/s5p-common/gpio.h" #include "cpu/samsung/s5p-common/s3c24x0_i2c.h" #include "cpu/samsung/exynos5-common/spi.h" -#include "cpu/samsung/exynos5-common/uart.h" #include <device/i2c.h> #include <drivers/maxim/max77686/max77686.h> +#include <uart.h> #include <console/console.h> #include <cbfs.h> @@ -124,125 +124,8 @@ void gpio_set_pull(int gpio, int mode) writel(value, &bank->pull); } -static uint32_t uart3_base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - #define CONFIG_SYS_CLK_FREQ 24000000 -static void serial_setbrg_dev(void) -{ -// struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - struct s5p_uart *uart = (struct s5p_uart *)uart3_base; - u32 uclk; - u32 baudrate = CONFIG_TTYS0_BAUD; - u32 val; -// enum periph_id periph; - -// periph = exynos5_get_periph_id(base_port); - uclk = clock_get_periph_rate(PERIPH_ID_UART3); - val = uclk / baudrate; - - writel(val / 16 - 1, &uart->ubrdiv); - - /* - * FIXME(dhendrix): the original uart.h had a "br_rest" value which - * does not seem relevant to the exynos5250... not entirely sure - * where/if we need to worry about it here - */ -#if 0 - if (s5p_uart_divslot()) - writew(udivslot[val % 16], &uart->rest.slot); - else - writeb(val % 16, &uart->rest.value); -#endif -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -static void exynos5_init_dev(void) -{ -// struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - struct s5p_uart *uart = (struct s5p_uart *)uart3_base; - - /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); - - serial_setbrg_dev(); -} - -static int exynos5_uart_err_check(int op) -{ - //struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - struct s5p_uart *uart = (struct s5p_uart *)uart3_base; - unsigned int mask; - - /* - * UERSTAT - * Break Detect [3] - * Frame Err [2] : receive operation - * Parity Err [1] : receive operation - * Overrun Err [0] : receive operation - */ - if (op) - mask = 0x8; - else - mask = 0xf; - - return readl(&uart->uerstat) & mask; -} - -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) - -#if 0 -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static unsigned char exynos5_uart_rx_byte(void) -{ -// struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - struct s5p_uart *uart = (struct s5p_uart *)uart3_base; - - /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | - RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) - return 0; - } - - return readb(&uart->urxh) & 0xff; -} -#endif - -/* - * Output a single byte to the serial port. - */ -static void exynos5_uart_tx_byte(unsigned char data) -{ -// struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - struct s5p_uart *uart = (struct s5p_uart *)uart3_base; - - if (data == '\n') - exynos5_uart_tx_byte('\r'); - - /* wait for room in the tx FIFO */ - while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) - return; - } - - writeb(data, &uart->utxh); -} - void puts(const char *s); void puts(const char *s) { @@ -250,10 +133,10 @@ void puts(const char *s) while (*s) { if (*s == '\n') { - exynos5_uart_tx_byte(0xd); /* CR */ + uart_tx_byte(0xd); /* CR */ } - exynos5_uart_tx_byte(*s++); + uart_tx_byte(*s++); n++; } } @@ -264,7 +147,7 @@ static void do_serial(void) gpio_set_pull(GPIO_A14, EXYNOS_GPIO_PULL_NONE); gpio_cfg_pin(GPIO_A15, EXYNOS_GPIO_FUNC(0x2)); - exynos5_init_dev(); + uart_init(); } #define I2C_WRITE 0 @@ -1616,7 +1499,7 @@ int do_printk(int msg_level, const char *fmt, ...) int i; va_start(args, fmt); - i = vtxprintf(exynos5_uart_tx_byte, fmt, args); + i = vtxprintf(uart_tx_byte, fmt, args); va_end(args); return i;

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New patch to review for coreboot: f6a7e6a exynos: de-duplicate UART header content
by David Hendricks 05 Feb '13

05 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2285 -gerrit commit f6a7e6ab549758e9d01a75beea94976d27b0b921 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 4 20:40:47 2013 -0800 exynos: de-duplicate UART header content Some header content got duplicated during the initial porting effort. This moves generic UART header stuff to exynos5-common and leaves exynos5250 #defines in the AP-specific UART header. Change-Id: Ifb6289d7b9dc26c76ae4dfcf511590b3885715a3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/uart.h | 2 ++ src/cpu/samsung/exynos5250/uart.h | 41 ++--------------------------------- src/include/uart.h | 2 +- 3 files changed, 5 insertions(+), 40 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h index 350e224..52da62d 100644 --- a/src/cpu/samsung/exynos5-common/uart.h +++ b/src/cpu/samsung/exynos5-common/uart.h @@ -52,4 +52,6 @@ static inline int s5p_uart_divslot(void) return 0; } +void uart_init(void); + #endif diff --git a/src/cpu/samsung/exynos5250/uart.h b/src/cpu/samsung/exynos5250/uart.h index 033d605..1d872d7 100644 --- a/src/cpu/samsung/exynos5250/uart.h +++ b/src/cpu/samsung/exynos5250/uart.h @@ -23,50 +23,13 @@ * from u-boot. */ -#ifndef __EXYNOS5_UART_H_ -#define __EXYNOS5_UART_H_ +#ifndef __EXYNOS5250_UART_H_ +#define __EXYNOS5250_UART_H_ -#include <types.h> - -/* FIXME: should these move into a Kconfig file? */ #define EXYNOS5_UART0_BASE 0x12c00000 #define EXYNOS5_UART1_BASE 0x12c10000 #define EXYNOS5_UART2_BASE 0x12c20000 #define EXYNOS5_UART3_BASE 0x12c30000 #define EXYNOS5_ISP_UART_BASE 0x13190000 -#if 0 -/* baudrate rest value */ -union br_rest { - unsigned short slot; /* udivslot */ - unsigned char value; /* ufracval */ -}; -#endif - -struct s5p_uart { - uint32_t ulcon; - uint32_t ucon; - uint32_t ufcon; - uint32_t umcon; - uint32_t utrstat; - uint32_t uerstat; - uint32_t ufstat; - uint32_t umstat; - uint8_t utxh; - uint8_t res1[3]; - uint8_t urxh; - uint8_t res2[3]; - uint32_t ubrdiv; - uint32_t ufracval; - uint32_t uintp; - uint32_t uints; - uint32_t uintm; -}; - -static inline int s5p_uart_divslot(void) -{ - return 0; -} - -void uart_init(void); #endif diff --git a/src/include/uart.h b/src/include/uart.h index 6628314..2a72575 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -31,7 +31,7 @@ #endif #if CONFIG_CPU_SAMSUNG_EXYNOS5 -#include <cpu/samsung/exynos5250/uart.h> +#include <cpu/samsung/exynos5-common/uart.h> #endif #ifndef __ROMCC__

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New patch to review for coreboot: 11330db Don't add another Kconfig special case for Tiano
by Stefan Reinauer 05 Feb '13

05 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2284 -gerrit commit 11330db62191be27f1442dcd7000d399800452b4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Feb 5 13:58:29 2013 -0800 Don't add another Kconfig special case for Tiano We don't need a special Kconfig variable anymore because the FV _is_ the payload, unlike with the old tianocoreboot implementation. Change-Id: I349b5a95783e4146e3ab7f926871188cf2021935 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 14 +++++++------- src/arch/x86/Makefile.inc | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 95afbe1..92bdf11 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -536,13 +536,6 @@ config FILO_MASTER Newest FILO version endchoice -config TIANOCORE_FILE - string "Tianocore FILE" - depends on PAYLOAD_TIANOCORE - default "COREBOOT.FD" - help - The result of a corebootPkg build - config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF @@ -558,6 +551,13 @@ config PAYLOAD_FILE depends on PAYLOAD_FILO default "payloads/external/FILO/filo/build/filo.elf" +config PAYLOAD_FILE + string "Tianocore firmware volume" + depends on PAYLOAD_TIANOCORE + default "COREBOOT.fd" + help + The result of a corebootPkg build + # TODO: Defined if no payload? Breaks build? config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 67789ce..419507b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -101,7 +101,7 @@ ifeq ($(CONFIG_PAYLOAD_FILO),y) endif ifeq ($(CONFIG_PAYLOAD_TIANOCORE),y) @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_TIANOCORE_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n"

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New patch to review for coreboot: 27ddadd cbfstool: Add support for 64bit UEFI
by Stefan Reinauer 05 Feb '13

05 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2283 -gerrit commit 27ddaddd5092babf1b11d5e4bcfaad5471747295 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Feb 5 13:46:49 2013 -0800 cbfstool: Add support for 64bit UEFI Right now cbfstool only accepts firmware volumes with a x86 SEC core and refuses an x86-64 SEC core because some magic values and the extended PE header are different. With this patch, both IA32/x64 images are supported. (No check is done whether the mainboard actually supports 64bit CPUs, so careful!) This needs another patch to Tiano Core that switches to long mode after jumping to the 64bit entry point. Right now that code assumes we're already in 64bit code and the machine crashes. Change-Id: I1e55f1ce1a31682f182f58a9c791ad69b2a1c536 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/cbfs-mkpayload.c | 49 +++++++++++++++++++++++++++--------------- util/cbfstool/coff.h | 40 +++++++++++++++++++++++++++++++++- 2 files changed, 71 insertions(+), 18 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 99142f4..e207b3e 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -261,11 +261,10 @@ int parse_fv_to_payload(const struct buffer *input, common_section_header_t *cs; dos_header_t *dh; coff_header_t *ch; - pe_opt_header_t *ph; int dh_offset; - uint32_t loadaddress; - uint32_t entrypoint; + uint32_t loadaddress = 0; + uint32_t entrypoint = 0; compress = compression_function(algo); if (!compress) @@ -282,18 +281,21 @@ int parse_fv_to_payload(const struct buffer *input, fh = (ffs_file_header_t *)(input->data + fv->header_length); if (fh->file_type != FILETYPE_SEC) { ERROR("Not a usable UEFI firmware volume.\n"); + INFO("First file in first FV not a SEC core.\n"); return -1; } cs = (common_section_header_t *)&fh[1]; if (cs->section_type != SECTION_PE32) { ERROR("Not a usable UEFI firmware volume.\n"); + INFO("Section type not PE32.\n"); return -1; } dh = (dos_header_t *)&cs[1]; - if (dh->signature != 0x5a4d) { + if (dh->signature != DOS_MAGIC) { ERROR("Not a usable UEFI firmware volume.\n"); + INFO("DOS header signature wrong.\n"); return -1; } @@ -301,23 +303,36 @@ int parse_fv_to_payload(const struct buffer *input, DEBUG("dos header offset = %x\n", dh_offset); ch = (coff_header_t *)(((void *)dh)+dh->e_lfanew); - if (ch->machine != 0x14c) { - ERROR("Not a usable UEFI firmware volume.\n"); - return -1; - } - ph = (pe_opt_header_t *)&ch[1]; - if (ph->signature != 267) { - ERROR("Not a usable UEFI firmware volume.\n"); + if (ch->machine == MACHINE_TYPE_X86) { + pe_opt_header_32_t *ph; + ph = (pe_opt_header_32_t *)&ch[1]; + if (ph->signature != PE_HDR_32_MAGIC) { + WARN("PE header signature incorrect.\n"); + return -1; + } + DEBUG("image base %x\n", ph->image_addr); + DEBUG("entry point %x\n", ph->entry_point); + + loadaddress = ph->image_addr - dh_offset; + entrypoint = ph->image_addr + ph->entry_point; + } else if (ch->machine == MACHINE_TYPE_X64) { + pe_opt_header_64_t *ph; + ph = (pe_opt_header_64_t *)&ch[1]; + if (ph->signature != PE_HDR_64_MAGIC) { + WARN("PE header signature incorrect.\n"); + return -1; + } + DEBUG("image base %lx\n", (unsigned long)ph->image_addr); + DEBUG("entry point %x\n", ph->entry_point); + + loadaddress = ph->image_addr - dh_offset; + entrypoint = ph->image_addr + ph->entry_point; + } else { + ERROR("Machine type not x86 or x64.\n"); return -1; } - DEBUG("image base %x\n", ph->image_addr); - DEBUG("entry point %x\n", ph->entry_point); - - loadaddress = ph->image_addr - dh_offset; - entrypoint = ph->image_addr + ph->entry_point; - if (buffer_create(output, (2 * sizeof(*segs) + input->size), input->name) != 0) return -1; diff --git a/util/cbfstool/coff.h b/util/cbfstool/coff.h index ebe4538..0720c15 100644 --- a/util/cbfstool/coff.h +++ b/util/cbfstool/coff.h @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define DOS_MAGIC 0x5a4d typedef struct { uint16_t signature; uint16_t lastsize; @@ -39,6 +40,8 @@ typedef struct { uint32_t e_lfanew; } dos_header_t; +#define MACHINE_TYPE_X86 0x014c +#define MACHINE_TYPE_X64 0x8664 typedef struct { uint8_t signature[4]; uint16_t machine; @@ -50,6 +53,7 @@ typedef struct { uint16_t characteristics; } coff_header_t; +#define PE_HDR_32_MAGIC 0x10b typedef struct { uint16_t signature; uint8_t major_linker_version; @@ -82,5 +86,39 @@ typedef struct { uint32_t loader_flags; uint32_t number_of_va_and_sizes; /* data directory not needed */ -} pe_opt_header_t; +} pe_opt_header_32_t; + +#define PE_HDR_64_MAGIC 0x20b +typedef struct { + uint16_t signature; + uint8_t major_linker_version; + uint8_t minor_linker_version; + uint32_t code_size; + uint32_t data_size; + uint32_t bss_size; + uint32_t entry_point; + uint32_t code_offset; + uint64_t image_addr; + uint32_t section_alignment; + uint32_t file_alignment; + uint16_t major_os_version; + uint16_t minor_os_version; + uint16_t major_image_version; + uint16_t minor_image_version; + uint16_t major_subsystem_version; + uint16_t minor_subsystem_version; + uint32_t reserved; + uint32_t image_size; + uint32_t header_size; + uint32_t checksum; + uint16_t subsystem; + uint16_t characteristics; + uint64_t stack_reserve_size; + uint64_t stack_commit_size; + uint64_t heap_reserve_size; + uint64_t heap_commit_size; + uint32_t loader_flags; + uint32_t number_of_va_and_sizes; + /* data directory not needed */ +} pe_opt_header_64_t;

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Patch merged into coreboot/master: 543a682 cbfstool: support parsing UEFI firmware volumes
by gerrit＠coreboot.org 05 Feb '13

05 Feb '13

the following patch was just integrated into master: commit 543a6824580331373a2d77694c23905dc7ca48a7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Feb 4 15:39:13 2013 -0800 cbfstool: support parsing UEFI firmware volumes This removes the hack implemented in http://review.coreboot.org/#/c/2280 (and should make using 64bit Tiano easier, but that's not yet supported) Change-Id: Ie30129c4102dfbd41584177f39057b31f5a937fd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Feb 5 18:23:46 2013, giving +2 Build-Tested: build bot (Jenkins) at Tue Feb 5 00:48:38 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 5 22:42:25 2013, giving +2 See http://review.coreboot.org/2281 for details. -gerrit

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Patch merged into coreboot/master: c13e4bf cbfstool: Use cbfs_image API for "add-*" (add-payload, add-stage, ...) commands.
by gerrit＠coreboot.org 05 Feb '13

05 Feb '13

the following patch was just integrated into master: commit c13e4bf3e16080993fb42399327501201c4f9f13 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Jan 29 15:22:11 2013 +0800 cbfstool: Use cbfs_image API for "add-*" (add-payload, add-stage, ...) commands. add-payload, add-stage, and add-flat-binary are now all using cbfs_image API. To test: cbfstool coreboot.rom add-stage -f FILE -n fallback/romstage -b 0xXXXX cbfstool coreboot.rom add-payload -f FILE -n fallback/pyload And compare with old cbfstool. Verified to boot on ARM(snow) and X86(qemu-i386). Change-Id: If65cb495c476ef6f9d90c778531f0c3caf178281 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2220 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Feb 4 23:33:02 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 5 22:26:24 2013, giving +2 See http://review.coreboot.org/2220 for details. -gerrit

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Patch merged into coreboot/master: 5f3eb26 cbfstool: Use cbfs_image api for "add" command.
by gerrit＠coreboot.org 05 Feb '13

05 Feb '13

the following patch was just integrated into master: commit 5f3eb26d857628615e6c92180a2dc2213011dd09 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Jan 29 10:24:00 2013 +0800 cbfstool: Use cbfs_image api for "add" command. The "add" command is compatible with all legacy usage. Also, to support platforms without top-aligned address, all address-type params (-b, -H, -l) can now be ROM offset (address < 0x8000000) or x86 top-aligned address (address > 0x80000000). Example: cbfstool coreboot.rom add -f config -n config -t raw -b 0x2000 cbfstool coreboot.rom add -f stage -n newstage -b 0xffffd1c0 Verified boot-able on both ARM(snow) and x86(QEMU) system. Change-Id: I485e4e88b5e269494a4b138e0a83f793ffc5a084 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2216 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Feb 4 23:11:01 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 5 22:26:17 2013, giving +2 See http://review.coreboot.org/2216 for details. -gerrit

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Patch merged into coreboot/master: f56c73f cbfstool: Use cbfs_image API for "create" command.
by gerrit＠coreboot.org 05 Feb '13

05 Feb '13

the following patch was just integrated into master: commit f56c73f1e1c2b13c7b2b989fc44358138394cc68 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Jan 29 09:45:12 2013 +0800 cbfstool: Use cbfs_image API for "create" command. Usage Changes: To support platforms with different memory layout, "create" takes two extra optional parameters: "-b": base address (or offset) for bootblock. When omitted, put bootblock in end of ROM (x86 style). "-H": header offset. When omitted, put header right before bootblock, and update a top-aligned virtual address reference in end of ROM. Example: (can be found in ARM MAkefile): cbfstool coreboot.rom create -m armv7 -s 4096K -B bootblock.bin \ -a 64 -b 0x0000 -H 0x2040 -o 0x5000 Verified to boot on ARM (Snow) and X86 (QEMU). Change-Id: Ida2a9e32f9a459787b577db5e6581550d9d7017b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2214 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue Feb 5 00:09:07 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 5 22:26:06 2013, giving +2 See http://review.coreboot.org/2214 for details. -gerrit

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Patch merged into coreboot/master: 215d1d7 cbfstool: Use cbfs_image API for "locate" command.
by gerrit＠coreboot.org 05 Feb '13

05 Feb '13

the following patch was just integrated into master: commit 215d1d7c9b8fdd94582bdec711e98111d1db5bb7 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Jan 29 03:46:02 2013 +0800 cbfstool: Use cbfs_image API for "locate" command. To support platforms without top-aligned address mapping like ARM, "locate" command now outputs platform independent ROM offset by default. To retrieve x86 style top-aligned virtual address, add "-T". To test: cbfstool coreboot.rom locate -f stage -n stage -a 0x100000 -T # Example output: 0xffffdc10 Change-Id: I474703c4197b36524b75407a91faab1194edc64d Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2213 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue Feb 5 00:15:59 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Feb 5 22:25:53 2013, giving +2 See http://review.coreboot.org/2213 for details. -gerrit

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coreboot February 2013