the following patch was just integrated into master:
commit e89ffeebb93b987c833beaad39651cdd44f00cc5
Author: Anton Kochkov <a.kochkov(a)securitycode.ru>
Date: Fri Jul 6 11:54:17 2012 +0400
libpayload: Add reset function for OHCI USB driver
Implemented OHCI reset function ohci_reset() in ohci.c
for libpayload's USB driver.
Change-Id: Id6518cbe00a21202757b34926bad171909740e97
Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com>
See http://review.coreboot.org/1177 for details.
-gerrit
the following patch was just integrated into master:
commit d43938adbd704c81d438d370fda471578c44e90d
Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
Date: Tue Jul 10 10:14:17 2012 -0500
Lenovo X60: correct SDHCI write protect polarity
Change-Id: I916deffe2c692042f7e54c936902e77770ee69df
Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
See http://review.coreboot.org/1205 for details.
-gerrit
the following patch was just integrated into master:
commit e7ae433b4efa92e0649c092fa5aa05323350c355
Author: Guenter Roeck <linux(a)roeck-us.net>
Date: Fri Jun 29 12:24:57 2012 -0700
superiotool: Dump data registers for Nuvoton chips
Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F,
and NCT6779D). Register contents will be dumped if the -e option is provided on
the command line.
Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad
Signed-off-by: Guenter Roeck <linux(a)roeck-us.net>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Jul 12 08:13:21 2012, giving +2
See http://review.coreboot.org/1150 for details.
-gerrit
the following patch was just integrated into master:
commit 7eedcba9fb8b1bd1100dca290b4d3a8544ae14d5
Author: Guenter Roeck <linux(a)roeck-us.net>
Date: Fri Jun 29 12:23:50 2012 -0700
superiotool: Add support for function to dump superio chip data registers
Add new function dump_data() to dump a bank of superio data registers.
Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f
Signed-off-by: Guenter Roeck <linux(a)roeck-us.net>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Jul 12 08:13:13 2012, giving +2
See http://review.coreboot.org/1149 for details.
-gerrit
the following patch was just integrated into master:
commit 765e44dcb2e0f7be7a46e674cab28991e726c3a4
Author: Guenter Roeck <linux(a)roeck-us.net>
Date: Fri Jun 29 12:22:51 2012 -0700
superiotool: Add support for NCT6775F(A/B) and NCT6779D
Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11
Signed-off-by: Guenter Roeck <linux(a)roeck-us.net>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Jul 12 08:10:28 2012, giving +2
See http://review.coreboot.org/1148 for details.
-gerrit
the following patch was just integrated into master:
commit c0da995d1c10799eddfc450436d35358eacb619c
Author: Sven Schnelle <svens(a)stackframe.org>
Date: Wed Jul 11 21:41:06 2012 +0200
Fix stack assignment during CPU initialization
There are two errors in the code. The first one is a missing
$ sign in mov _stack, %esp. Thanks to Ronald G Minnich for
catching that bug.
The second bug is the 'incl %eax', which shouldn't be there, as
there's no secondary CPU with index 0. CPU0 uses always the stack
below _estack.
Change-Id: Id267a654ba95b0e898eeaaafb2403b438250a563
Signed-off-by: Sven Schnelle <svens(a)stackframe.org>
Build-Tested: build bot (Jenkins) at Wed Jul 11 22:11:39 2012, giving +1
See http://review.coreboot.org/1212 for details.
-gerrit
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1217
-gerrit
commit b8b5b1e535becc2ff11767dced0d2a875e4b763e
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 10 13:10:24 2012 +0300
AMD: Fix GFXUMA with 4GB or more RAM
Northbridge code incorrectly adjusted the last cacheable memory
resource to accomodate room for UMA framebuffer. If system had
4GB or more memory that last resource is not below 4GB and not
the one where UMA is located.
There are three consequences:
The last entry in coreboot memory table is reduced by uma_memory_size.
Due the incorrect code in northbridge code state.tomk,
end of last resource below 4GB, had not been adjusted.
Incrementing that by uma_memory_size diverts a region
possibly claimed for MMIO to RAM, as TOP_MEM is written.
Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
it was ignored from the MTRR setup and not set uncacheable.
The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
should be copied from BSP to all APs instead of deriving the data
separately for each Logical CPU.
Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/mtrr/amd_mtrr.c | 24 ++++++++++++++-----
src/northbridge/amd/agesa/family10/northbridge.c | 5 ----
src/northbridge/amd/agesa/family15/northbridge.c | 5 ----
src/northbridge/amd/agesa/family15tn/northbridge.c | 5 ----
src/northbridge/amd/amdfam10/northbridge.c | 5 ----
src/northbridge/amd/amdk8/northbridge.c | 12 +--------
6 files changed, 19 insertions(+), 37 deletions(-)
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index ec72425..f639d59 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -102,6 +102,20 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
}
+static void uma_fb_resource(void *gp, struct device *dev, struct resource *res)
+{
+ struct mem_state *state = gp;
+ unsigned long topk;
+
+ topk = resk(res->base + res->size);
+ if (state->tom2k < topk) {
+ state->tom2k = topk;
+ }
+ if ((topk < 4*1024*1024) && (state->tomk < topk)) {
+ state->tomk = topk;
+ }
+}
+
void amd_setup_mtrrs(void)
{
unsigned long address_bits;
@@ -133,6 +147,9 @@ void amd_setup_mtrrs(void)
state.tomk = state.tom2k = 0;
search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB,
+ uma_fb_resource, &state);
+ search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_fixed_mtrr_resource, &state);
@@ -144,13 +161,6 @@ void amd_setup_mtrrs(void)
state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
msr.hi = state.tomk >> 22;
msr.lo = state.tomk << 10;
- /* If UMA graphics is enabled, the frame buffer memory
- * has been deducted from the size of memory below 4GB.
- * When setting TOM, include UMA DRAM
- */
- #if CONFIG_GFXUMA
- msr.lo += uma_memory_size;
- #endif
wrmsr(TOP_MEM, msr);
/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 12d83ad..fb64757 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -1063,11 +1063,6 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA
- /* Deduct uma memory before reporting because
- * this is what the mtrr code expects */
- sizek -= uma_memory_size / 1024;
-#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index d9da183..0e18956 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -782,11 +782,6 @@ static void domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA
- /* Deduct uma memory before reporting because
- * this is what the mtrr code expects */
- sizek -= uma_memory_size / 1024;
-#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index efc8e68..0330017 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -768,11 +768,6 @@ static void domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA == 1
- /* Deduct uma memory before reporting because
- * this is what the mtrr code expects */
- sizek -= uma_memory_size / 1024;
-#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES==1
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 41434e8..39b4a40 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1051,11 +1051,6 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA
- /* Deduct uma memory before reporting because
- * this is what the mtrr code expects */
- sizek -= uma_memory_size / 1024;
-#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 8b9140d..36dd2b4 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -1030,16 +1030,8 @@ static void amdk8_domain_set_resources(device_t dev)
sizek -= (4*1024*1024 - mmio_basek);
}
}
- /* If sizek == 0, it was split at mmio_basek without a hole.
- * Don't create an empty ram_resource.
- */
-#if CONFIG_GFXUMA
- /* Deduct uma memory before reporting because
- * this is what the mtrr code expects */
- sizek -= uma_memory_size / 1024;
-#endif
- if (sizek)
- ram_resource(dev, (idx | i), basek, sizek);
+
+ ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",