coreboot July 2012

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Patch merged into coreboot/master: 891ea78 Drop start_cpu_lock
by gerrit＠coreboot.org 10 Jul '12

10 Jul '12

the following patch was just integrated into master: commit 891ea785344ce58984beb1653e248f9a163b4613 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 10 10:17:32 2012 +0300 Drop start_cpu_lock Function alloc_find_dev() is serialized. Change-Id: I40d27d1adca629f1f7ce2f09c1cb2fd04b76eb9a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jul 10 09:49:27 2012, giving +1 See http://review.coreboot.org/1198 for details. -gerrit

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New patch to review for coreboot: d43938a Lenovo X60: correct SDHCI write protect polarity
by Jonathan A. Kollasch 10 Jul '12

10 Jul '12

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1205 -gerrit commit d43938adbd704c81d438d370fda471578c44e90d Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Jul 10 10:14:17 2012 -0500 Lenovo X60: correct SDHCI write protect polarity Change-Id: I916deffe2c692042f7e54c936902e77770ee69df Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/include/device/pci_ids.h | 1 + src/mainboard/lenovo/x60/mainboard.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ee92594..fd886da 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1525,6 +1525,7 @@ #define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 #define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 #define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 +#define PCI_DEVICE_ID_RICOH_R5C822 0x0822 #define PCI_VENDOR_ID_ARTOP 0x1191 #define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index b45342a..453cf38 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -29,6 +29,7 @@ #include "chip.h" #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pci_ids.h> #include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> @@ -52,7 +53,7 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_enable(device_t dev) { - device_t dev0, idedev; + device_t dev0, idedev, sdhci_dev; u8 defaults_loaded = 0; ec_clr_bit(0x03, 2); @@ -79,6 +80,19 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0x04); } + /* Set SDHCI write protect polarity "SDWPPol" */ + sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0); + if (sdhci_dev) { + if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) { + /* unlock */ + pci_write_config8(sdhci_dev, 0xf9, 0xfc); + /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */ + pci_write_config8(sdhci_dev, 0xfa, 0x20); + /* restore lock */ + pci_write_config8(sdhci_dev, 0xf9, 0x00); + } + } + if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); defaults_loaded = 0;

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New patch to review for coreboot: 1d41941 Define uma_memory_base and uma_memory_size just once
by Kyösti Mälkki 10 Jul '12

10 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1204 -gerrit commit 1d419416ad63b40b73ff6b724f3d35963fbd73d7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 10 14:54:17 2012 +0300 Define uma_memory_base and uma_memory_size just once Use of the variables is very scattered. It may be possible to get rid of these two globals with a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/mtrr/amd_mtrr.c | 4 ---- src/cpu/x86/mtrr/mtrr.c | 4 ---- src/devices/device.c | 5 +++++ src/include/device/device.h | 4 ++++ src/mainboard/advansus/a785e-i/mainboard.c | 1 - src/mainboard/amd/bimini_fam10/mainboard.c | 1 - src/mainboard/amd/dbm690t/mainboard.c | 1 - src/mainboard/amd/dinar/mainboard.c | 1 - src/mainboard/amd/inagua/mainboard.c | 1 - src/mainboard/amd/mahogany/mainboard.c | 2 -- src/mainboard/amd/mahogany_fam10/mainboard.c | 2 -- src/mainboard/amd/persimmon/mainboard.c | 1 - src/mainboard/amd/pistachio/mainboard.c | 1 - src/mainboard/amd/south_station/mainboard.c | 1 - src/mainboard/amd/tilapia_fam10/mainboard.c | 2 -- src/mainboard/amd/torpedo/mainboard.c | 1 - src/mainboard/amd/union_station/mainboard.c | 1 - src/mainboard/asrock/939a785gmh/mainboard.c | 2 -- src/mainboard/asrock/e350m1/mainboard.c | 1 - src/mainboard/asus/m2v-mx_se/mainboard.c | 4 ---- src/mainboard/asus/m4a78-em/mainboard.c | 2 -- src/mainboard/asus/m4a785-m/mainboard.c | 2 -- src/mainboard/asus/m5a88-v/mainboard.c | 1 - src/mainboard/avalue/eax-785e/mainboard.c | 1 - src/mainboard/gigabyte/ma785gm/mainboard.c | 2 -- src/mainboard/gigabyte/ma785gmt/mainboard.c | 2 -- src/mainboard/gigabyte/ma78gm/mainboard.c | 2 -- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 -- src/mainboard/jetway/pa78vm5/mainboard.c | 2 -- src/mainboard/kontron/kt690/mainboard.c | 1 - src/mainboard/siemens/sitemp_g1p1/mainboard.c | 1 - src/mainboard/technexion/tim5690/mainboard.c | 1 - src/mainboard/technexion/tim8690/mainboard.c | 1 - src/northbridge/amd/agesa/family10/northbridge.c | 4 ---- src/northbridge/amd/agesa/family12/northbridge.c | 4 ---- src/northbridge/amd/agesa/family14/northbridge.c | 4 ---- src/northbridge/amd/agesa/family15/northbridge.c | 4 ---- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ---- src/northbridge/amd/amdfam10/northbridge.c | 4 ---- src/northbridge/amd/amdk8/northbridge.c | 4 ---- src/northbridge/intel/i82810/northbridge.c | 3 --- src/northbridge/intel/i82830/northbridge.c | 3 --- src/northbridge/intel/i945/northbridge.c | 3 --- src/northbridge/intel/sandybridge/northbridge.c | 3 --- src/northbridge/intel/sch/northbridge.c | 3 --- src/southbridge/amd/rs690/cmn.c | 2 -- src/southbridge/amd/rs780/cmn.c | 2 -- src/southbridge/amd/rs780/gfx.c | 2 -- src/southbridge/amd/rs780/rs780.c | 1 - src/southbridge/via/k8t890/dram.c | 4 ---- 50 files changed, 9 insertions(+), 105 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 5c48cfd..7fabb44 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -6,10 +6,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#if CONFIG_GFXUMA -extern uint64_t uma_memory_size; -#endif - static unsigned long resk(uint64_t value) { unsigned long resultk; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index f8b2591..851c8c4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -40,10 +40,6 @@ #include <arch/cpu.h> #include <arch/acpi.h> -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static unsigned int mtrr_msr[] = { MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, diff --git a/src/devices/device.c b/src/devices/device.c index ebac1a0..e45efdc 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -54,6 +54,11 @@ struct resource *free_resources = NULL; DECLARE_SPIN_LOCK(dev_lock) + +/* IGD UMA memory */ +uint64_t uma_memory_base = 0; +uint64_t uma_memory_size = 0; + /** * Allocate a new device structure. * diff --git a/src/include/device/device.h b/src/include/device/device.h index c4332e5..eae7f3b 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -103,6 +103,10 @@ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; extern struct bus *free_links; +/* IGD UMA memory */ +extern uint64_t uma_memory_base; +extern uint64_t uma_memory_size; + /* Generic device interface functions */ device_t alloc_dev(struct bus *parent, struct device_path *path); void dev_enumerate(void); diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index afa82f3..3504ac2 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -28,7 +28,6 @@ #include "SBPLATFORM.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; u8 is_dev3_present(void); void set_pcie_dereset(void); diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 241d905..4d685e2 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -28,7 +28,6 @@ #include <southbridge/amd/sb800/sb800.h> #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; u8 is_dev3_present(void); void set_pcie_dereset(void); diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 8841291..c5515b4 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; /******************************************************** * dbm690t uses a BCM5789 as on-board NIC. diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 360e1df..8eea6da 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -67,7 +67,6 @@ void set_pcie_dereset(void *nbconfig) } } -uint64_t uma_memory_base, uma_memory_size; /************************************************* * enable the dedicated function in dinar board. diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index d35b175..41aa907 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -71,7 +71,6 @@ void set_pcie_dereset(void) RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48); } -uint64_t uma_memory_base, uma_memory_size; /************************************************* * enable the dedicated function in INAGUA board. diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 989070c..a263f6e 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -29,8 +29,6 @@ #include "southbridge/amd/sb700/smbus.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 1f1941b..16dff47 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -29,8 +29,6 @@ #include "southbridge/amd/sb700/smbus.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 76a9ae6..c0db1c0 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -50,7 +50,6 @@ void set_pcie_dereset(void) { } -uint64_t uma_memory_base, uma_memory_size; /************************************************* * enable the dedicated function in persimmon board. diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index e5d0efa..6f62b58 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -39,7 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, #define ADT7475_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; /******************************************************** * pistachio uses a BCM5787 as on-board NIC. diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index ed65b34..bb6c522 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -28,7 +28,6 @@ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index e2ef3f9..1777c2b 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -39,8 +39,6 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 7248bfb..ee9ffa4 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -50,7 +50,6 @@ void set_pcie_dereset(void) { } -uint64_t uma_memory_base, uma_memory_size; /************************************************* * enable the dedicated function in torpedo board. diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index c5b481d..81777d8 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -47,7 +47,6 @@ void set_pcie_dereset(void) { } -uint64_t uma_memory_base, uma_memory_size; /************************************************* * enable the dedicated function in unionstation board. diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 0b566e4..d1b06c5 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -29,8 +29,6 @@ #include "southbridge/amd/sb700/smbus.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 8642e28..bf13746 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -46,7 +46,6 @@ void set_pcie_dereset(void) { } -uint64_t uma_memory_base, uma_memory_size; /************************************************* * enable the dedicated function in e350m1 board. diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index c936fa9..d5b9304 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -24,10 +24,6 @@ #include <southbridge/via/k8t890/k8t890.h> #include "chip.h" -#if CONFIG_GFXUMA -uint64_t uma_memory_base, uma_memory_size; -#endif - int add_mainboard_resources(struct lb_memory *mem) { #if CONFIG_GFXUMA diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 10ecb64..2b4e97c 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -29,8 +29,6 @@ #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 3b68143..3693300 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -38,8 +38,6 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 38b9648..291510c 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -28,7 +28,6 @@ #include "SBPLATFORM.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; u8 is_dev3_present(void); void set_pcie_dereset(void); diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 52befa5..89a0e96 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -28,7 +28,6 @@ #include "SBPLATFORM.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; u8 is_dev3_present(void); void set_pcie_dereset(void); diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 254df00..ea3f27e 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -29,8 +29,6 @@ #include "southbridge/amd/sb700/smbus.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); int is_dev3_present(void); diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 8d669ba..174c08d 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -39,8 +39,6 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); int is_dev3_present(void); diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index ee353ed..b81ebaa 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -30,8 +30,6 @@ #include "southbridge/amd/sb700/smbus.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index ef02c89..6d20523 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -29,8 +29,6 @@ #include "southbridge/amd/sb700/smbus.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index e992f74..329b4f6 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -30,8 +30,6 @@ #include "southbridge/amd/sb700/smbus.h" #include "chip.h" -uint64_t uma_memory_base, uma_memory_size; - void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index c2a401e..fcb2462 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; /******************************************************** * dbm690t uses a BCM5789 as on-board NIC. diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 0d7b8da..840e060 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -162,7 +162,6 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -uint64_t uma_memory_base, uma_memory_size; static u32 smbus_io_base = SMBUS_IO_BASE; static u32 adt7475_address = ADT7475_ADDRESS; diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 6350230..ab21212 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -83,7 +83,6 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; /* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the LDN the register belongs to, before you can access the register. */ diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 18abbc9..45b1b4d 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -uint64_t uma_memory_base, uma_memory_size; diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 3a1eb7b..12d83ad 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -908,10 +908,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void amdfam10_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 50694c7..6a591c5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -338,10 +338,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void read_resources(device_t dev) { u32 nodeid; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 9e6b257..021a1db 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -326,10 +326,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void read_resources(device_t dev) { u32 nodeid; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c76c963..d9da183 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -626,10 +626,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index ef5f1d8..efc8e68 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -613,10 +613,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA == 1 -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM == 1 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index dd2a9af..41434e8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -847,10 +847,6 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) #include <cbmem.h> #endif -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void amdfam10_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 621c0f1..8b9140d 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -822,10 +822,6 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) #include <cbmem.h> #endif -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void amdk8_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 78e3728..3337417 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -62,9 +62,6 @@ static const struct pci_driver i810e_northbridge_driver __pci_driver = { .device = 0x7124, }; -/* IGD UMA memory */ -uint64_t uma_memory_base=0, uma_memory_size=0; - int add_northbridge_resources(struct lb_memory *mem) { printk(BIOS_DEBUG, "Adding IGD UMA memory area\n"); diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 93bdc28..22f59dc 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -52,9 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -/* IGD memory */ -uint64_t uma_memory_base=0, uma_memory_size=0; - int add_northbridge_resources(struct lb_memory *mem) { printk(BIOS_DEBUG, "Adding IGD UMA memory area\n"); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 40b1aaa..58e70d7 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -68,9 +68,6 @@ static int get_pcie_bar(u32 *base, u32 *len) return 0; } -/* IDG memory */ -uint64_t uma_memory_base=0, uma_memory_size=0; - static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 6419f8c..b261c9d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -118,9 +118,6 @@ static int get_pcie_bar(u32 *base, u32 *len) return 0; } -/* IDG memory */ -uint64_t uma_memory_base=0, uma_memory_size=0; - static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 57245b6..047d7da 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -73,9 +73,6 @@ static int get_pcie_bar(u32 *base, u32 *len) return 0; } -/* IDG memory */ -u64 uma_memory_base = 0, uma_memory_size = 0; - static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 5e06d4f..68c46e9 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -315,8 +315,6 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) */ void rs690_set_tom(device_t nb_dev) { - extern uint64_t uma_memory_base; - /* set TOM */ pci_write_config32(nb_dev, 0x90, uma_memory_base); nbmc_write_index(nb_dev, 0x1e, uma_memory_base); diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 40a7262..5c72a04 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -356,8 +356,6 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) */ void rs780_set_tom(device_t nb_dev) { - extern uint64_t uma_memory_base; - /* set TOM */ pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index e07aa10..904e154 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -43,8 +43,6 @@ extern int is_dev3_present(void); void set_pcie_reset(void); void set_pcie_dereset(void); -extern uint64_t uma_memory_base, uma_memory_size; - /* Trust the original resource allocation. Don't do it again. */ #undef DONT_TRUST_RESOURCE_ALLOCATION //#define DONT_TRUST_RESOURCE_ALLOCATION diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index 9b153aa..f1029ca 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -221,7 +221,6 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) /* Program Straps. */ romstrap2 = 1 << 26; // enables audio function #if CONFIG_GFXUMA - extern uint64_t uma_memory_size; // bits 7-9: aperture size // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 7e450cc..11c8481 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -71,10 +71,6 @@ static void dram_enable(struct device *dev) } -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - static void dram_enable_k8m890(struct device *dev) { #if CONFIG_GFXUMA

1 0

New patch to review for coreboot: a2d2a6b Add global uma_resource()
by Kyösti Mälkki 10 Jul '12

10 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1203 -gerrit commit a2d2a6b483485d8a2dc7b0af5893201f6454377c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 10 13:27:26 2012 +0300 Add global uma_resource() Like ram_resource(), but reserved and not cacheable. Switch all AMD northbridges to use this one. Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/devices/device_util.c | 15 +++++++++++++++ src/include/device/device.h | 2 ++ src/northbridge/amd/agesa/family10/northbridge.c | 14 +------------- src/northbridge/amd/agesa/family12/northbridge.c | 17 +---------------- src/northbridge/amd/agesa/family14/northbridge.c | 16 +--------------- src/northbridge/amd/agesa/family15/northbridge.c | 14 +------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 16 ++-------------- src/northbridge/amd/amdfam10/northbridge.c | 14 +------------- src/northbridge/amd/amdk8/northbridge.c | 14 +------------- 9 files changed, 25 insertions(+), 97 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 5225938..4e25eb1 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -822,6 +822,21 @@ void ram_resource(device_t dev, unsigned long index, IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } +void uma_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) + return; + + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; diff --git a/src/include/device/device.h b/src/include/device/device.h index 0aea1d6..c4332e5 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -159,6 +159,8 @@ unsigned int scan_static_bus(device_t bus, unsigned int max); void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek); +void uma_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek); void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 7b73987..3a1eb7b 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -910,18 +910,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; - -static void add_uma_resource(struct device *dev, int index) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} #endif static void amdfam10_domain_set_resources(device_t dev) @@ -1102,7 +1090,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - add_uma_resource(dev, 7); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index efc0a48..50694c7 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -340,20 +340,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; - -static void add_uma_resource(struct device *dev, int index) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - add_uma_resource - Start.\n"); - - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Fam12h - northbridge.c - add_uma_resource - End.\n"); -} #endif static void read_resources(device_t dev) @@ -759,8 +745,7 @@ printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek); printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size); #if CONFIG_GFXUMA - printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); - add_uma_resource(dev, 7); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index f7c3b8e..9e6b257 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -328,19 +328,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; - -static void add_uma_resource(struct device *dev, int index) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "\nFam14h - Adding UMA memory.\n"); - - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} #endif static void read_resources(device_t dev) @@ -733,8 +720,7 @@ static void domain_set_resources(device_t dev) high_tables_size); #if CONFIG_GFXUMA - printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); - add_uma_resource(dev, 7); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 130086e..c76c963 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -628,18 +628,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; -static void add_uma_resource(struct device *dev, int index) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; -} #endif static void domain_set_resources(device_t dev) @@ -821,7 +809,7 @@ static void domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - add_uma_resource(dev, 7); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 3df5c60..ef5f1d8 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -615,18 +615,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; -static void add_uma_resource(struct device *dev, int index) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; -} #endif static void domain_set_resources(device_t dev) @@ -806,8 +794,8 @@ static void domain_set_resources(device_t dev) #endif } -#if CONFIG_GFXUMA == 1 - add_uma_resource(dev, 7); +#if CONFIG_GFXUMA + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3b20684..dd2a9af 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -849,18 +849,6 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; - -static void add_uma_resource(struct device *dev, int index) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} #endif static void amdfam10_domain_set_resources(device_t dev) @@ -1090,7 +1078,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - add_uma_resource(dev, 7); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5eeeda2..621c0f1 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -824,18 +824,6 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; - -static void add_uma_resource(struct device *dev, int index) -{ - struct resource *resource; - - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} #endif static void amdk8_domain_set_resources(device_t dev) @@ -1073,7 +1061,7 @@ static void amdk8_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - add_uma_resource(dev, 7); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #endif assign_resources(dev->link_list);

1 0

Patch set updated for coreboot: 10f6618 Add Fujitsu Siemens TX200 S3
by Sven Schnelle 10 Jul '12

10 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1202 -gerrit commit 10f661844f6205454a51a234e865424e3726f24f Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 12:02:55 2012 +0200 Add Fujitsu Siemens TX200 S3 Change-Id: I4a8e906b72dc4270976096ccb74920288ae4f026 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/Kconfig | 3 + src/mainboard/fsc/Kconfig | 16 +++ src/mainboard/fsc/tx200s3/Kconfig | 45 +++++++ src/mainboard/fsc/tx200s3/chip.h | 21 +++ src/mainboard/fsc/tx200s3/cmos.layout | 142 ++++++++++++++++++++ src/mainboard/fsc/tx200s3/devicetree.cb | 145 +++++++++++++++++++++ src/mainboard/fsc/tx200s3/irq_tables.c | 57 ++++++++ src/mainboard/fsc/tx200s3/mainboard.c | 117 +++++++++++++++++ src/mainboard/fsc/tx200s3/mptable.c | 68 ++++++++++ src/mainboard/fsc/tx200s3/romstage.c | 214 +++++++++++++++++++++++++++++++ 10 files changed, 828 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index b53b0e7..7abafc0 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -52,6 +52,8 @@ config VENDOR_ECS bool "ECS" config VENDOR_EMULATION bool "Emulation" +config VENDOR_FSC + bool "Fujitsu Siemens Computer(FSC)" config VENDOR_GETAC bool "Getac" config VENDOR_GIGABYTE @@ -153,6 +155,7 @@ source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/ecs/Kconfig" source "src/mainboard/emulation/Kconfig" +source "src/mainboard/fsc/Kconfig" source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" source "src/mainboard/hp/Kconfig" diff --git a/src/mainboard/fsc/Kconfig b/src/mainboard/fsc/Kconfig new file mode 100644 index 0000000..aa5ca11 --- /dev/null +++ b/src/mainboard/fsc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_FSC + +choice + prompt "Mainboard model" + +config BOARD_FSC_TX200S3 + bool "TX200 S3" +endchoice + +source "src/mainboard/fsc/tx200s3/Kconfig" + +config MAINBOARD_VENDOR + string + default "FSC (Fujitsu Siemens Computer)" + +endif # VENDOR_FSC diff --git a/src/mainboard/fsc/tx200s3/Kconfig b/src/mainboard/fsc/tx200s3/Kconfig new file mode 100644 index 0000000..71d6b56 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/Kconfig @@ -0,0 +1,45 @@ +if BOARD_FSC_TX200S3 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_SMSC_SMSCSUPERIO + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + select IPMI_KCS + select DRIVERS_GENERIC_IOAPIC + +config MAINBOARD_DIR + string + default fsc/tx200s3 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "TX200 S3" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/fsc/tx200s3/chip.h b/src/mainboard/fsc/tx200s3/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/fsc/tx200s3/cmos.layout b/src/mainboard/fsc/tx200s3/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/fsc/tx200s3/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/fsc/tx200s3/devicetree.cb b/src/mainboard/fsc/tx200s3/devicetree.cb new file mode 100644 index 0000000..81ff95d --- /dev/null +++ b/src/mainboard/fsc/tx200s3/devicetree.cb @@ -0,0 +1,145 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCI Express x8 Port 2-3 + device pci 00.0 on # PCI Express Upstream Port + device pci 00.0 on # PCI Express Downstream Port E1 + device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A + # PCI slot + device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B + # PCI slot + end + end + + end + device pci 02.0 on # PCI Express Downstream Port E3 + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.3 on # PCI Express to PCI-X Bridge + # PCI-X Slot + end + end + + device pci 03.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/serverengines/pilot + device pnp 4e.0 on # unknown + io 0x60 = 0xf00 + end + + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 4e.3 on # unknown + io 0x60 = 0xe00 + io 0x62 = 0x200 + io 0x64 = 0x204 + io 0x66 = 0x208 + end + + device pnp 4e.4 off end # unknown + device pnp 4e.5 off end # unknown + device pnp 4e.6 off end # unknown + device pnp 4e.7 off end # unknown + device pnp 4e.8 on # IPMI + io 0x60 = 0xca4 + io 0x62 = 0xca5 + end + + device pnp 4e.9 on # IPMI + io 0x60 = 0xca2 + io 0x62 = 0xca3 + end + + device pnp 4e.a off end # unknown + + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 on # LPT + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 off end + device pnp 2e.5 off end + + device pnp 2e.7 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + device pnp 2e.a off end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on + end # SMBUS + end + end +end diff --git a/src/mainboard/fsc/tx200s3/irq_tables.c b/src/mainboard/fsc/tx200s3/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/fsc/tx200s3/mainboard.c b/src/mainboard/fsc/tx200s3/mainboard.c new file mode 100644 index 0000000..08d642a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <smbios.h> +#include <string.h> +#include <../../../drivers/ipmi/ipmi_kcs.h> + +static const unsigned char ipmi_acpi_poweron[] = { 0xa0, 0x7f }; +static const unsigned char ipmi_boot_wdt_off[] = { 0x80, 0x28, 0x00, 0x0a, 0xc0 }; +static const unsigned char ipmi_clear_errors[] = { 0x80, 0x28, 0x00, 0x08, 0x01 }; + +static void mainboard_enable(device_t dev) +{ + unsigned char ipmi_response[32]; + int i, ret; + + ret = ipmi_kcs_message(0xca2, IPMI_NETFN_APPLICATION, 0, IPMI_CMD_ACPI_POWERON, + ipmi_acpi_poweron, sizeof(ipmi_acpi_poweron), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_boot_wdt_off, sizeof(ipmi_boot_wdt_off), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_clear_errors, sizeof(ipmi_clear_errors), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + +} + +static int smbios_data(device_t dev, int *handle, unsigned long *current) +{ + struct smbios_type38 *t = (struct smbios_type38 *)*current; + int len = sizeof(struct smbios_type38); + + memset(t, 0, sizeof(struct smbios_type38)); + t->type = 38; + t->handle = *handle++; + t->length = len; + t->interface_type = 1; /* KCS */ + t->ipmi_rev = 0x15; + t->i2c_slave_addr = 0x24; + t->nv_storage_addr = 0xff; + t->base_address = 0xca3; + t->base_address_modifier = 0; + *current += len; + return len - 1; /* FIXME: why? */ + +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, + .get_smbios_data = smbios_data, +}; + diff --git a/src/mainboard/fsc/tx200s3/mptable.c b/src/mainboard/fsc/tx200s3/mptable.c new file mode 100644 index 0000000..b95e6b9 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/mptable.c @@ -0,0 +1,68 @@ +/* generated by MPTable, version 2.0.15*/ +/* as modified by RGM for coreboot */ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 0x9, 0x20, IO_APIC_ADDR + 0x80000); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x03 << 2) | INTA, 0x8, 0x10); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x08 << 2) | INTA, 0x8, 0x10); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x8, 0x10); + + /* USB ports */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x8, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x02 << 2) | INTA, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | INTA, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x03 << 2) | INTA, 0x9, 0x3); + + /* MPT SAS */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x9, (0x05 << 2) | INTA, 0x8, 0x15); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/fsc/tx200s3/romstage.c b/src/mainboard/fsc/tx200s3/romstage.c new file mode 100644 index 0000000..343ef2a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/romstage.c @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/serverengines/pilot/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> +#include <delay.h> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + outl(0xff0cffe7, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xed00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x53990000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000bfe7, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030300, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x360f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x10); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0xe01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0xca1); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + pilot_enable_serial(PNP_DEV(0x4e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); + + device_t dev = PNP_DEV(0x4e, 0); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xf00); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 3); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xe00); + pnp_set_iobase(dev, 0x62, 0x200); + pnp_set_iobase(dev, 0x64, 0x204); + pnp_set_iobase(dev, 0x66, 0x208); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 4); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 5); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 6); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 7); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 8); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca4); + pnp_set_iobase(dev, 0x62, 0xca5); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 9); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca2); + pnp_set_iobase(dev, 0x62, 0xca3); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 0x0a); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +}

1 0

Patch set updated for coreboot: c4ce294 Add Fujitsu Siemens TX200 S3
by Sven Schnelle 10 Jul '12

10 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1202 -gerrit commit c4ce294b52f2ecded95d6e8f60edd3d43d52553d Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 12:02:55 2012 +0200 Add Fujitsu Siemens TX200 S3 Change-Id: I4a8e906b72dc4270976096ccb74920288ae4f026 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/Kconfig | 3 + src/mainboard/fsc/Kconfig | 16 +++ src/mainboard/fsc/tx200s3/Kconfig | 45 +++++++ src/mainboard/fsc/tx200s3/chip.h | 21 +++ src/mainboard/fsc/tx200s3/cmos.layout | 142 ++++++++++++++++++++ src/mainboard/fsc/tx200s3/devicetree.cb | 145 +++++++++++++++++++++ src/mainboard/fsc/tx200s3/irq_tables.c | 57 ++++++++ src/mainboard/fsc/tx200s3/mainboard.c | 117 +++++++++++++++++ src/mainboard/fsc/tx200s3/romstage.c | 214 +++++++++++++++++++++++++++++++ 9 files changed, 760 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index b53b0e7..7abafc0 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -52,6 +52,8 @@ config VENDOR_ECS bool "ECS" config VENDOR_EMULATION bool "Emulation" +config VENDOR_FSC + bool "Fujitsu Siemens Computer(FSC)" config VENDOR_GETAC bool "Getac" config VENDOR_GIGABYTE @@ -153,6 +155,7 @@ source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/ecs/Kconfig" source "src/mainboard/emulation/Kconfig" +source "src/mainboard/fsc/Kconfig" source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" source "src/mainboard/hp/Kconfig" diff --git a/src/mainboard/fsc/Kconfig b/src/mainboard/fsc/Kconfig new file mode 100644 index 0000000..aa5ca11 --- /dev/null +++ b/src/mainboard/fsc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_FSC + +choice + prompt "Mainboard model" + +config BOARD_FSC_TX200S3 + bool "TX200 S3" +endchoice + +source "src/mainboard/fsc/tx200s3/Kconfig" + +config MAINBOARD_VENDOR + string + default "FSC (Fujitsu Siemens Computer)" + +endif # VENDOR_FSC diff --git a/src/mainboard/fsc/tx200s3/Kconfig b/src/mainboard/fsc/tx200s3/Kconfig new file mode 100644 index 0000000..71d6b56 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/Kconfig @@ -0,0 +1,45 @@ +if BOARD_FSC_TX200S3 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_SMSC_SMSCSUPERIO + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + select IPMI_KCS + select DRIVERS_GENERIC_IOAPIC + +config MAINBOARD_DIR + string + default fsc/tx200s3 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "TX200 S3" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/fsc/tx200s3/chip.h b/src/mainboard/fsc/tx200s3/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/fsc/tx200s3/cmos.layout b/src/mainboard/fsc/tx200s3/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/fsc/tx200s3/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/fsc/tx200s3/devicetree.cb b/src/mainboard/fsc/tx200s3/devicetree.cb new file mode 100644 index 0000000..81ff95d --- /dev/null +++ b/src/mainboard/fsc/tx200s3/devicetree.cb @@ -0,0 +1,145 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCI Express x8 Port 2-3 + device pci 00.0 on # PCI Express Upstream Port + device pci 00.0 on # PCI Express Downstream Port E1 + device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A + # PCI slot + device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B + # PCI slot + end + end + + end + device pci 02.0 on # PCI Express Downstream Port E3 + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.3 on # PCI Express to PCI-X Bridge + # PCI-X Slot + end + end + + device pci 03.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/serverengines/pilot + device pnp 4e.0 on # unknown + io 0x60 = 0xf00 + end + + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 4e.3 on # unknown + io 0x60 = 0xe00 + io 0x62 = 0x200 + io 0x64 = 0x204 + io 0x66 = 0x208 + end + + device pnp 4e.4 off end # unknown + device pnp 4e.5 off end # unknown + device pnp 4e.6 off end # unknown + device pnp 4e.7 off end # unknown + device pnp 4e.8 on # IPMI + io 0x60 = 0xca4 + io 0x62 = 0xca5 + end + + device pnp 4e.9 on # IPMI + io 0x60 = 0xca2 + io 0x62 = 0xca3 + end + + device pnp 4e.a off end # unknown + + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 on # LPT + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 off end + device pnp 2e.5 off end + + device pnp 2e.7 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + device pnp 2e.a off end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on + end # SMBUS + end + end +end diff --git a/src/mainboard/fsc/tx200s3/irq_tables.c b/src/mainboard/fsc/tx200s3/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/fsc/tx200s3/mainboard.c b/src/mainboard/fsc/tx200s3/mainboard.c new file mode 100644 index 0000000..08d642a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <smbios.h> +#include <string.h> +#include <../../../drivers/ipmi/ipmi_kcs.h> + +static const unsigned char ipmi_acpi_poweron[] = { 0xa0, 0x7f }; +static const unsigned char ipmi_boot_wdt_off[] = { 0x80, 0x28, 0x00, 0x0a, 0xc0 }; +static const unsigned char ipmi_clear_errors[] = { 0x80, 0x28, 0x00, 0x08, 0x01 }; + +static void mainboard_enable(device_t dev) +{ + unsigned char ipmi_response[32]; + int i, ret; + + ret = ipmi_kcs_message(0xca2, IPMI_NETFN_APPLICATION, 0, IPMI_CMD_ACPI_POWERON, + ipmi_acpi_poweron, sizeof(ipmi_acpi_poweron), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_boot_wdt_off, sizeof(ipmi_boot_wdt_off), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_clear_errors, sizeof(ipmi_clear_errors), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + +} + +static int smbios_data(device_t dev, int *handle, unsigned long *current) +{ + struct smbios_type38 *t = (struct smbios_type38 *)*current; + int len = sizeof(struct smbios_type38); + + memset(t, 0, sizeof(struct smbios_type38)); + t->type = 38; + t->handle = *handle++; + t->length = len; + t->interface_type = 1; /* KCS */ + t->ipmi_rev = 0x15; + t->i2c_slave_addr = 0x24; + t->nv_storage_addr = 0xff; + t->base_address = 0xca3; + t->base_address_modifier = 0; + *current += len; + return len - 1; /* FIXME: why? */ + +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, + .get_smbios_data = smbios_data, +}; + diff --git a/src/mainboard/fsc/tx200s3/romstage.c b/src/mainboard/fsc/tx200s3/romstage.c new file mode 100644 index 0000000..343ef2a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/romstage.c @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/serverengines/pilot/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> +#include <delay.h> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + outl(0xff0cffe7, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xed00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x53990000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000bfe7, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030300, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x360f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x10); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0xe01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0xca1); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + pilot_enable_serial(PNP_DEV(0x4e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); + + device_t dev = PNP_DEV(0x4e, 0); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xf00); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 3); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xe00); + pnp_set_iobase(dev, 0x62, 0x200); + pnp_set_iobase(dev, 0x64, 0x204); + pnp_set_iobase(dev, 0x66, 0x208); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 4); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 5); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 6); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 7); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 8); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca4); + pnp_set_iobase(dev, 0x62, 0xca5); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 9); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca2); + pnp_set_iobase(dev, 0x62, 0xca3); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 0x0a); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +}

1 0

Patch set updated for coreboot: 3635c71 Add Fujitsu Siemens TX200 S3
by Sven Schnelle 10 Jul '12

10 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1202 -gerrit commit 3635c7102b4b4c9ef8822e04370f1ba937bd8276 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 12:02:55 2012 +0200 Add Fujitsu Siemens TX200 S3 Change-Id: I4a8e906b72dc4270976096ccb74920288ae4f026 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/Kconfig | 3 + src/mainboard/fsc/Kconfig | 16 +++ src/mainboard/fsc/tx200s3/Kconfig | 45 +++++++ src/mainboard/fsc/tx200s3/chip.h | 21 +++ src/mainboard/fsc/tx200s3/cmos.layout | 142 ++++++++++++++++++++ src/mainboard/fsc/tx200s3/devicetree.cb | 145 +++++++++++++++++++++ src/mainboard/fsc/tx200s3/dsdt.asl | 25 ++++ src/mainboard/fsc/tx200s3/irq_tables.c | 57 ++++++++ src/mainboard/fsc/tx200s3/mainboard.c | 117 +++++++++++++++++ src/mainboard/fsc/tx200s3/romstage.c | 214 +++++++++++++++++++++++++++++++ 10 files changed, 785 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index b53b0e7..7abafc0 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -52,6 +52,8 @@ config VENDOR_ECS bool "ECS" config VENDOR_EMULATION bool "Emulation" +config VENDOR_FSC + bool "Fujitsu Siemens Computer(FSC)" config VENDOR_GETAC bool "Getac" config VENDOR_GIGABYTE @@ -153,6 +155,7 @@ source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/ecs/Kconfig" source "src/mainboard/emulation/Kconfig" +source "src/mainboard/fsc/Kconfig" source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" source "src/mainboard/hp/Kconfig" diff --git a/src/mainboard/fsc/Kconfig b/src/mainboard/fsc/Kconfig new file mode 100644 index 0000000..aa5ca11 --- /dev/null +++ b/src/mainboard/fsc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_FSC + +choice + prompt "Mainboard model" + +config BOARD_FSC_TX200S3 + bool "TX200 S3" +endchoice + +source "src/mainboard/fsc/tx200s3/Kconfig" + +config MAINBOARD_VENDOR + string + default "FSC (Fujitsu Siemens Computer)" + +endif # VENDOR_FSC diff --git a/src/mainboard/fsc/tx200s3/Kconfig b/src/mainboard/fsc/tx200s3/Kconfig new file mode 100644 index 0000000..71d6b56 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/Kconfig @@ -0,0 +1,45 @@ +if BOARD_FSC_TX200S3 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_SMSC_SMSCSUPERIO + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + select IPMI_KCS + select DRIVERS_GENERIC_IOAPIC + +config MAINBOARD_DIR + string + default fsc/tx200s3 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "TX200 S3" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/fsc/tx200s3/chip.h b/src/mainboard/fsc/tx200s3/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/fsc/tx200s3/cmos.layout b/src/mainboard/fsc/tx200s3/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/fsc/tx200s3/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/fsc/tx200s3/devicetree.cb b/src/mainboard/fsc/tx200s3/devicetree.cb new file mode 100644 index 0000000..81ff95d --- /dev/null +++ b/src/mainboard/fsc/tx200s3/devicetree.cb @@ -0,0 +1,145 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCI Express x8 Port 2-3 + device pci 00.0 on # PCI Express Upstream Port + device pci 00.0 on # PCI Express Downstream Port E1 + device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A + # PCI slot + device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B + # PCI slot + end + end + + end + device pci 02.0 on # PCI Express Downstream Port E3 + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.3 on # PCI Express to PCI-X Bridge + # PCI-X Slot + end + end + + device pci 03.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/serverengines/pilot + device pnp 4e.0 on # unknown + io 0x60 = 0xf00 + end + + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 4e.3 on # unknown + io 0x60 = 0xe00 + io 0x62 = 0x200 + io 0x64 = 0x204 + io 0x66 = 0x208 + end + + device pnp 4e.4 off end # unknown + device pnp 4e.5 off end # unknown + device pnp 4e.6 off end # unknown + device pnp 4e.7 off end # unknown + device pnp 4e.8 on # IPMI + io 0x60 = 0xca4 + io 0x62 = 0xca5 + end + + device pnp 4e.9 on # IPMI + io 0x60 = 0xca2 + io 0x62 = 0xca3 + end + + device pnp 4e.a off end # unknown + + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 on # LPT + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 off end + device pnp 2e.5 off end + + device pnp 2e.7 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + device pnp 2e.a off end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on + end # SMBUS + end + end +end diff --git a/src/mainboard/fsc/tx200s3/dsdt.asl b/src/mainboard/fsc/tx200s3/dsdt.asl new file mode 100644 index 0000000..08f3cc9 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/dsdt.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT", "DSDT", 1, "BLAKFORD", "COREBOOT", 0x0000001) +{ +} + diff --git a/src/mainboard/fsc/tx200s3/irq_tables.c b/src/mainboard/fsc/tx200s3/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/fsc/tx200s3/mainboard.c b/src/mainboard/fsc/tx200s3/mainboard.c new file mode 100644 index 0000000..08d642a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <smbios.h> +#include <string.h> +#include <../../../drivers/ipmi/ipmi_kcs.h> + +static const unsigned char ipmi_acpi_poweron[] = { 0xa0, 0x7f }; +static const unsigned char ipmi_boot_wdt_off[] = { 0x80, 0x28, 0x00, 0x0a, 0xc0 }; +static const unsigned char ipmi_clear_errors[] = { 0x80, 0x28, 0x00, 0x08, 0x01 }; + +static void mainboard_enable(device_t dev) +{ + unsigned char ipmi_response[32]; + int i, ret; + + ret = ipmi_kcs_message(0xca2, IPMI_NETFN_APPLICATION, 0, IPMI_CMD_ACPI_POWERON, + ipmi_acpi_poweron, sizeof(ipmi_acpi_poweron), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_boot_wdt_off, sizeof(ipmi_boot_wdt_off), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_clear_errors, sizeof(ipmi_clear_errors), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + +} + +static int smbios_data(device_t dev, int *handle, unsigned long *current) +{ + struct smbios_type38 *t = (struct smbios_type38 *)*current; + int len = sizeof(struct smbios_type38); + + memset(t, 0, sizeof(struct smbios_type38)); + t->type = 38; + t->handle = *handle++; + t->length = len; + t->interface_type = 1; /* KCS */ + t->ipmi_rev = 0x15; + t->i2c_slave_addr = 0x24; + t->nv_storage_addr = 0xff; + t->base_address = 0xca3; + t->base_address_modifier = 0; + *current += len; + return len - 1; /* FIXME: why? */ + +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, + .get_smbios_data = smbios_data, +}; + diff --git a/src/mainboard/fsc/tx200s3/romstage.c b/src/mainboard/fsc/tx200s3/romstage.c new file mode 100644 index 0000000..343ef2a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/romstage.c @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/serverengines/pilot/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> +#include <delay.h> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + outl(0xff0cffe7, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xed00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x53990000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000bfe7, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030300, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x360f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x10); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0xe01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0xca1); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + pilot_enable_serial(PNP_DEV(0x4e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); + + device_t dev = PNP_DEV(0x4e, 0); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xf00); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 3); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xe00); + pnp_set_iobase(dev, 0x62, 0x200); + pnp_set_iobase(dev, 0x64, 0x204); + pnp_set_iobase(dev, 0x66, 0x208); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 4); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 5); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 6); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 7); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 8); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca4); + pnp_set_iobase(dev, 0x62, 0xca5); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 9); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca2); + pnp_set_iobase(dev, 0x62, 0xca3); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 0x0a); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +}

1 0

New patch to review for coreboot: 761f894 Add Fujitsu Siemens TX200 S3
by Sven Schnelle 10 Jul '12

10 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1202 -gerrit commit 761f894af9251c809e8fbddb060ae3b4246305dc Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 12:02:55 2012 +0200 Add Fujitsu Siemens TX200 S3 Change-Id: I4a8e906b72dc4270976096ccb74920288ae4f026 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/Kconfig | 3 + src/mainboard/fsc/Kconfig | 16 +++ src/mainboard/fsc/tx200s3/#dsdt.asl# | 66 +++++++++ src/mainboard/fsc/tx200s3/Kconfig | 45 ++++++ src/mainboard/fsc/tx200s3/acpi_tables.c | 223 +++++++++++++++++++++++++++++++ src/mainboard/fsc/tx200s3/chip.h | 21 +++ src/mainboard/fsc/tx200s3/cmos.layout | 142 ++++++++++++++++++++ src/mainboard/fsc/tx200s3/devicetree.cb | 145 ++++++++++++++++++++ src/mainboard/fsc/tx200s3/dsdt.asl | 25 ++++ src/mainboard/fsc/tx200s3/fadt.c | 182 +++++++++++++++++++++++++ src/mainboard/fsc/tx200s3/irq_tables.c | 57 ++++++++ src/mainboard/fsc/tx200s3/mainboard.c | 117 ++++++++++++++++ src/mainboard/fsc/tx200s3/romstage.c | 214 +++++++++++++++++++++++++++++ 13 files changed, 1256 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index b53b0e7..7abafc0 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -52,6 +52,8 @@ config VENDOR_ECS bool "ECS" config VENDOR_EMULATION bool "Emulation" +config VENDOR_FSC + bool "Fujitsu Siemens Computer(FSC)" config VENDOR_GETAC bool "Getac" config VENDOR_GIGABYTE @@ -153,6 +155,7 @@ source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/ecs/Kconfig" source "src/mainboard/emulation/Kconfig" +source "src/mainboard/fsc/Kconfig" source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" source "src/mainboard/hp/Kconfig" diff --git a/src/mainboard/fsc/Kconfig b/src/mainboard/fsc/Kconfig new file mode 100644 index 0000000..aa5ca11 --- /dev/null +++ b/src/mainboard/fsc/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_FSC + +choice + prompt "Mainboard model" + +config BOARD_FSC_TX200S3 + bool "TX200 S3" +endchoice + +source "src/mainboard/fsc/tx200s3/Kconfig" + +config MAINBOARD_VENDOR + string + default "FSC (Fujitsu Siemens Computer)" + +endif # VENDOR_FSC diff --git a/src/mainboard/fsc/tx200s3/#dsdt.asl# b/src/mainboard/fsc/tx200s3/#dsdt.asl# new file mode 100644 index 0000000..5bbba34 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/#dsdt.asl# @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT", "DSDT", 1, "BLAKFORD", "COREBOOT", 0x0000001) +{ + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + Name (PICM, 0x00) + Method (_PIC, 1, NotSerialized) + { + Store (Arg0, PICM) + } + /* System bus */ + Scope (\_SB) + { + /* Routing PCI0 */ + Name (PR00, Package () + { + Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, + Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, + Package (0x04){0x0002FFFF,0x01,LNKB,0x00}, + Package (0x04){0x0002FFFF,0x02,LNKC,0x00}, + Package (0x04){0x0002FFFF,0x03,LNKD,0x00}, + Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, + Package (0x04){0x0003FFFF,0x01,LNKB,0x00}, + Package (0x04){0x0003FFFF,0x02,LNKC,0x00}, + Package (0x04){0x0003FFFF,0x03,LNKD,0x00}, + Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, + Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, + Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, + Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, + Package (0x04){0x001FFFFF,0x03,LNKA,0x00} + }) + Device(LPC) + { + Name(_ADR, 0x001f0000) + + } + } + +} + diff --git a/src/mainboard/fsc/tx200s3/Kconfig b/src/mainboard/fsc/tx200s3/Kconfig new file mode 100644 index 0000000..71d6b56 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/Kconfig @@ -0,0 +1,45 @@ +if BOARD_FSC_TX200S3 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_SMSC_SMSCSUPERIO + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + select IPMI_KCS + select DRIVERS_GENERIC_IOAPIC + +config MAINBOARD_DIR + string + default fsc/tx200s3 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "TX200 S3" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/fsc/tx200s3/acpi_tables.c b/src/mainboard/fsc/tx200s3/acpi_tables.c new file mode 100644 index 0000000..5734191 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/acpi_tables.c @@ -0,0 +1,223 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u64 mmcfg; + + dev = dev_find_device(0x8086, 0x35B0, 0); // 0:0x13.0 + if (!dev) + return current; + + // MMCFG not supported or not enabled. + mmcfg = ((u64) pci_read_config16(dev, 0xce)) << 16; + if (!mmcfg) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + mmcfg, 0x0, 0x0, 0xff); + + return current; +} + +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfed00000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "IC ", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + // XXX factory bios just puts an address here -- who's right? + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x80861234; + hpet->number = 0x00; + hpet->min_tick = 0x0090; + + header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +#define IO_APIC0 2 +#define IO_APIC1 3 + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int irq_start = 0; + device_t dev = 0; + unsigned char bus_isa; + + /* Local Apic */ + current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0); + // This one is for the second core... Will it hurt? + current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, IO_APIC_ADDR, irq_start); + irq_start += 24; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, IO_APIC_ADDR + 0x80000, irq_start); + irq_start += 24; + + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + + if (dev) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); + bus_isa = 7; + } + + /* Map ISA IRQ 0 to IRQ 2 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, bus_isa, 0, 2, 0); + + /* IRQ9 differs from ISA standard - ours is active high, level-triggered */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d); + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", current); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/fsc/tx200s3/chip.h b/src/mainboard/fsc/tx200s3/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/fsc/tx200s3/cmos.layout b/src/mainboard/fsc/tx200s3/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/fsc/tx200s3/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/fsc/tx200s3/devicetree.cb b/src/mainboard/fsc/tx200s3/devicetree.cb new file mode 100644 index 0000000..81ff95d --- /dev/null +++ b/src/mainboard/fsc/tx200s3/devicetree.cb @@ -0,0 +1,145 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCI Express x8 Port 2-3 + device pci 00.0 on # PCI Express Upstream Port + device pci 00.0 on # PCI Express Downstream Port E1 + device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A + # PCI slot + device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B + # PCI slot + end + end + + end + device pci 02.0 on # PCI Express Downstream Port E3 + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.3 on # PCI Express to PCI-X Bridge + # PCI-X Slot + end + end + + device pci 03.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/serverengines/pilot + device pnp 4e.0 on # unknown + io 0x60 = 0xf00 + end + + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 4e.3 on # unknown + io 0x60 = 0xe00 + io 0x62 = 0x200 + io 0x64 = 0x204 + io 0x66 = 0x208 + end + + device pnp 4e.4 off end # unknown + device pnp 4e.5 off end # unknown + device pnp 4e.6 off end # unknown + device pnp 4e.7 off end # unknown + device pnp 4e.8 on # IPMI + io 0x60 = 0xca4 + io 0x62 = 0xca5 + end + + device pnp 4e.9 on # IPMI + io 0x60 = 0xca2 + io 0x62 = 0xca3 + end + + device pnp 4e.a off end # unknown + + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 on # LPT + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 off end + device pnp 2e.5 off end + + device pnp 2e.7 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + device pnp 2e.a off end + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on + end # SMBUS + end + end +end diff --git a/src/mainboard/fsc/tx200s3/dsdt.asl b/src/mainboard/fsc/tx200s3/dsdt.asl new file mode 100644 index 0000000..08f3cc9 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/dsdt.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT", "DSDT", 1, "BLAKFORD", "COREBOOT", 0x0000001) +{ +} + diff --git a/src/mainboard/fsc/tx200s3/fadt.c b/src/mainboard/fsc/tx200s3/fadt.c new file mode 100644 index 0000000..c584c62 --- /dev/null +++ b/src/mainboard/fsc/tx200s3/fadt.c @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +#define ACPI_PM1_STS (pmbase + 0x00) +#define ACPI_PM1_EN (pmbase + 0x02) +#define ACPI_PM1_CNT (pmbase + 0x04) +#define ACPI_PM1_TMR (pmbase + 0x08) +#define ACPI_PROC_CNT (pmbase + 0x10) +#define ACPI_LV2 (pmbase + 0x14) +#define ACPI_GPE0_STS (pmbase + 0x28) +#define ACPI_GPE0_EN (pmbase + 0x2C) +#define ACPI_SMI_EN (pmbase + 0x30) +#define ACPI_SMI_STS (pmbase + 0x34) +#define ACPI_ALT_GP_SMI_EN (pmbase + 0x38) +#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A) +#define ACPI_MON_SMI (pmbase + 0x40) +#define ACPI_DEVACT_STS (pmbase + 0x44) +#define ACPI_DEVTRAP_EN (pmbase + 0x48) +#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C) +#define ACPI_BUS_CYC_TRACK (pmbase + 0x4E) + +#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS +#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT +#define ACPI_PM_TMR_BLK ACPI_PM1_TMR +#define ACPI_P_BLK ACPI_PROC_CNT +#define ACPI_GPE0_BLK ACPI_GPE0_STS + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = 7; /* Performance Server */ + fadt->sci_int = 0x9; +#if CONFIG_HAVE_SMI_HANDLER + fadt->smi_cmd = APM_CNT; +#else + fadt->smi_cmd = 0x00; +#endif + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0x0; + + fadt->pm1_evt_len = 0x4; + fadt->pm1_cnt_len = 0x2; + fadt->pm2_cnt_len = 0x0; + fadt->pm_tmr_len = 0x4; + fadt->gpe0_blk_len = 0x8; + fadt->gpe1_blk_len = 0x0; + fadt->gpe1_base = 0x0; + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 0x65; + fadt->p_lvl3_lat = 0x3e9; + fadt->flush_size = 0x400; + fadt->flush_stride = 0x10; + fadt->duty_offset = 0x1; + fadt->duty_width = 0x3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + fadt->flags = 0xa5; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + fadt->res3 = 0; + fadt->res4 = 0; + fadt->res5 = 0; + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 32; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 32; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/fsc/tx200s3/irq_tables.c b/src/mainboard/fsc/tx200s3/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/fsc/tx200s3/mainboard.c b/src/mainboard/fsc/tx200s3/mainboard.c new file mode 100644 index 0000000..08d642a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <smbios.h> +#include <string.h> +#include <../../../drivers/ipmi/ipmi_kcs.h> + +static const unsigned char ipmi_acpi_poweron[] = { 0xa0, 0x7f }; +static const unsigned char ipmi_boot_wdt_off[] = { 0x80, 0x28, 0x00, 0x0a, 0xc0 }; +static const unsigned char ipmi_clear_errors[] = { 0x80, 0x28, 0x00, 0x08, 0x01 }; + +static void mainboard_enable(device_t dev) +{ + unsigned char ipmi_response[32]; + int i, ret; + + ret = ipmi_kcs_message(0xca2, IPMI_NETFN_APPLICATION, 0, IPMI_CMD_ACPI_POWERON, + ipmi_acpi_poweron, sizeof(ipmi_acpi_poweron), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_boot_wdt_off, sizeof(ipmi_boot_wdt_off), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + + ret = ipmi_kcs_message(0xca2, 0x2e, 0, 0xf1, + ipmi_clear_errors, sizeof(ipmi_clear_errors), + ipmi_response, sizeof(ipmi_response)); + + if (ret <= 0) { + printk(BIOS_WARNING, "IPMI status: %d\n", ret); + return; + } + + printk(BIOS_INFO, "IPMI response: "); + for(i = 0; i < ret; i++) { + printk(BIOS_INFO, "%02X ", ipmi_response[i]); + } + printk(BIOS_INFO, "\n"); + +} + +static int smbios_data(device_t dev, int *handle, unsigned long *current) +{ + struct smbios_type38 *t = (struct smbios_type38 *)*current; + int len = sizeof(struct smbios_type38); + + memset(t, 0, sizeof(struct smbios_type38)); + t->type = 38; + t->handle = *handle++; + t->length = len; + t->interface_type = 1; /* KCS */ + t->ipmi_rev = 0x15; + t->i2c_slave_addr = 0x24; + t->nv_storage_addr = 0xff; + t->base_address = 0xca3; + t->base_address_modifier = 0; + *current += len; + return len - 1; /* FIXME: why? */ + +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, + .get_smbios_data = smbios_data, +}; + diff --git a/src/mainboard/fsc/tx200s3/romstage.c b/src/mainboard/fsc/tx200s3/romstage.c new file mode 100644 index 0000000..343ef2a --- /dev/null +++ b/src/mainboard/fsc/tx200s3/romstage.c @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/serverengines/pilot/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> +#include <delay.h> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + outl(0xff0cffe7, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xed00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x53990000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000bfe7, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030300, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x360f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x10); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0xe01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0xca1); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + pilot_enable_serial(PNP_DEV(0x4e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); + + device_t dev = PNP_DEV(0x4e, 0); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xf00); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 3); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xe00); + pnp_set_iobase(dev, 0x62, 0x200); + pnp_set_iobase(dev, 0x64, 0x204); + pnp_set_iobase(dev, 0x66, 0x208); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 4); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 5); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 6); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 7); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, 8); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca4); + pnp_set_iobase(dev, 0x62, 0xca5); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 9); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0xca2); + pnp_set_iobase(dev, 0x62, 0xca3); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + + dev = PNP_DEV(0x4e, 0x0a); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +}

1 0

Patch set updated for coreboot: 64e022a Drop invalid device ops on Agesa northbridge
by Kyösti Mälkki 10 Jul '12

10 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1180 -gerrit commit 64e022a2c8f74de28de940164592445438fea729 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 6 17:27:37 2012 +0300 Drop invalid device ops on Agesa northbridge One could not pass a device of type APIC to PCI resource functions. The correct CPU model specific cpu->ops is set at later time in cpu_initialize(). Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 18 ------------------ src/northbridge/amd/agesa/family15/northbridge.c | 18 ------------------ src/northbridge/amd/agesa/family15tn/northbridge.c | 18 ------------------ 3 files changed, 0 insertions(+), 54 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 7b73987..3088f54 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1231,21 +1231,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1447,9 +1432,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 130086e..5b22707 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -889,21 +889,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1100,9 +1085,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 3df5c60..d967793 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -873,21 +873,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1084,9 +1069,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); }

1 0

Patch set updated for coreboot: 5f8eb59 Move cpus_ready_for_init() to AMD K8
by Kyösti Mälkki 10 Jul '12

10 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1184 -gerrit commit 5f8eb595cd8cf9c39da83e85dd9ff6284866bfc1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 7 13:42:03 2012 +0300 Move cpus_ready_for_init() to AMD K8 The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/lapic/lapic_cpu_init.c | 2 -- src/include/cpu/cpu.h | 6 ------ src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/ibm/e325/Kconfig | 1 - src/mainboard/ibm/e326/Kconfig | 1 - src/mainboard/iwill/dk8_htx/Kconfig | 1 - src/mainboard/iwill/dk8s2/Kconfig | 1 - src/mainboard/iwill/dk8x/Kconfig | 1 - src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/technexion/tim8690/Kconfig | 1 - src/northbridge/amd/amdk8/Kconfig | 4 ++++ src/northbridge/amd/amdk8/amdk8.h | 2 ++ src/northbridge/amd/amdk8/northbridge.c | 3 +++ 14 files changed, 9 insertions(+), 23 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index de40c05..d7240de 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,7 +1,3 @@ -config WAIT_BEFORE_CPUS_INIT - bool - default n - config UDELAY_IO bool default y if !UDELAY_LAPIC && !UDELAY_TSC diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index b6dc560..302eeba 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -286,8 +286,6 @@ void initialize_cpus(struct bus *cpu_bus) smm_init(); #endif - cpus_ready_for_init(); - /* Initialize the bootstrap processor */ cpu_initialize(cpu_bus, 0); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9765dfd..90e4620 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -11,12 +11,6 @@ void secondary_cpu_init(int index); extern unsigned int cpucount; -#if !CONFIG_WAIT_BEFORE_CPUS_INIT - #define cpus_ready_for_init() do {} while(0) -#else - void cpus_ready_for_init(void); -#endif - #if CONFIG_HAVE_SMI_HANDLER void smm_init(void); void smm_lock(void); diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index d140878..a83fbcf 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 9ef4c48..839ea8f 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 475cb85..ac52534 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index 5ad70f3..5f9920a 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select LIFT_BSP_APIC_ID select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index 7fda0a6..f13d06a 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index 452b6e6..a17f104 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index a1f69c8..0856ff8 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -157,10 +157,6 @@ config MEM_TRAIN_SEQ int default 2 -config WAIT_BEFORE_CPUS_INIT - bool - default n - config AMD_UCODE_PATCH_FILE string default "mc_patch_01000096.h" diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 293590c..6bfa814 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 70e75e9..9ea5404 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -33,6 +33,10 @@ config K8_HT_FREQ_1G_SUPPORT bool default n +config WAIT_BEFORE_CPUS_INIT + bool + default n + config MEM_TRAIN_SEQ int default 0 diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 5aa3b31..e001706 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -14,4 +14,6 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif +void cpus_ready_for_init(void); + #endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5eeeda2..cf80389 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1331,6 +1331,9 @@ static u32 cpu_bus_scan(device_t dev, u32 max) static void cpu_bus_init(device_t dev) { +#if CONFIG_WAIT_BEFORE_CPUS_INIT + cpus_ready_for_init(); +#endif initialize_cpus(dev->link_list); }

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coreboot July 2012