coreboot July 2012

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639 discussions

Re: [coreboot] New patch to review for coreboot: 7219e05 i5000: Fix resource allocation
by Patrick Georgi 13 Jul '12

13 Jul '12

Am 13.07.2012 19:46, schrieb ron minnich: > Everything that's not 64-bit seems to either have not much memory > (geode) or be able to "flip" memory to the 4G+ boundary and manage > it. > Would this make any sense? i945 can't remap to 4G+ and is 32bit only in some configurations Patrick

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Help needed on VX900 port
by Alex G. 13 Jul '12

13 Jul '12

I have been working on a VIA VX900 port for over a year. Main problem is, I can't get the memory running properly. If you have a VX900 board, I would definitely appreciate some help. The datasheet for the VX900 is available from http://linux.via.com.tw/. I also have some code provided by VIA, which unfortunately, is missing lots of #define, and lookup tables, so it's not a plug in solution, but has been a useful resource in correcting many problems with my code. If you are interested, I can provide my branch of the code, and the code provided by VIA (which was given to me under GPLv2). I cannot provide any documentation, other than the comments I have made in the code, sorry. So far I've got CAR working. This is actually just the CAR code from the VIA C7, but it plays nicely with the VIA Nano. Serial console is working on my EPIA M-850, and of course, so is the SMBUS. I've got the memory init code running up to the point that some memory banks (bank = chip_on_the_dimm) are returning correct data, and some, just garbage. I ran out of ideas last night, and I could definitely use a fresh perspective. If anyone is interested in the VX900, please let me know. Alex

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Patch set updated for coreboot: 96313ec amd/lx: Move configuration from source to Kconfig
by Patrick Georgi 13 Jul '12

13 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1227 -gerrit commit 96313ec2c0421d8a9555d320c5fe767281e0b958 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jul 13 19:06:22 2012 +0200 amd/lx: Move configuration from source to Kconfig LX has two values that are usually automatically derived but can be overridden, that were so far defined in each board's romstage. These values, along with the toggle to enable override are now part of LX's Kconfig. For boards that gave values but requested autogeneration, the values are removed. Further improvements: Figure out the various fields in PLLMSRlo and make them sensible Kconfig options (instead of the hex value it is now) Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 6 +--- src/mainboard/amd/db800/romstage.c | 6 +--- src/mainboard/amd/norwich/romstage.c | 6 +--- src/mainboard/artecgroup/dbe61/romstage.c | 8 +----- src/mainboard/bachmann/ot200/Kconfig | 6 ++++ src/mainboard/bachmann/ot200/romstage.c | 6 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 6 +--- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 6 ++++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 10 +------ src/mainboard/iei/pm-lx-800-r11/Kconfig | 19 +++---------- src/mainboard/iei/pm-lx-800-r11/romstage.c | 12 +-------- src/mainboard/lippert/hurricane-lx/Kconfig | 6 ++++ src/mainboard/lippert/hurricane-lx/romstage.c | 6 +--- src/mainboard/lippert/literunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/literunner-lx/romstage.c | 6 +--- src/mainboard/lippert/roadrunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/roadrunner-lx/romstage.c | 6 +--- src/mainboard/lippert/spacerunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/spacerunner-lx/romstage.c | 6 +--- src/mainboard/pcengines/alix1c/romstage.c | 6 +--- src/mainboard/pcengines/alix2d/romstage.c | 6 +--- src/mainboard/traverse/geos/Kconfig | 6 ++++ src/mainboard/traverse/geos/romstage.c | 6 +--- src/mainboard/winent/pl6064/romstage.c | 6 +--- src/northbridge/amd/lx/Kconfig | 31 ++++++++++++++++++++++- src/northbridge/amd/lx/pll_reset.c | 8 +++--- 26 files changed, 97 insertions(+), 111 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index 4b510a9..2d3b71d 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -47,10 +47,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -79,7 +75,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 3590c37..2bb6cd3 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -41,10 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -74,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index d8fca5a..c71b31f 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -38,10 +38,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index f97af92..61bd03e 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address) return 0xFF; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -/* CPU and GLIU mult/div 500/266*/ -#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */ -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -94,7 +88,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index a201bde..5d185c0 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select POWER_BUTTON_DEFAULT_DISABLE select DRIVERS_I2C_IDREG + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -25,4 +27,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x07de001e + endif # BOARD_BACHMANN_OT200 diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 9edd5f7..3a8ecad 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */ -#define PLLMSRlo 0x07de001e - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index d30e2b0..caafd2f 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -22,10 +22,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -57,7 +53,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index eae72ae..69e106e 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 9 +config PLLMSRlo + hex + default 0x00DE6000 + endif # BOARD_IEI_PCISA_LX_800_R10 diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index aec9843..7bd1b74 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ -//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ -#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ -//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -78,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index a897106..e443c6c 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS select PIRQ_ROUTE select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT int default 7 -choice - prompt "Core/GLIU Frequency" - default CORE_GLIU_500_266 - -config CORE_GLIU_500_266 - bool "500MHz / 266MHz" - -config CORE_GLIU_500_333 - bool "500MHz / 333MHz" - -config CORE_GLIU_500_400 - bool "500MHz / 400MHz" - -endchoice +config PLLMSRlo + hex + default 0x07de0000 endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f756622..2992f53 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#if CONFIG_CORE_GLIU_500_400 -# define PLLMSRhi 0x0000059c -#elif CONFIG_CORE_GLIU_500_333 -# define PLLMSRhi 0x0000049c -#else -# define PLLMSRhi 0x0000039c -#endif - -#define PLLMSRlo 0x07de000 - #include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/pll_reset.c> #include <northbridge/amd/lx/raminit.c> @@ -80,7 +70,7 @@ void main(unsigned long bist) report_bist_failure(bist); - pll_reset(1); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 118809d..64e1631 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -50,4 +52,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_HURRICANE_LX diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 29aa9d1..b2ee033 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -40,10 +40,6 @@ /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -138,7 +134,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 12a3ae1..c4684c9 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -42,4 +44,8 @@ config ONBOARD_IDE_SLAVE If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_LITERUNNER_LX diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 1e82bdb..77e2d12 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -181,7 +177,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 2d11b33..f5ec9b9 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -34,4 +36,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_ROADRUNNER_LX diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 20e5b6a..827c41b 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -37,10 +37,6 @@ #include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/early_serial.c" -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -113,7 +109,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index 99ecf7c..c4a2ce8 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -41,4 +43,8 @@ config ONBOARD_IDE_SLAVE help If selected, the on-board SSD will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_SPACERUNNER_LX diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9dcb37b..d62c039 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -178,7 +174,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f109031..9de3863 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -99,10 +99,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -132,7 +128,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 0e8cc63..fd5582d 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -98,10 +98,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -156,7 +152,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 40679fe..3139d7d 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 select POWER_BUTTON_DEFAULT_DISABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x00de602e + endif # BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 588681b..0b61d41 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* manual settings for the PLL */ -#define PLLMSRlo 0x00DE602E - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6651acd..39e4ecf 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -77,7 +73,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index c1fea49..d74d715 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA +if NORTHBRIDGE_AMD_LX + config VIDEO_MB int default 8 - depends on NORTHBRIDGE_AMD_LX + +config PLL_MANUAL_CONFIG + bool + +if PLL_MANUAL_CONFIG + +# "Core/GLIU Frequency" +config CORE_GLIU_500_266 + bool # "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool # "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool # "500MHz / 400MHz" + +config PLLMSRhi + hex + default 0x39c if CORE_GLIU_500_266 + default 0x49c if CORE_GLIU_500_333 + default 0x59c if CORE_GLIU_500_400 + +config PLLMSRlo + hex + +endif + +endif diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 3077b61..bf01e54 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void pll_reset(char manualconf) +static void pll_reset(void) { msr_t msrGlcpSysRstpll; @@ -31,13 +31,13 @@ static void pll_reset(char manualconf) if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { printk(BIOS_DEBUG, "Configuring PLL.\n"); - if (manualconf) { + if (CONFIG_PLL_MANUAL_CONFIG) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi; /* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; + msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo; } else { /*automatic configuration (straps) */ post_code(POST_PLL_STRAP);

1 0

Patch set updated for coreboot: 18fa711 amd/lx: Move configuration from source to Kconfig
by Patrick Georgi 13 Jul '12

13 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1227 -gerrit commit 18fa71163f9952cd2b4724e0c495d39acec2b90b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jul 13 19:06:22 2012 +0200 amd/lx: Move configuration from source to Kconfig LX has two values that are usually automatically derived but can be overridden, that were so far defined in each board's romstage. These values, along with the toggle to enable override are now part of LX's Kconfig. For boards that gave values but requested autogeneration, the values are removed. Further improvements: Figure out the various fields in PLLMSRlo and make them sensible Kconfig options (instead of the hex value it is now) Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 6 +--- src/mainboard/amd/db800/romstage.c | 6 +--- src/mainboard/amd/norwich/romstage.c | 6 +--- src/mainboard/artecgroup/dbe61/romstage.c | 8 +----- src/mainboard/bachmann/ot200/Kconfig | 6 ++++ src/mainboard/bachmann/ot200/romstage.c | 6 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 6 +--- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 6 ++++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 10 +------ src/mainboard/iei/pm-lx-800-r11/Kconfig | 19 +++---------- src/mainboard/iei/pm-lx-800-r11/romstage.c | 10 ------- src/mainboard/lippert/hurricane-lx/Kconfig | 6 ++++ src/mainboard/lippert/hurricane-lx/romstage.c | 6 +--- src/mainboard/lippert/literunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/literunner-lx/romstage.c | 6 +--- src/mainboard/lippert/roadrunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/roadrunner-lx/romstage.c | 6 +--- src/mainboard/lippert/spacerunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/spacerunner-lx/romstage.c | 6 +--- src/mainboard/pcengines/alix1c/romstage.c | 6 +--- src/mainboard/pcengines/alix2d/romstage.c | 6 +--- src/mainboard/traverse/geos/Kconfig | 6 ++++ src/mainboard/traverse/geos/romstage.c | 6 +--- src/mainboard/winent/pl6064/romstage.c | 6 +--- src/northbridge/amd/lx/Kconfig | 31 ++++++++++++++++++++++- src/northbridge/amd/lx/pll_reset.c | 8 +++--- 26 files changed, 96 insertions(+), 110 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index 4b510a9..2d3b71d 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -47,10 +47,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -79,7 +75,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 3590c37..2bb6cd3 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -41,10 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -74,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index d8fca5a..c71b31f 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -38,10 +38,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index f97af92..61bd03e 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address) return 0xFF; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -/* CPU and GLIU mult/div 500/266*/ -#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */ -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -94,7 +88,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index a201bde..5d185c0 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select POWER_BUTTON_DEFAULT_DISABLE select DRIVERS_I2C_IDREG + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -25,4 +27,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x07de001e + endif # BOARD_BACHMANN_OT200 diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 9edd5f7..3a8ecad 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */ -#define PLLMSRlo 0x07de001e - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index d30e2b0..caafd2f 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -22,10 +22,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -57,7 +53,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index eae72ae..69e106e 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 9 +config PLLMSRlo + hex + default 0x00DE6000 + endif # BOARD_IEI_PCISA_LX_800_R10 diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index aec9843..7bd1b74 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ -//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ -#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ -//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -78,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index a897106..e443c6c 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS select PIRQ_ROUTE select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT int default 7 -choice - prompt "Core/GLIU Frequency" - default CORE_GLIU_500_266 - -config CORE_GLIU_500_266 - bool "500MHz / 266MHz" - -config CORE_GLIU_500_333 - bool "500MHz / 333MHz" - -config CORE_GLIU_500_400 - bool "500MHz / 400MHz" - -endchoice +config PLLMSRlo + hex + default 0x07de0000 endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f756622..57a9fc6 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#if CONFIG_CORE_GLIU_500_400 -# define PLLMSRhi 0x0000059c -#elif CONFIG_CORE_GLIU_500_333 -# define PLLMSRhi 0x0000049c -#else -# define PLLMSRhi 0x0000039c -#endif - -#define PLLMSRlo 0x07de000 - #include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/pll_reset.c> #include <northbridge/amd/lx/raminit.c> diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 118809d..64e1631 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -50,4 +52,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_HURRICANE_LX diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 29aa9d1..b2ee033 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -40,10 +40,6 @@ /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -138,7 +134,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 12a3ae1..c4684c9 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -42,4 +44,8 @@ config ONBOARD_IDE_SLAVE If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_LITERUNNER_LX diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 1e82bdb..77e2d12 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -181,7 +177,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 2d11b33..f5ec9b9 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -34,4 +36,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_ROADRUNNER_LX diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 20e5b6a..827c41b 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -37,10 +37,6 @@ #include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/early_serial.c" -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -113,7 +109,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index 99ecf7c..c4a2ce8 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -41,4 +43,8 @@ config ONBOARD_IDE_SLAVE help If selected, the on-board SSD will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_SPACERUNNER_LX diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9dcb37b..d62c039 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -178,7 +174,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f109031..9de3863 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -99,10 +99,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -132,7 +128,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 0e8cc63..fd5582d 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -98,10 +98,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -156,7 +152,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 40679fe..3139d7d 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 select POWER_BUTTON_DEFAULT_DISABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x00de602e + endif # BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 588681b..0b61d41 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* manual settings for the PLL */ -#define PLLMSRlo 0x00DE602E - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6651acd..39e4ecf 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -77,7 +73,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index c1fea49..d74d715 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA +if NORTHBRIDGE_AMD_LX + config VIDEO_MB int default 8 - depends on NORTHBRIDGE_AMD_LX + +config PLL_MANUAL_CONFIG + bool + +if PLL_MANUAL_CONFIG + +# "Core/GLIU Frequency" +config CORE_GLIU_500_266 + bool # "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool # "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool # "500MHz / 400MHz" + +config PLLMSRhi + hex + default 0x39c if CORE_GLIU_500_266 + default 0x49c if CORE_GLIU_500_333 + default 0x59c if CORE_GLIU_500_400 + +config PLLMSRlo + hex + +endif + +endif diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 3077b61..bf01e54 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void pll_reset(char manualconf) +static void pll_reset(void) { msr_t msrGlcpSysRstpll; @@ -31,13 +31,13 @@ static void pll_reset(char manualconf) if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { printk(BIOS_DEBUG, "Configuring PLL.\n"); - if (manualconf) { + if (CONFIG_PLL_MANUAL_CONFIG) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi; /* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; + msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo; } else { /*automatic configuration (straps) */ post_code(POST_PLL_STRAP);

1 0

Patch merged into coreboot/master: 2e66ea9 sconfig: fix up shipped code
by gerrit＠coreboot.org 13 Jul '12

13 Jul '12

the following patch was just integrated into master: commit 2e66ea915ae2527bc15e4caa5c2b59bfffab26df Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 13 12:02:44 2012 +0200 sconfig: fix up shipped code The lex compile wasn't current (or something) and so INTA wasn't lexed properly. Change-Id: I5a760430788792f54c4e1e0d419b8dd525079d15 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Jul 13 14:07:54 2012, giving +1 See http://review.coreboot.org/1226 for details. -gerrit

1 0

New patch to review for coreboot: 7219e05 i5000: Fix resource allocation
by Sven Schnelle 13 Jul '12

13 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1220 -gerrit commit 7219e05f3f707dc6515ccaa5174ce69579f649ff Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 12 20:05:22 2012 +0200 i5000: Fix resource allocation The current code didn't reserve static resource the right way. Also reduce TOLM to 0xd0000000, because those boards have so many PCI devices that 0xe0000000 isn't sufficient. Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/northbridge.c | 104 +++++++++++++++-------------- src/northbridge/intel/i5000/raminit.c | 6 +- 2 files changed, 57 insertions(+), 53 deletions(-) diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index f5cc0ba..d3e00c5 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -31,6 +31,9 @@ #include <arch/acpi.h> #include <cbmem.h> #include "chip.h" +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { @@ -43,60 +46,18 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, -}; - -static struct device_operations mc_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, -}; - -static const unsigned short nb_ids[] = { - 0x25c0, /* 5000X */ - 0x25d0, /* 5000Z */ - 0x25d4, /* 5000V */ - 0x25d8, /* 5000P */ - 0}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = nb_ids, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static void cpu_bus_noop(device_t dev) -{ -} -static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - -static void pci_domain_set_resources(device_t dev) +static void mc_read_resources(device_t dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0; + device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + pci_dev_read_resources(dev); + tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16; hecbase = pci_read_config16(dev16_0, 0x64) >> 12; hecbase &= 0xffff; @@ -119,8 +80,8 @@ static void pci_domain_set_resources(device_t dev) memsize <<= 24; printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize); - if (memsize > 0xe0000000) { - memsize -= 0xe0000000; + if (memsize > 0xd0000000) { + memsize -= 0xd0000000; printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576); ram_resource(dev, idx++, 4096 * 1024, memsize / 1024); } @@ -156,8 +117,6 @@ static void pci_domain_set_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - assign_resources(dev->link_list); - #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = tolm - HIGH_MEMORY_SIZE; @@ -166,6 +125,51 @@ static void pci_domain_set_resources(device_t dev) #endif } +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const unsigned short nb_ids[] = { + 0x25c0, /* 5000X */ + 0x25d0, /* 5000Z */ + 0x25d4, /* 5000V */ + 0x25d8, /* 5000P */ + 0}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = nb_ids, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 841e809..ffc579a 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1349,8 +1349,8 @@ static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) i5000_setup_interleave(setup); - if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00) - tolm = 0xe00; + if ((tolm = MIN(setup->totalmem, 0xd00)) > 0xd00) + tolm = 0xd00; tolm <<= 4; printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm); @@ -1759,7 +1759,7 @@ void i5000_fbdimm_init(void) #if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK if (ram_check_nodie(0x000000, 0x0a0000) || - ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) { + ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) { i5000_try_restart("RAM verification failed"); }

2 1

New patch to review for coreboot: 109481e amd/lx: Move configuration from source to Kconfig
by Patrick Georgi 13 Jul '12

13 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1227 -gerrit commit 109481e06febb3f1b1475f087b2dcd2d0e7e3b0a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jul 13 19:06:22 2012 +0200 amd/lx: Move configuration from source to Kconfig LX has two values that are usually automatically derived but can be overridden, that were so far defined in each board's romstage. These values, along with the toggle to enable override are now part of LX's Kconfig. For boards that gave values but requested autogeneration, the values are removed. Further improvements: Figure out the various fields in PLLMSRlo and make them sensible Kconfig options (instead of the hex value it is now) Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 6 +--- src/mainboard/amd/db800/romstage.c | 6 +--- src/mainboard/amd/norwich/romstage.c | 6 +--- src/mainboard/artecgroup/dbe61/romstage.c | 8 +----- src/mainboard/bachmann/ot200/Kconfig | 6 ++++ src/mainboard/bachmann/ot200/romstage.c | 4 --- src/mainboard/digitallogic/msm800sev/romstage.c | 6 +--- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 6 ++++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 10 +------ src/mainboard/iei/pm-lx-800-r11/Kconfig | 19 +++---------- src/mainboard/iei/pm-lx-800-r11/romstage.c | 10 ------- src/mainboard/lippert/hurricane-lx/Kconfig | 6 ++++ src/mainboard/lippert/hurricane-lx/romstage.c | 4 --- src/mainboard/lippert/literunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/literunner-lx/romstage.c | 4 --- src/mainboard/lippert/roadrunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/roadrunner-lx/romstage.c | 4 --- src/mainboard/lippert/spacerunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/spacerunner-lx/romstage.c | 4 --- src/mainboard/pcengines/alix1c/romstage.c | 6 +--- src/mainboard/pcengines/alix2d/romstage.c | 6 +--- src/mainboard/traverse/geos/Kconfig | 6 ++++ src/mainboard/traverse/geos/romstage.c | 4 --- src/mainboard/winent/pl6064/romstage.c | 6 +--- src/northbridge/amd/lx/Kconfig | 31 ++++++++++++++++++++++- src/northbridge/amd/lx/pll_reset.c | 8 +++--- 26 files changed, 90 insertions(+), 104 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index 4b510a9..2d3b71d 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -47,10 +47,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -79,7 +75,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 3590c37..2bb6cd3 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -41,10 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -74,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index d8fca5a..c71b31f 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -38,10 +38,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index f97af92..61bd03e 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address) return 0xFF; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -/* CPU and GLIU mult/div 500/266*/ -#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */ -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -94,7 +88,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index a201bde..5d185c0 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select POWER_BUTTON_DEFAULT_DISABLE select DRIVERS_I2C_IDREG + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -25,4 +27,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x07de001e + endif # BOARD_BACHMANN_OT200 diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 9edd5f7..fbe4bd7 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */ -#define PLLMSRlo 0x07de001e - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index d30e2b0..caafd2f 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -22,10 +22,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -57,7 +53,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index eae72ae..69e106e 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 9 +config PLLMSRlo + hex + default 0x00DE6000 + endif # BOARD_IEI_PCISA_LX_800_R10 diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index aec9843..7bd1b74 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ -//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ -#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ -//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -78,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index a897106..e443c6c 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS select PIRQ_ROUTE select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT int default 7 -choice - prompt "Core/GLIU Frequency" - default CORE_GLIU_500_266 - -config CORE_GLIU_500_266 - bool "500MHz / 266MHz" - -config CORE_GLIU_500_333 - bool "500MHz / 333MHz" - -config CORE_GLIU_500_400 - bool "500MHz / 400MHz" - -endchoice +config PLLMSRlo + hex + default 0x07de0000 endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f756622..57a9fc6 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#if CONFIG_CORE_GLIU_500_400 -# define PLLMSRhi 0x0000059c -#elif CONFIG_CORE_GLIU_500_333 -# define PLLMSRhi 0x0000049c -#else -# define PLLMSRhi 0x0000039c -#endif - -#define PLLMSRlo 0x07de000 - #include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/pll_reset.c> #include <northbridge/amd/lx/raminit.c> diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 118809d..64e1631 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -50,4 +52,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_HURRICANE_LX diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 29aa9d1..78188bb 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -40,10 +40,6 @@ /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 12a3ae1..c4684c9 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -42,4 +44,8 @@ config ONBOARD_IDE_SLAVE If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_LITERUNNER_LX diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 1e82bdb..b80c7ca 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 2d11b33..f5ec9b9 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -34,4 +36,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_ROADRUNNER_LX diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 20e5b6a..e59e4fa 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -37,10 +37,6 @@ #include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/early_serial.c" -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index 99ecf7c..c4a2ce8 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -41,4 +43,8 @@ config ONBOARD_IDE_SLAVE help If selected, the on-board SSD will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_SPACERUNNER_LX diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9dcb37b..fca28c0 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f109031..9de3863 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -99,10 +99,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -132,7 +128,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 0e8cc63..fd5582d 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -98,10 +98,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -156,7 +152,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 40679fe..3139d7d 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 select POWER_BUTTON_DEFAULT_DISABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x00de602e + endif # BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 588681b..50cc8fa 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* manual settings for the PLL */ -#define PLLMSRlo 0x00DE602E - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6651acd..39e4ecf 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -77,7 +73,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index c1fea49..d74d715 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA +if NORTHBRIDGE_AMD_LX + config VIDEO_MB int default 8 - depends on NORTHBRIDGE_AMD_LX + +config PLL_MANUAL_CONFIG + bool + +if PLL_MANUAL_CONFIG + +# "Core/GLIU Frequency" +config CORE_GLIU_500_266 + bool # "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool # "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool # "500MHz / 400MHz" + +config PLLMSRhi + hex + default 0x39c if CORE_GLIU_500_266 + default 0x49c if CORE_GLIU_500_333 + default 0x59c if CORE_GLIU_500_400 + +config PLLMSRlo + hex + +endif + +endif diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 3077b61..bf01e54 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void pll_reset(char manualconf) +static void pll_reset(void) { msr_t msrGlcpSysRstpll; @@ -31,13 +31,13 @@ static void pll_reset(char manualconf) if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { printk(BIOS_DEBUG, "Configuring PLL.\n"); - if (manualconf) { + if (CONFIG_PLL_MANUAL_CONFIG) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi; /* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; + msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo; } else { /*automatic configuration (straps) */ post_code(POST_PLL_STRAP);

1 0

Patch set updated for coreboot: ea2ef07 Make the device tree available in the rom stage
by Ronald G. Minnich 13 Jul '12

13 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1194 -gerrit commit ea2ef07eb98af9596cedf598b902303919c2d084 Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Mon Jul 2 10:05:57 2012 -0700 Make the device tree available in the rom stage We've needed a way to use the device tree in romstage for about ten years, and the need has gotten more urgent as the RAM setup takes longer and longer, and requires information only available in the device tree. Further, RAM setup needs a lot more configuration performed than used to be the case, and we've gotten by with hardcodes until now. Finally, for a better "user experience", it is good to have the platform activate, e.g., backlights, so the user knows that the machine is alive. This last problem was the precipitating event for this change. We thought about two ways to do this change. The way we decided to try was to #ifdef __PRE_RAM__ and #ifndef __PRE_RAM__ a few things: 1. initializers for ops struct member 2. global declarations 3. Definition of which section to place device tree data in. The sconfig tool can define a SECTION attribute as a struct tag so that device structs can be placed in the readonly area of romstage. The sconfig tool will now declare structs as follows: struct bus SECTION dev_root_links[]; There are 46 instances on one test board but this is all generated by sconfig. Translation: almost nobody ever looks at this file so I doubt it matters that it's not pretty. A device struct now looks like this: static struct device SECTION _dev14 = { .ops = 0, .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x16,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev15, .chip_ops = &southbridge_intel_bd82x6x_ops, .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev15 }; The result allows us to compile ram- and rom-stage device tree from one file. The sconfig tool is modified so that: 1. References to ops struct members are not generated for PRE_RAM 2. We try to tag global structs and put them into .text 3. Due to a bug in gld, we have to create an accessor function for last_dev. No idea why. This is tested on a device at Google, and works fine. It allows us to use the config structs in romstage and remove ugly hard-codes. It will not affect boards that don't use the device tree in romstage. Right now, one must use the romcc_io.h pci functions OR the device tree oriented pci functions, due to the all-too-clever overloading of the device_t name. We plan to remove this limitation in a future patch, so that both the lowest level non-device tree functions can be used as well as device tree functions. IIRC that's what we did in v3 as well. This includes a minor tweak to the lint test to make it work correctly and another minor tweak to PCI Makefile that seems to have gotten lost in the 'type 2 must die' upgrade without which it will not compile. Change-Id: I01589fb57a070128abbcc236951ad58cf044af19 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- Makefile.inc | 5 ++ src/arch/x86/lib/Makefile.inc | 3 +- src/devices/Makefile.inc | 3 + src/devices/device.c | 2 - src/devices/device_util.c | 66 ++++++++++++++++++++++++++ src/include/device/device.h | 4 ++ util/lint/lint-stable-002-build-dir-handling | 10 ++-- util/sconfig/main.c | 66 +++++++++++++++++++------- 8 files changed, 134 insertions(+), 25 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..6c96a58 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,6 +228,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" @@ -237,6 +238,10 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< +$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 2186072..78f8a23 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,7 +1,6 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c -ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c @@ -13,6 +12,8 @@ romstage-y += romstage_console.c romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c +romstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c +romstage-y += pci_ops_conf1.c smm-y += memset.c smm-y += memcpy.c diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9ffc0bb..79c59ab 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,9 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +romstage-y+= device_util.c +romstage-y+= pci_ops.c + subdirs-y += oprom ifeq ($(CONFIG_PCI_ROM_RUN),y) diff --git a/src/devices/device.c b/src/devices/device.c index fafa599..08fdbb0 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -45,8 +45,6 @@ #include <arch/ebda.h> #endif -/** Linked list of ALL devices */ -struct device *all_devices = &dev_root; /** Pointer to the last device */ extern struct device *last_dev; /** Linked list of free resources */ diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 7c1cde9..c4ddea4 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -29,6 +29,12 @@ #include <device/resource.h> #include <string.h> +/** Linked list of ALL devices */ +#ifdef __PRE_RAM__ +struct device __attribute__((__section__(".text"))) *all_devices = &dev_root; +#else +struct device *all_devices = &dev_root; + /** * See if a device structure exists for path. * @@ -48,6 +54,23 @@ device_t find_dev_path(struct bus *parent, struct device_path *path) } /** + * See if a device structure already exists and if not allocate it. + * + * @param parent The bus to find the device on. + * @param path The relative path from the bus to the appropriate device. + * @return Pointer to a device structure for the device on bus at path. + */ +device_t alloc_find_dev(struct bus *parent, struct device_path *path) +{ + device_t child; + child = find_dev_path(parent, path); + if (!child) + child = alloc_dev(parent, path); + return child; +} + +#endif +/** * Given a PCI bus and a devfn number, find the device structure. * * @param bus The bus number. @@ -158,6 +181,47 @@ struct device *dev_find_class(unsigned int class, struct device *from) return from; } +#ifdef __PRE_RAM__ +const char *dev_path(device_t dev) +{ + if (!dev) { + return "<null>"; + } else { + switch(dev->path.type) { + case DEVICE_PATH_ROOT: + return "Root Device"; + break; + case DEVICE_PATH_PCI: + return "PCI: "; + break; + case DEVICE_PATH_PNP: + return "PNP: "; + break; + case DEVICE_PATH_I2C: + return "I2C: "; + break; + case DEVICE_PATH_APIC: + return "APIC: "; + break; + case DEVICE_PATH_PCI_DOMAIN: + return "PCI_DOMAIN: "; + break; + case DEVICE_PATH_APIC_CLUSTER: + return "APIC_CLUSTER: "; + break; + case DEVICE_PATH_CPU: + return "CPU: "; + break; + case DEVICE_PATH_CPU_BUS: + return "CPU_BUS: "; + break; + default: + return "Unknown"; + break; + } + } +} +#else /* * Warning: This function uses a static buffer. Don't call it more than once * from the same print statement! @@ -856,3 +920,5 @@ int dev_count_cpu(void) return count; } +#endif + diff --git a/src/include/device/device.h b/src/include/device/device.h index f36710a..4b1b6ef 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -103,12 +103,16 @@ struct device { /** * This is the root of the device tree. The device tree is defined in the * static.c file and is generated by the config tool at compile time. + * In the romstage one must use accessor functions as we do not have + * globals. */ extern struct device dev_root; +#ifndef __PRE_RAM__ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; extern struct bus *free_links; +#endif /* Generic device interface functions */ device_t alloc_dev(struct bus *parent, struct device_path *path); diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling index c4247b5..60548f1 100755 --- a/util/lint/lint-stable-002-build-dir-handling +++ b/util/lint/lint-stable-002-build-dir-handling @@ -33,7 +33,7 @@ fi # $1: object directory run_printall() { -$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |tr " " "\n"|grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s,^r.mstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../,g" |tr " " "\n"|grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," } # find GNU make @@ -54,10 +54,10 @@ $MAKE DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null # look up parent directory PARENTDIR=`dirname $PWD` -compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" +compare_output "`run_printall build`" "build/.../static.c build/.../static.c build/.../static.ramstage.o build/.../static.romstage.o" +compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o $PARENTDIR/obj/.../static.romstage.o" +compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" +compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.ramstage.o /tmp/.../static.romstage.o" rm -f $TMPCONFIG diff --git a/util/sconfig/main.c b/util/sconfig/main.c index ca8c3c5..51949f1 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -361,14 +361,18 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir } static void pass0(FILE *fil, struct device *ptr) { - if (ptr->type == device && ptr->id == 0) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + if (ptr->type == device && ptr->id == 0){ + fprintf(fil, "struct bus SECTION %s_links[];\n", ptr->name); + } if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { fprintf(fil, "static struct device %s;\n", ptr->name); - if (ptr->rescnt > 0) - fprintf(fil, "struct resource %s_res[];\n", ptr->name); - if (ptr->children || ptr->multidev) - fprintf(fil, "struct bus %s_links[];\n", ptr->name); + if (ptr->rescnt > 0){ + fprintf(fil, "struct resource SECTION %s_res[];\n", ptr->name); + } + if (ptr->children || ptr->multidev){ + fprintf(fil, "struct bus SECTION %s_links[];\n", + ptr->name); + } } } @@ -376,11 +380,14 @@ static void pass1(FILE *fil, struct device *ptr) { int pin; if (!ptr->used && (ptr->type == device)) { - if (ptr->id != 0) + if (ptr->id) fprintf(fil, "static "); - fprintf(fil, "struct device %s = {\n", ptr->name); + fprintf(fil, "struct device SECTION %s = {\n", ptr->name); + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); - fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); + fprintf(fil, "#endif\n"); + fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, + ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); fprintf(fil, "},\n"); @@ -411,7 +418,9 @@ static void pass1(FILE *fil, struct device *ptr) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { + fprintf(fil, "#ifndef __PRE_RAM__\n"); fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); } if (ptr->nextdev) @@ -420,7 +429,8 @@ static void pass1(FILE *fil, struct device *ptr) } if (ptr->rescnt > 0) { int i=1; - fprintf(fil, "struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "struct resource SECTION %s_res[] = {\n", + ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_"); @@ -437,7 +447,7 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t };\n"); } if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { - fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + fprintf(fil, "struct bus SECTION %s_links[] = {\n", ptr->name); if (ptr->multidev) { struct device *d = ptr; while (d) { @@ -469,8 +479,9 @@ static void pass1(FILE *fil, struct device *ptr) } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", - ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "struct %s_config SECTION %s_info_%d\t= {\n", + ptr->name_underscore, ptr->name_underscore, + ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -478,7 +489,7 @@ static void pass1(FILE *fil, struct device *ptr) } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", + fprintf(fil, "struct %s_config SECTION %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id); } } @@ -606,12 +617,33 @@ int main(int argc, char** argv) { h = h->next; fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); } - + fprintf(autogen, + "#ifdef __PRE_RAM__\n" + "#define SECTION " + "__attribute__((__section__(\".text\")))\n" + "#else\n" + "#define SECTION\n" + "#endif\n"); walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL); fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); - fprintf(autogen, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\n" - "struct device *last_dev = &%s;\n", lastdev->name); + + /* the section attribute fails (another gld bug?) + * for last_dev. So we have to do the accessor function. + */ + fprintf(autogen,"\n/* pass 1 */\n" + "static struct " + "mainboard_config SECTION mainboard_info_0;\n" + "#ifndef __PRE_RAM__\n" + "struct device *last_dev = &%s;\n" + "#endif\n", + lastdev->name); + /* generate accessor function for PRE_RAM */ + fprintf(autogen,"#ifdef __PRE_RAM__\n"); + fprintf(autogen,"struct device *get_last_dev(void);\n"); + fprintf(autogen,"struct device *get_last_dev(void)\n" + "{\nreturn &%s;\n}\n", lastdev->name); + fprintf(autogen,"#endif\n"); walk_device_tree(autogen, &root, pass1, NULL); } else if (scan_mode == BOOTBLOCK_MODE) {

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Patch merged into coreboot/master: b465d63 Add preliminary support for Bachmann electronic OT200
by gerrit＠coreboot.org 13 Jul '12

13 Jul '12

the following patch was just integrated into master: commit b465d63f6e0627c5407db97a68b41bbd12ccd9d3 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Fri Jul 13 11:36:08 2012 +0200 Add preliminary support for Bachmann electronic OT200 Linux boots fine :) Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 13 14:34:31 2012, giving +2 See http://review.coreboot.org/1225 for details. -gerrit

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Tinkering with old and new motherboards
by David Griffith 13 Jul '12

13 Jul '12

I have an old motherboard which I'd like to experiment on and have my eyes on a bleeding-edge board. The old one is a Shuttle AN35N Ultra (socket 1). The new one is an MSI 990FXA-GD80V2 (socket AM3+). Neither of these appear on the list of supported motherboards. Tinkering with the old board should be relatively safe because the BIOS lives in a socketed PLCC. I can't seem to figure out what sort of package the firmware in the newer one lives in. None of the photos I've found of it seem to have good enough resolution to tell. Can I get some help here? -- David Griffith dave(a)661.org

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coreboot July 2012