coreboot July 2012

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New patch to review for coreboot: c2f9141 Supermicro X7DB8: Use autogeneration of mptable
by Sven Schnelle 13 Jul '12

13 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1222 -gerrit commit c2f9141eee1fdd4108ed5f072610f8d96317dd14 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Jun 25 21:35:45 2012 +0200 Supermicro X7DB8: Use autogeneration of mptable And fix the wrong indenting of devicetree.cb while at it. Change-Id: Idbb19fb5d7155f44675098e79920caf65191c239 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/supermicro/x7db8/Kconfig | 1 + src/mainboard/supermicro/x7db8/devicetree.cb | 184 ++++++++++++++++---------- 2 files changed, 115 insertions(+), 70 deletions(-) diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 5365f85..2e26c78 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 + select DRIVERS_GENERIC_IOAPIC config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb index 66e5cfe..8949c54 100644 --- a/src/mainboard/supermicro/x7db8/devicetree.cb +++ b/src/mainboard/supermicro/x7db8/devicetree.cb @@ -33,22 +33,30 @@ chip northbridge/intel/i5000 subsystemid 0x15d9 0x2017 end - device pci 02.0 on # PCIe bridge - device pci 00.0 on - device pci 00.0 on - device pci 00.0 on end - device pci 02.0 on end - end - device pci 02.0 on - device pci 00.0 on - device pci 02.0 on - device pci 00.0 on end # e1000 #1 - device pci 00.1 on end # e1000 #2 + device pci 02.0 on # PCI Express x8 Port 2-3 + ioapic_irq 8 INTA 0x10 + ioapic_irq 8 INTB 0x11 + ioapic_irq 8 INTC 0x12 + ioapic_irq 8 INTD 0x13 + device pci 00.0 on # PCI Express Upstream Port + device pci 00.0 on # PCI Express Downstream Port E1 + device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A + ioapic_irq 8 INTA 0x11 + ioapic_irq 8 INTB 0x10 + ioapic_irq 8 INTC 0x11 + ioapic_irq 8 INTD 0x10 + # PCI slot + device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B + # PCI slot + end + device pci 02.0 on # Adaptec U320 #1 + ioapic_irq 8 INTA 0x10 + end + device pci 02.1 on # Adaptec U320 #2 + ioapic_irq 8 INTB 0x11 end end - device pci 00.1 on end end - end device pci 00.1 on end device pci 00.3 on end end @@ -58,6 +66,31 @@ chip northbridge/intel/i5000 device pci 05.0 on end device pci 06.0 on end device pci 07.0 on end + device pci 00.3 on # PCI Express to PCI-X Bridge + ioapic_irq 9 INTA 3 + ioapic_irq 9 INTB 0 + ioapic_irq 9 INTC 1 + ioapic_irq 9 INTD 2 + # PCI-X Slot + end + end + + device pci 03.0 on + ioapic_irq 8 INTA 0x10 + end + device pci 04.0 on + ioapic_irq 8 INTA 0x10 + end + device pci 05.0 on + ioapic_irq 8 INTA 0x10 + end + device pci 06.0 on + ioapic_irq 8 INTA 0x10 + end + device pci 07.0 on + ioapic_irq 8 INTA 0x10 + end + device pci 10.0 on end # FBD device pci 10.1 on end # FBD device pci 10.2 on end # FBD @@ -71,68 +104,79 @@ chip northbridge/intel/i5000 register "pirq_e_h" = "0x80808080" register "sata_ports_implemented" = "0x3f" - device pci 1c.0 on end # PCIe bridge - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on - device pci 01.0 on - end - end + device pci 1c.0 on + ioapic_irq 8 INTA 0x14 + ioapic_irq 8 INTB 0x15 + ioapic_irq 8 INTC 0x16 + ioapic_irq 8 INTD 0x17 + end # PCIe bridge + device pci 1d.0 on + ioapic_irq 8 INTA 0x10 + end # USB UHCI + device pci 1d.1 on + ioapic_irq 8 INTB 0x11 + end # USB UHCI + device pci 1d.2 on + ioapic_irq 8 INTC 0x12 + end # USB UHCI + device pci 1d.3 on + ioapic_irq 8 INTD 0x13 + end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on + device pci 01.0 on end + end - device pci 1f.0 on # PCI-LPC bridge - subsystemid 0x15d9 0x2009 - chip superio/winbond/w83627hf - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end + device pci 1f.0 on # PCI-LPC bridge + ioapic_irq 8 INTA 0x11 + subsystemid 0x15d9 0x2009 + chip superio/winbond/w83627hf + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end - device pnp 2e.3 off end - device pnp 2e.5 on # KBC - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 + device pnp 2e.3 off end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # Game port / MIDI + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 on end # GPIO3 + device pnp 2e.a on end # ACPI + device pnp 2e.b off end # HWMON end - - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # Game port / MIDI - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 on end # GPIO3 - device pnp 2e.a on end # ACPI - device pnp 2e.b off end # HWMON - end - end - device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on - chip drivers/i2c/w83793 - register "mfc" = "0x28" - register "fanin" = "0x1f" - register "peci_agent_conf" = "0x33" - register "tcase0" = "0x5e" - register "tcase1" = "0x5e" - register "tcase2" = "0x5e" - register "tcase3" = "0x5e" - register "tr_enable" = "0x01" - register "critical_temperature" = "0x7f" - register "td1_fan_select" = "0x01" - register "td2_fan_select" = "0x01" - register "td3_fan_select" = "0x01" - register "td4_fan_select" = "0x01" - - device i2c 0x2f on end end - end # SMBUS + device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on + chip drivers/i2c/w83793 + register "mfc" = "0x28" + register "fanin" = "0x1f" + register "peci_agent_conf" = "0x33" + register "tcase0" = "0x5e" + register "tcase1" = "0x5e" + register "tcase2" = "0x5e" + register "tcase3" = "0x5e" + register "tr_enable" = "0x01" + register "critical_temperature" = "0x7f" + register "td1_fan_select" = "0x01" + register "td2_fan_select" = "0x01" + register "td3_fan_select" = "0x01" + register "td4_fan_select" = "0x01" + device i2c 0x2f on end + end + end # SMBUS end end end

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Patch merged into coreboot/master: 1e3051e msrtool: add support for cs5536 LPC_SERIRQ (0x5140004e)
by gerrit＠coreboot.org 13 Jul '12

13 Jul '12

the following patch was just integrated into master: commit 1e3051e6d356190b98dbb7ad4b80565da7eb8eac Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed Jul 11 09:31:12 2012 +0200 msrtool: add support for cs5536 LPC_SERIRQ (0x5140004e) This register is helpful for porting new mainboards based on cs5536 southbridge. Change-Id: Iff3adc2c2fbc672c8541096756f95b3322f6ab19 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 13 08:40:14 2012, giving +2 See http://review.coreboot.org/1211 for details. -gerrit

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Patch merged into coreboot/master: 7fb8699 MPTAPLE: generate from devicetree.cb
by gerrit＠coreboot.org 13 Jul '12

13 Jul '12

the following patch was just integrated into master: commit 7fb869913fd4c223e9bb35b8250334671ef3b88f Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 21 22:19:48 2012 +0200 MPTAPLE: generate from devicetree.cb This patch adds support for autogenerating the MPTABLE from devicetree.cb. This is done by a write_smp_table() declared weak in mpspec.c. If the mainboard doesn't provide it's own function, this generic implementation is called. Syntax in devicetree.cb: ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN> The ioapic_irq directive can be used in pci and pci_domain devices. If there's no directive, the autogen code traverses the tree back to the pci_domain and stops at the first device which such a directive, and use that information to generate the entry according to PCI IRQ routing rules. Change-Id: I4df5b198e8430f939d477c14c798414e398a2027 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 13 08:38:13 2012, giving +2 See http://review.coreboot.org/1138 for details. -gerrit

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Patch merged into coreboot/master: fa073e1 IOAPIC: hook up driver in Kconfig
by gerrit＠coreboot.org 13 Jul '12

13 Jul '12

the following patch was just integrated into master: commit fa073e1cbf85191f1f2e21924a00e154b1fdc3c9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jul 11 21:45:46 2012 +0200 IOAPIC: hook up driver in Kconfig Missed to add the driver to Kconfig and Makefile.inc. Change-Id: I64b02abc5de2f6483f610436ebb38a7ca433f9b6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 13 08:38:08 2012, giving +2 See http://review.coreboot.org/1219 for details. -gerrit

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Re: [coreboot] Link at http://www.coreboot.org/Previous_GSoC_Projects
by Darmawan Salihun 13 Jul '12

13 Jul '12

Thanks Marc :-) On 7/13/12, Marc Jones <marcj303(a)gmail.com> wrote: > On Thu, Jul 12, 2012 at 2:01 PM, Darmawan Salihun > <darmawan.salihun(a)gmail.com> wrote: >> Hi guys, >> >> The link to: Low Cost Embedded x86 Teaching Tool >> in the wiki: >> http://www.coreboot.org/Previous_GSoC_Projects#USB_Option_ROM_for_SeaBIOS >> >> Should point to >> https://sites.google.com/site/pinczakko/low-cost-embedded-x86-teaching-tool… >> >> The Geocities page has long been gone. >> >> I don't have access to edit the page. >> >> Thanks, >> >> Darmawan >> -- >> -------------------------------------------------------------------- >> -= Human knowledge belongs to the world =- >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > Fixed. > > Thanks, > Marc > > -- > http://se-eng.com > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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Re: [coreboot] Link at http://www.coreboot.org/Previous_GSoC_Projects
by Marc Jones 12 Jul '12

12 Jul '12

On Thu, Jul 12, 2012 at 2:01 PM, Darmawan Salihun <darmawan.salihun(a)gmail.com> wrote: > Hi guys, > > The link to: Low Cost Embedded x86 Teaching Tool > in the wiki: http://www.coreboot.org/Previous_GSoC_Projects#USB_Option_ROM_for_SeaBIOS > > Should point to > https://sites.google.com/site/pinczakko/low-cost-embedded-x86-teaching-tool… > > The Geocities page has long been gone. > > I don't have access to edit the page. > > Thanks, > > Darmawan > -- > -------------------------------------------------------------------- > -= Human knowledge belongs to the world =- > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Fixed. Thanks, Marc -- http://se-eng.com

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Link at http://www.coreboot.org/Previous_GSoC_Projects
by Darmawan Salihun 12 Jul '12

12 Jul '12

Hi guys, The link to: Low Cost Embedded x86 Teaching Tool in the wiki: http://www.coreboot.org/Previous_GSoC_Projects#USB_Option_ROM_for_SeaBIOS Should point to https://sites.google.com/site/pinczakko/low-cost-embedded-x86-teaching-tool… The Geocities page has long been gone. I don't have access to edit the page. Thanks, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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Patch merged into coreboot/master: 50e9f32 Drop Kconfig VAR_MTRR_HOLE option
by gerrit＠coreboot.org 12 Jul '12

12 Jul '12

the following patch was just integrated into master: commit 50e9f32b1fed83731c6f30cbef749a51ced2a43d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jul 11 14:40:19 2012 +0300 Drop Kconfig VAR_MTRR_HOLE option All but one board use the default value of enabled. Disabling this can only increase the number of MTRR registers used. Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jul 12 01:38:34 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 12 20:28:35 2012, giving +2 See http://review.coreboot.org/1213 for details. -gerrit

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New patch to review for coreboot: 4715d6b Poison the stack to uncover programming errors
by Ronald G. Minnich 12 Jul '12

12 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1221 -gerrit commit 4715d6b4706fb78e9073295b878b69a6cf37ab6f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Jul 12 11:21:51 2012 -0700 Poison the stack to uncover programming errors Code can easily make the mistake of using uninitialized values or, in assembly, mistakenly dereferencing stack pointers when an address is desired. Set the stack to a non-zero value which is also (by testing) a pointer which will crash coreboot if used. This poisoning has uncovered at least one bug. Change-Id: I4affb9a14b96611e8bf83cb82636e47913025a5d Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/lib/c_start.S | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index fd9dce7..9c1fdb1 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -16,17 +16,21 @@ _start: post_code(POST_ENTRY_C_START) /* post 13 */ - /** clear stack */ + /** poison the stack. Code should not count on the + * stack being full of zeros. This stack poisoning + * recently uncovered a bug in the broadcast SIPI + * code. + */ cld leal _stack, %edi movl $_estack, %ecx subl %edi, %ecx shrl $2, %ecx /* it is 32 bit aligned, right? */ - xorl %eax, %eax + movl $0xDEADBEEF, %eax rep stosl - /** clear bss */ + /** clear bss, which unlike the stack is zero by definition */ leal _bss, %edi movl $_ebss, %ecx subl %edi, %ecx

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New patch to review for coreboot: fa073e1 IOAPIC: hook up driver in Kconfig
by Sven Schnelle 12 Jul '12

12 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1219 -gerrit commit fa073e1cbf85191f1f2e21924a00e154b1fdc3c9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jul 11 21:45:46 2012 +0200 IOAPIC: hook up driver in Kconfig Missed to add the driver to Kconfig and Makefile.inc. Change-Id: I64b02abc5de2f6483f610436ebb38a7ca433f9b6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/drivers/generic/Kconfig | 2 +- src/drivers/generic/Makefile.inc | 1 + 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/drivers/generic/Kconfig b/src/drivers/generic/Kconfig index fbbfeb1..597a186 100644 --- a/src/drivers/generic/Kconfig +++ b/src/drivers/generic/Kconfig @@ -1,3 +1,3 @@ source src/drivers/generic/debug/Kconfig source src/drivers/generic/generic/Kconfig - +source src/drivers/generic/ioapic/Kconfig diff --git a/src/drivers/generic/Makefile.inc b/src/drivers/generic/Makefile.inc index 08e6cc5..802aac0 100644 --- a/src/drivers/generic/Makefile.inc +++ b/src/drivers/generic/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += debug subdirs-y += generic +subdirs-y += ioapic

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coreboot July 2012