coreboot June 2012

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Trac reminder: list of new ticket(s)
by coreboot tracker 11 Jun '12

11 Jun '12

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New patch to review for coreboot: bd563e6 udelay: add missing bus frequency
by Sven Schnelle 10 Jun '12

10 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1099 -gerrit commit bd563e66681569f8b010f43a2289aa9d82537ec3 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 10 19:03:36 2012 +0200 udelay: add missing bus frequency commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/cpu/x86/lapic/apic_timer.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index bb6cca7..a4106d4 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -34,7 +34,7 @@ static int set_timer_fsb(void) { struct cpuinfo_x86 c; int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; - int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 }; + int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 }; get_fms(&c, cpuid_eax(1)); if (c.x86 != 6) @@ -45,7 +45,7 @@ static int set_timer_fsb(void) case 0x1c: /* Atom */ timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; break; - case 0xf: /* Core 2*/ + case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; break;

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Boots from PCI add-on card on Intel ICHs
by Kyösti Mälkki 10 Jun '12

10 Jun '12

Hi I did not find this method of bypassing the mainboard flash chip and booting from PCI add-on card documented or discussed before. The nice think in this is that neither mainboard or its flash needs to be modified. Good news in the case of a soldered flash and this method may work with mini-PCI slots on laptops too. For pre-ICH6 the key is in subtractive PCI decode. This has been supported in 82801 chipset from the early days and is briefly documented in ICH3 datasheet [1], see 5.1.1. PCI Bus interface. This decode mode is on by default and there is no documentation of a hw bootstrap that could disable it. For ICH7 onwards there are HW bootstraps to select between LPC/SPI/PCI. If you don't know where the bootstraps are, go with SPI and forget about this PCI add-on boot. To try this, I have modified a PCI PATA-RAID card as follows: I cut the PCI RST# signal from card edge to controller, put a jumper to close it for normal boots and placed a weak 10kOhm pull-up to Vio on the chip side. With this I have succesfully done the following on a ICH4 based mainboard: 1. I built SerialICE as usual and programmed the option ROM of the modified PCI card with it. 2. I set the PCI config BAR for that option ROM as 0xfffe0000. I had this hacked in flashrom, setpci might work as well. This was 128kB region while my flash was actually 64kB. 3. Reset the machine, but not the PCI card. I simply removed the jumper on the RST# signal on the PCI card before giving reboot command. 4. I got into SerialICE prompt. Should go without saying: Code run from option ROM must not switch from subtractive to positive PCI decode. I also think the PCI slot used must be directly on the southbridge PCI bus and not behind some other PCI bridge. To use this on cold boots and as a recovery method some means to default that config BAR for option ROM on cold power-on is required. Custom PCI FPGA can do that for sure, other ideas are welcome. Kyösti [1] http://www.intel.com/content/dam/doc/datasheet/82801ca-io-controller-hub-3-…

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Re: [coreboot] VGA Option ROM
by Kevin O'Connor 10 Jun '12

10 Jun '12

On Sat, Jun 09, 2012 at 09:17:34PM +0200, Wolfgang Kamp - datakamp wrote: > Hi, > > When execution of VGA option ROM is configured in seabios, > seabios first scans all PCI devices and looks for a vga type device as you can see in my attached log. > If seabios finds a pci vga device then it looks for a suitable VGA BIOS (Vendor id:Device id / 1002:9804) in CBFS. > But if seabios does not find a vga device, it doesn't look for the VGA BIOS. That is what happens. > In my issue seabios can only find the pci VGA device if I first enabled VGA ROM execution in coreboot. > If seabios finds the vga device it will also find the correct VGA BIOS in CBFS and executes it. > The log shows this. The issue is that the pci enumertion fails in seabios and it does not list all available devices. > Why is it broken? It could be a coreboot or seabios problem. Looks like a coreboot issue to me. The PCI device does not appear to be present when SeaBIOS doesn't find it. As Ron indicated in another email, it looks like coreboot needs an option to enable the vga but not run the rom for your board. -Kevin

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Re: [coreboot] VGA Option ROM
by Wolfgang Kamp - datakamp 09 Jun '12

09 Jun '12

Hi, When execution of VGA option ROM is configured in seabios, seabios first scans all PCI devices and looks for a vga type device as you can see in my attached log. If seabios finds a pci vga device then it looks for a suitable VGA BIOS (Vendor id:Device id / 1002:9804) in CBFS. But if seabios does not find a vga device, it doesn't look for the VGA BIOS. That is what happens. In my issue seabios can only find the pci VGA device if I first enabled VGA ROM execution in coreboot. If seabios finds the vga device it will also find the correct VGA BIOS in CBFS and executes it. The log shows this. The issue is that the pci enumertion fails in seabios and it does not list all available devices. Why is it broken? It could be a coreboot or seabios problem. Regards Wolfgang Von: QingPei Wang [mailto:wangqingpei@gmail.com] Gesendet: Samstag, 9. Juni 2012 20:48 An: Wolfgang Kamp - datakamp Cc: Coreboot Betreff: Re: [coreboot] VGA Option ROM what does "seabios cannot run the vga option ROM" looks like? did seabios find the vbios from CBFS? 1. found, but vbios executed failed? 2. seabios could not find vbios? Best wishes QingPei Wang Phone: 86+018930528086 On Fri, Jun 8, 2012 at 11:42 PM, Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de<mailto:wmkamp@datakamp.de>> wrote: Normally seabios should run the option ROMs. But in my issue seabios cannot run the vga option ROM, because it cannot find the vga pci device. Seabios first looks for the vga pci device and if it finds a vga device it searches in CBFS for the correct ROM file. So I think there is a pci enumeration problem which seems to be caused from coreboot. Wolfgang -----Ursprüngliche Nachricht----- Von: ron minnich [mailto:rminnich@gmail.com<mailto:rminnich@gmail.com>] Gesendet: Freitag, 8. Juni 2012 17:16 An: Wolfgang Kamp - datakamp Cc: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Betreff: Re: [coreboot] VGA Option ROM I wonder if we need another option :-( to configure the rom but not run it? ron -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] VGA Option ROM
by QingPei Wang 09 Jun '12

09 Jun '12

what does "seabios cannot run the vga option ROM" looks like? did seabios find the vbios from CBFS? 1. found, but vbios executed failed? 2. seabios could not find vbios? Best wishes QingPei Wang Phone: 86+018930528086 On Fri, Jun 8, 2012 at 11:42 PM, Wolfgang Kamp - datakamp < wmkamp(a)datakamp.de> wrote: > Normally seabios should run the option ROMs. But in my issue seabios > cannot run the vga option ROM, > because it cannot find the vga pci device. > Seabios first looks for the vga pci device and if it finds a vga device it > searches in CBFS for the correct ROM file. > So I think there is a pci enumeration problem which seems to be caused > from coreboot. > > Wolfgang > > -----Ursprüngliche Nachricht----- > Von: ron minnich [mailto:rminnich@gmail.com] > Gesendet: Freitag, 8. Juni 2012 17:16 > An: Wolfgang Kamp - datakamp > Cc: coreboot(a)coreboot.org > Betreff: Re: [coreboot] VGA Option ROM > > I wonder if we need another option :-( to configure the rom but not run it? > > ron > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] PCIe devices not enabled on amd/persimmon
by She Kairui 09 Jun '12

09 Jun '12

2012/6/9, Andy Sharp <andywyse6(a)gmail.com>: > It's a persimmon board ~:^) > > I'd be happy to test any patches. Meanwhile, I'm working on a patch to > properly enable the southbridge PCIe devices so they can be scanned. > Wolfgang (Wolfie?) is quite correct, the code that enables/deresets those > PCIe ports happens after the bus is scanned. When nothing shows up on the > bus scan, the code powers down those devices right after it [too late] > powers them up. Broken. > > This persimmon board is made by iBASE. and is a mini-ITX. It has a PCIe > slot and a mini-PCIe card socket on the sb800 PCIe ports. I have a persimmon Rev. D board, I found NONE of the PCIe devices is from SB800 GPP. You can double check it by booting from the factory BIOS. Thanks -- Kerry Sheh > I may have earlier said that it had a USB3 ctlr, that was my bad. So many twisty > passages.... > > I'll try out various combinations of the various patches you good folks > have been throwing my way, plus some of my own ideas and let the list know > what happens. > > Cheers, > > a > > > > On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave(a)se-eng.com> wrote: > >> There shouldn't be any need to guess if it is a Persimmon. On a >> Persimmon board, next to the SATA connectors there should be >> printing that says "DB FT1". >> >> The Persimmon can also have up to two PCIe Ethernet chips on it. >> >> dave >> >> ----- Original Message ----- >> > From: "Zheng Bao" <Zheng.Bao(a)amd.com> >> > To: "Andy Sharp" <andywyse6(a)gmail.com> >> > Cc: "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> >> > Sent: Friday, June 8, 2012 5:37:58 AM >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon >> > >> > Hi, Andy, >> > The persimmon board I have got doesn't have any PCIe slot or onboard >> > PCIe device attached to SB800. And I am wondering if you actually >> > use a inagua board, which has the same APU & SB with persimmon and 2 >> > minipcie slots other than that. >> > >> > Let us assume you are testing on Inagua. >> > Here is my patch for the PCIe on SB800. There was a bug. It is just a >> > workaround patch, not ready for submitting. >> > >> > This patch can fix the sb800/pcie issue on Inagua. If you have your >> > work based on persimmon, please note the devicetree.cb should be >> > modify as Inagua. >> > The dev15func[0123] should be enabled and the gpp_configuration >> > should be 4. >> > >> > Joe >> > >> > diff --git a/src/southbridge/amd/cimx/sb800/late.c >> > b/src/southbridge/amd/cimx/sb800/late.c >> > index 0ce82b3..34cd937 100644 >> > --- a/src/southbridge/amd/cimx/sb800/late.c >> > +++ b/src/southbridge/amd/cimx/sb800/late.c >> > @@ -29,6 +29,7 @@ >> > #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ >> > #include "cfg.h" /* sb800 Cimx configuration */ >> > #include "chip.h" /* struct >> southbridge_amd_cimx_sb800_config */ >> > +#include "smbus.h" >> > #include "sb_cimx.h" /* AMD CIMX wrapper entries */ >> > >> > >> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = { >> > .set_resources = pci_dev_set_resources, >> > .enable_resources = pci_bus_enable_resources, >> > .init = pci_init, >> > + .enable = 0, >> > .scan_bus = pci_scan_bridge, >> > .reset_bus = pci_bus_reset, >> > .ops_pci = &lops_pci, >> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = { >> > .reset_bus = pci_bus_reset, >> > .ops_pci = &lops_pci, >> > }; >> > - >> > +#if 0 >> > /* 0:15:0 PCIe PortA */ >> > static const struct pci_driver PORTA_driver __pci_driver = { >> > .ops = &bridge_ops, >> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver >> > __pci_driver = { >> > .vendor = PCI_VENDOR_ID_ATI, >> > .device = PCI_DEVICE_ID_ATI_SB800_PCIED, >> > }; >> > - >> > +#endif >> > >> > /** >> > * South Bridge CIMx ramstage entry point wrapper. >> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev) >> > switch (dev->path.pci.devfn) { >> > case (0x11 << 3) | 0: /* 0:11.0 SATA */ >> > /* the first sb800 device */ >> > + abcfg_reg(0xc0, 0x1FF, 0x0F4); >> > sb800_cimx_config(sb_config); >> > >> > if (dev->enabled) { >> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev) >> > sb_config->GppLinkConfig = >> sb_chip->gpp_configuration; >> > } >> > break; >> > + case (0x15 << 3) | 1: >> > + case (0x15 << 3) | 2: >> > + case (0x15 << 3) | 3: >> > + //abcfg_reg(0xc0, 0xF0, 0x00); >> > + break; >> > >> > case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ >> > sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; >> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev) >> > /* call the CIMX entry at the last sb800 device, >> > * so make sure the mainboard devicetree is complete >> > */ >> > + abcfg_reg(0xc0, 0x100, 0x100); >> > #if CONFIG_HAVE_ACPI_RESUME >> > if (acpi_slp_type != 3) >> > sb_Before_Pci_Init(); >> > >> > >> > >> > >> > From: coreboot-bounces(a)coreboot.org >> > [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Sharp >> > Sent: Friday, June 08, 2012 8:57 AM >> > To: coreboot(a)coreboot.org >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon >> > >> > Hi Steve, >> > >> > Makes no [substantive] difference. All that does is cause 4 extra >> > lines to be added to the console output: >> > >> > . >> > . >> > . >> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling >> > it. >> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling >> > it. >> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling >> > it. >> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling >> > it. >> > . >> > . >> > . >> > >> > >> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich >> > <steve.goodrich(a)se-eng.com> wrote: >> > ARG.. Thanks, Outlook. :P >> > >> > Andy, >> > >> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon >> > folder. Mine shows: >> > >> > device pci 15.0 off end # PCIe PortA >> > device pci 15.1 off end # PCIe PortB >> > device pci 15.2 off end # PCIe PortC >> > device pci 15.3 off end # PCIe PortD >> > >> > I'm not 100% certain, but I suspect that changing these from "off" to >> > "on" will enable the devices. Try the change and see if the console >> > output starts reflecting the devices you're looking for. >> > >> > -- Steve G. >> > >> > >> > >> > From: coreboot-bounces(a)coreboot.org >> > [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Sharp >> > Sent: Thursday, June 07, 2012 2:31 PM >> > To: coreboot(a)coreboot.org >> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon >> > >> > Howdy, >> > >> > I've got an AMD/persimmon board, with the agesa family 14 northbridge >> > on the CPU, and the SB800 southbridge. Both have 4 PCIe ports on >> > them, but coreboot isn't enabling or enumerating any of the PCIe >> > devices on the SB800. Does anyone have any ideas for me? The two >> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot. >> > >> > >> > Pasting the console output below for those interested: >> > >> > >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 >> > starting... >> > POST: 0x34 >> > BSP Family_Model: 00500f20 >> > cpu_init_detectedx = 00000000 >> > POST: 0x35 >> > agesawrapper_amdinitmmio passed. >> > POST: 0x37 >> > agesawrapper_amdinitreset passed. >> > POST: 0x39 >> > agesawrapper_amdinitearly POST: 0x34 >> > BSP Family_Model: 00500f20 >> > cpu_init_detectedx = 00000001 >> > POST: 0x35 >> > agesawrapper_amdinitmmio passed. >> > POST: 0x37 >> > agesawrapper_amdinitreset passed. >> > POST: 0x39 >> > agesawrapper_amdinitearly passed. >> > SLP_TYP type was 0 >> > POST: 0x40 >> > agesawrapper_amdinitpost >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > SLP_TYP type was 0 >> > error level: 4 >> > POST: 0x42 >> > agesawrapper_amdinitenv SLP_TYP type was 0 >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 >> > SLP_TYP type was 0 >> > SLP_TYP type was 0 >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 >> > SLP_TYP type was 0 >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 >> > SLP_TYP type was 0 >> > SLP_TYP type was 0 >> > SLP_TYP type was 0 >> > passed. >> > POST: 0x43 >> > POST: 0x44 >> > POST: 0x50 >> > Loading image. >> > CBFS: Looking for 'fallback/coreboot_ram' >> > CBFS: found. >> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), >> > entry @ 0x200000 >> > Jumping to image. >> > POST: 0x80 >> > POST: 0x39 >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 >> > booting... >> > POST: 0x40 >> > Enumerating buses... >> > Show all devs...Before device enumeration. >> > Root Device: enabled 1 >> > APIC_CLUSTER: 0: enabled 1 >> > APIC: 00: enabled 1 >> > PCI_DOMAIN: 0000: enabled 1 >> > PCI: 00:00.0: enabled 1 >> > PCI: 00:01.0: enabled 1 >> > PCI: 00:01.1: enabled 1 >> > PCI: 00:04.0: enabled 1 >> > PCI: 00:05.0: enabled 0 >> > PCI: 00:06.0: enabled 0 >> > PCI: 00:07.0: enabled 0 >> > PCI: 00:08.0: enabled 0 >> > PCI: 00:11.0: enabled 1 >> > PCI: 00:12.0: enabled 1 >> > PCI: 00:12.1: enabled 1 >> > PCI: 00:12.2: enabled 1 >> > PCI: 00:13.0: enabled 1 >> > PCI: 00:13.1: enabled 1 >> > PCI: 00:13.2: enabled 1 >> > PCI: 00:14.0: enabled 1 >> > I2C: 00:50: enabled 1 >> > I2C: 00:51: enabled 1 >> > PCI: 00:14.1: enabled 1 >> > PCI: 00:14.2: enabled 1 >> > PCI: 00:14.3: enabled 1 >> > PNP: 004e.0: enabled 0 >> > PNP: 004e.3: enabled 0 >> > PNP: 004e.4: enabled 0 >> > PNP: 004e.5: enabled 1 >> > PNP: 004e.6: enabled 0 >> > PNP: 004e.a: enabled 0 >> > PNP: 004e.10: enabled 1 >> > PNP: 004e.11: enabled 0 >> > PCI: 00:14.4: enabled 1 >> > PCI: 00:14.5: enabled 1 >> > PCI: 00:15.0: enabled 0 >> > PCI: 00:15.1: enabled 0 >> > PCI: 00:15.2: enabled 0 >> > PCI: 00:15.3: enabled 0 >> > PCI: 00:16.0: enabled 0 >> > PCI: 00:16.2: enabled 0 >> > PCI: 00:18.0: enabled 1 >> > PCI: 00:18.1: enabled 1 >> > PCI: 00:18.2: enabled 1 >> > PCI: 00:18.3: enabled 1 >> > PCI: 00:18.4: enabled 1 >> > PCI: 00:18.5: enabled 1 >> > PCI: 00:18.6: enabled 1 >> > PCI: 00:18.7: enabled 1 >> > Compare with tree... >> > Root Device: enabled 1 >> > APIC_CLUSTER: 0: enabled 1 >> > APIC: 00: enabled 1 >> > PCI_DOMAIN: 0000: enabled 1 >> > PCI: 00:00.0: enabled 1 >> > PCI: 00:01.0: enabled 1 >> > PCI: 00:01.1: enabled 1 >> > PCI: 00:04.0: enabled 1 >> > PCI: 00:05.0: enabled 0 >> > PCI: 00:06.0: enabled 0 >> > PCI: 00:07.0: enabled 0 >> > PCI: 00:08.0: enabled 0 >> > PCI: 00:11.0: enabled 1 >> > PCI: 00:12.0: enabled 1 >> > PCI: 00:12.1: enabled 1 >> > PCI: 00:12.2: enabled 1 >> > PCI: 00:13.0: enabled 1 >> > PCI: 00:13.1: enabled 1 >> > PCI: 00:13.2: enabled 1 >> > PCI: 00:14.0: enabled 1 >> > I2C: 00:50: enabled 1 >> > I2C: 00:51: enabled 1 >> > PCI: 00:14.1: enabled 1 >> > PCI: 00:14.2: enabled 1 >> > PCI: 00:14.3: enabled 1 >> > PNP: 004e.0: enabled 0 >> > PNP: 004e.3: enabled 0 >> > PNP: 004e.4: enabled 0 >> > PNP: 004e.5: enabled 1 >> > PNP: 004e.6: enabled 0 >> > PNP: 004e.a: enabled 0 >> > PNP: 004e.10: enabled 1 >> > PNP: 004e.11: enabled 0 >> > PCI: 00:14.4: enabled 1 >> > PCI: 00:14.5: enabled 1 >> > PCI: 00:15.0: enabled 0 >> > PCI: 00:15.1: enabled 0 >> > PCI: 00:15.2: enabled 0 >> > PCI: 00:15.3: enabled 0 >> > PCI: 00:16.0: enabled 0 >> > PCI: 00:16.2: enabled 0 >> > PCI: 00:18.0: enabled 1 >> > PCI: 00:18.1: enabled 1 >> > PCI: 00:18.2: enabled 1 >> > PCI: 00:18.3: enabled 1 >> > PCI: 00:18.4: enabled 1 >> > PCI: 00:18.5: enabled 1 >> > PCI: 00:18.6: enabled 1 >> > PCI: 00:18.7: enabled 1 >> > Mainboard Persimmon Enable. >> > SLP_TYP type was 0 >> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000 >> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = >> > 0x00000000 >> > persimmon_enable: uma size 0x18000000, memory start 0x67000000 >> > scan_static_bus for Root Device >> > APIC_CLUSTER: 0 enabled >> > PCI_DOMAIN: 0000 enabled >> > APIC_CLUSTER: 0 scanning... >> > AP siblings=1 >> > CPU: APIC: 00 enabled >> > CPU: APIC: 01 enabled >> > PCI_DOMAIN: 0000 scanning... >> > PCI: pci_scan_bus for bus 00 >> > POST: 0x24 >> > PCI: 00:00.0 [1022/1510] ops >> > PCI: 00:00.0 [1022/1510] enabled >> > PCI: 00:01.0 [1002/9804] enabled >> > Capability: type 0x01 @ 0x50 >> > Capability: type 0x10 @ 0x58 >> > Capability: type 0x05 @ 0xa0 >> > Capability: type 0x0d @ 0xb0 >> > Capability: type 0x08 @ 0xb8 >> > Capability: type 0x01 @ 0x50 >> > Capability: type 0x10 @ 0x58 >> > PCI: 00:04.0 subordinate bus PCI Express >> > PCI: 00:04.0 [1022/1512] enabled >> > sb800_enable() SLP_TYP type was 0 >> > PCI: 00:11.0 [1002/4393] ops >> > PCI: 00:11.0 [1002/4393] enabled >> > sb800_enable() PCI: 00:12.0 [1002/4397] ops >> > PCI: 00:12.0 [1002/4397] enabled >> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling >> > it. >> > sb800_enable() PCI: 00:12.2 [1002/4396] ops >> > PCI: 00:12.2 [1002/4396] enabled >> > sb800_enable() PCI: 00:13.0 [1002/4397] ops >> > PCI: 00:13.0 [1002/4397] enabled >> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling >> > it. >> > sb800_enable() PCI: 00:13.2 [1002/4396] ops >> > PCI: 00:13.2 [1002/4396] enabled >> > sb800_enable() sm_init(). >> > IOAPIC: Clearing IOAPIC at 0xfec00000 >> > IOAPIC: 23 interrupts >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 >> > IOAPIC: Initializing IOAPIC at 0xfec00000 >> > IOAPIC: Bootstrap Processor Local APIC = 0x00 >> > IOAPIC: ID = 0x02 >> > IOAPIC: 23 interrupts >> > IOAPIC: Enabling interrupts on FSB >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 >> > PCI: 00:14.0 [1002/4385] enabled >> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling >> > it. >> > sb800_enable() hda enabled >> > PCI: 00:14.2 [1002/4383] ops >> > PCI: 00:14.2 [1002/4383] enabled >> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops >> > PCI: 00:14.3 [1002/439d] enabled >> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops >> > PCI: 00:14.4 [1002/4384] enabled >> > sb800_enable() PCI: 00:14.5 [1002/4399] ops >> > PCI: 00:14.5 [1002/4399] enabled >> > sb800_enable() sb800_enable() sb800_enable() sb800_enable() >> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled >> > PCI: 00:18.1 [1022/1701] enabled >> > PCI: 00:18.2 [1022/1702] enabled >> > PCI: 00:18.3 [1022/1703] enabled >> > PCI: 00:18.4 [1022/1704] enabled >> > PCI: 00:18.5 [1022/1718] enabled >> > PCI: 00:18.6 [1022/1716] enabled >> > PCI: 00:18.7 [1022/1719] enabled >> > POST: 0x25 >> > PCI: Left over static devices: >> > PCI: 00:01.1 >> > PCI: Check your devicetree.cb. >> > do_pci_scan_bridge for PCI: 00:04.0 >> > PCI: pci_scan_bus for bus 01 >> > POST: 0x24 >> > PCI: 01:00.0 [10ec/8168] enabled >> > POST: 0x25 >> > PCI: pci_scan_bus returning with max=001 >> > POST: 0x55 >> > >> > -- >> > coreboot mailing list: coreboot(a)coreboot.org >> > http://www.coreboot.org/mailman/listinfo/coreboot >> > >> > >> > -- >> > coreboot mailing list: coreboot(a)coreboot.org >> > http://www.coreboot.org/mailman/listinfo/coreboot >> >

1 0

Patch merged into coreboot/master: 2541489 libpayload: Add timeouts in the UHCI USB driver
by gerrit＠coreboot.org 09 Jun '12

09 Jun '12

the following patch was just integrated into master: commit 2541489b34e3a5d1fa4a96fdd4dfd7bcbaa92ac5 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon May 21 14:23:03 2012 +0200 libpayload: Add timeouts in the UHCI USB driver We should always have some timeout when we wait for the hardware. This adds missing timeouts to the UHCI driver. Change-Id: Ic37b95ce12ff3ff5efe3e7ca346090946f6ee7de Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Jun 9 13:12:58 2012, giving +2 See http://review.coreboot.org/1073 for details. -gerrit

1 0

Patch merged into coreboot/master: b2d5bd2 libpayload: Fix an integer overflow in USB mass storage
by gerrit＠coreboot.org 09 Jun '12

09 Jun '12

the following patch was just integrated into master: commit b2d5bd239402dd8410fdab99fcee678e24ab9308 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon May 21 13:59:43 2012 +0200 libpayload: Fix an integer overflow in USB mass storage Change-Id: I3d618497016478ea727c520e866d27dbc3ebf9af Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Jun 9 13:11:35 2012, giving +2 See http://review.coreboot.org/1070 for details. -gerrit

1 0

Re: [coreboot] PCIe devices not enabled on amd/persimmon
by Bao, Zheng 09 Jun '12

09 Jun '12

Hi, Andy, The persimmon board I have got doesn't have any PCIe slot or onboard PCIe device attached to SB800. And I am wondering if you actually use a inagua board, which has the same APU & SB with persimmon and 2 minipcie slots other than that. Let us assume you are testing on Inagua. Here is my patch for the PCIe on SB800. There was a bug. It is just a workaround patch, not ready for submitting. This patch can fix the sb800/pcie issue on Inagua. If you have your work based on persimmon, please note the devicetree.cb should be modify as Inagua. The dev15func[0123] should be enabled and the gpp_configuration should be 4. Joe diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 0ce82b3..34cd937 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -29,6 +29,7 @@ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ +#include "smbus.h" #include "sb_cimx.h" /* AMD CIMX wrapper entries */ @@ -273,6 +274,7 @@ static struct device_operations pci_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, + .enable = 0, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, @@ -295,7 +297,7 @@ struct device_operations bridge_ops = { .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, }; - +#if 0 /* 0:15:0 PCIe PortA */ static const struct pci_driver PORTA_driver __pci_driver = { .ops = &bridge_ops, @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver __pci_driver = { .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB800_PCIED, }; - +#endif /** * South Bridge CIMx ramstage entry point wrapper. @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev) switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ /* the first sb800 device */ + abcfg_reg(0xc0, 0x1FF, 0x0F4); sb800_cimx_config(sb_config); if (dev->enabled) { @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev) sb_config->GppLinkConfig = sb_chip->gpp_configuration; } break; + case (0x15 << 3) | 1: + case (0x15 << 3) | 2: + case (0x15 << 3) | 3: + //abcfg_reg(0xc0, 0xF0, 0x00); + break; case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ + abcfg_reg(0xc0, 0x100, 0x100); #if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) sb_Before_Pci_Init(); From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Sharp Sent: Friday, June 08, 2012 8:57 AM To: coreboot(a)coreboot.org Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon Hi Steve, Makes no [substantive] difference. All that does is cause 4 extra lines to be added to the console output: . . . sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling it. sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling it. sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling it. sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling it. . . . On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich <steve.goodrich(a)se-eng.com> wrote: ARG.. Thanks, Outlook. :P Andy, Check the devicetree.cb file in your ./src/mainboard/amd/persimmon folder. Mine shows: device pci 15.0 off end # PCIe PortA device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD I'm not 100% certain, but I suspect that changing these from "off" to "on" will enable the devices. Try the change and see if the console output starts reflecting the devices you're looking for. -- Steve G. From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Sharp Sent: Thursday, June 07, 2012 2:31 PM To: coreboot(a)coreboot.org Subject: [coreboot] PCIe devices not enabled on amd/persimmon Howdy, I've got an AMD/persimmon board, with the agesa family 14 northbridge on the CPU, and the SB800 southbridge. Both have 4 PCIe ports on them, but coreboot isn't enabling or enumerating any of the PCIe devices on the SB800. Does anyone have any ideas for me? The two devices on that southbridge are an NEC USB3 and a Mini-PCIe slot. Pasting the console output below for those interested: coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 starting... POST: 0x34 BSP Family_Model: 00500f20 cpu_init_detectedx = 00000000 POST: 0x35 agesawrapper_amdinitmmio passed. POST: 0x37 agesawrapper_amdinitreset passed. POST: 0x39 agesawrapper_amdinitearly POST: 0x34 BSP Family_Model: 00500f20 cpu_init_detectedx = 00000001 POST: 0x35 agesawrapper_amdinitmmio passed. POST: 0x37 agesawrapper_amdinitreset passed. POST: 0x39 agesawrapper_amdinitearly passed. SLP_TYP type was 0 POST: 0x40 agesawrapper_amdinitpost EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. SLP_TYP type was 0 error level: 4 POST: 0x42 agesawrapper_amdinitenv SLP_TYP type was 0 BiosAllocateBuffer BiosHeapBaseAddr: 10000 SLP_TYP type was 0 SLP_TYP type was 0 BiosAllocateBuffer BiosHeapBaseAddr: 10000 SLP_TYP type was 0 BiosAllocateBuffer BiosHeapBaseAddr: 10000 SLP_TYP type was 0 SLP_TYP type was 0 SLP_TYP type was 0 passed. POST: 0x43 POST: 0x44 POST: 0x50 Loading image. CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), entry @ 0x200000 Jumping to image. POST: 0x80 POST: 0x39 coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 004e.0: enabled 0 PNP: 004e.3: enabled 0 PNP: 004e.4: enabled 0 PNP: 004e.5: enabled 1 PNP: 004e.6: enabled 0 PNP: 004e.a: enabled 0 PNP: 004e.10: enabled 1 PNP: 004e.11: enabled 0 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:15.1: enabled 0 PCI: 00:15.2: enabled 0 PCI: 00:15.3: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 004e.0: enabled 0 PNP: 004e.3: enabled 0 PNP: 004e.4: enabled 0 PNP: 004e.5: enabled 1 PNP: 004e.6: enabled 0 PNP: 004e.a: enabled 0 PNP: 004e.10: enabled 1 PNP: 004e.11: enabled 0 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:15.1: enabled 0 PCI: 00:15.2: enabled 0 PCI: 00:15.3: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 Mainboard Persimmon Enable. SLP_TYP type was 0 persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000 persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000 persimmon_enable: uma size 0x18000000, memory start 0x67000000 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... AP siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [1022/1510] ops PCI: 00:00.0 [1022/1510] enabled PCI: 00:01.0 [1002/9804] enabled Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:04.0 subordinate bus PCI Express PCI: 00:04.0 [1022/1512] enabled sb800_enable() SLP_TYP type was 0 PCI: 00:11.0 [1002/4393] ops PCI: 00:11.0 [1002/4393] enabled sb800_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it. sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it. sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb800_enable() sm_init(). IOAPIC: Clearing IOAPIC at 0xfec00000 IOAPIC: 23 interrupts IOAPIC: reg 0x00000000 value 0x00000000 0x00010000 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb800_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb800_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb800_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled PCI: 00:18.1 [1022/1701] enabled PCI: 00:18.2 [1022/1702] enabled PCI: 00:18.3 [1022/1703] enabled PCI: 00:18.4 [1022/1704] enabled PCI: 00:18.5 [1022/1718] enabled PCI: 00:18.6 [1022/1716] enabled PCI: 00:18.7 [1022/1719] enabled POST: 0x25 PCI: Left over static devices: PCI: 00:01.1 PCI: Check your devicetree.cb. do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [10ec/8168] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot June 2012