coreboot June 2012

coreboot@coreboot.org

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241 discussions

New patch to review for coreboot: b84b83a mptable: Fix 'mptable.c:1019:12: warning: ‘c’ may be used uninitialized in this function'
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1110 -gerrit commit b84b83a5a1ed0eb2b4a3e3ce49559ff61f26a4a2 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 09:22:17 2012 +0200 mptable: Fix 'mptable.c:1019:12: warning: ‘c’ may be used uninitialized in this function' Change-Id: Icf6968f5bcbbe28c3a2a1d6ee7c1fd0be583f182 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- util/mptable/mptable.c | 11 +++-------- 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/util/mptable/mptable.c b/util/mptable/mptable.c index 7c3033e..3ce2493 100644 --- a/util/mptable/mptable.c +++ b/util/mptable/mptable.c @@ -997,9 +997,7 @@ lookupBusType( char* name ) static void busEntry( void ) { - int x; char name[ 8 ]; - char c; BusEntry entry; /* read it into local memory */ @@ -1013,12 +1011,9 @@ busEntry( void ) printf( "\t " ); pnstr( entry.busType, 6 ); printf( "\n" ); } - for ( x = 0; x < 6; ++x ) { -// if ( (c = entry.busType[ x ]) == ' ' ) - //break; - name[ x ] = c; - } - name[ x ] = '\0'; + memset(name, '\0', sizeof(name)); + strncpy(name, (char *)entry.busType, 6); + busses[ entry.busID ] = lookupBusType( name ); printf("\tsmp_write_bus(mc, %d, \"", entry.busID); pnstr( entry.busType, 6 );

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New patch to review for coreboot: bf2873d mptable: remove unused variable
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1109 -gerrit commit bf2873d14cbc48ca35efb6f477a8e671f567b05b Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 09:14:08 2012 +0200 mptable: remove unused variable Change-Id: I1ff7e040b5aafcdb05a3669158ae94551981e747 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- util/mptable/mptable.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/util/mptable/mptable.c b/util/mptable/mptable.c index 9488e36..7c3033e 100644 --- a/util/mptable/mptable.c +++ b/util/mptable/mptable.c @@ -731,7 +731,7 @@ MPConfigTableHeader( uint32_t pap ) vm_offset_t paddr; mpcth_t cth; int x; - int totalSize, t; + int totalSize; int count, c; int type; @@ -804,7 +804,7 @@ MPConfigTableHeader( uint32_t pap ) printf( "--\nProcessors:\tAPIC ID\tVersion\tState" "\t\tFamily\tModel\tStep\tFlags\n" ); } - for ( t = totalSize, c = count; c; c-- ) { + for ( c = count; c; c-- ) { if ( readType() == 0 ) processorEntry(); totalSize -= basetableEntryTypes[ 0 ].length; @@ -812,7 +812,7 @@ MPConfigTableHeader( uint32_t pap ) /* process all the busses */ printf( "/*Bus:\t\tBus ID\tType*/\n" ); - for ( t = totalSize, c = count; c; c-- ) { + for ( c = count; c; c-- ) { if ( readType() == 1 ) busEntry(); totalSize -= basetableEntryTypes[ 1 ].length; @@ -820,7 +820,7 @@ MPConfigTableHeader( uint32_t pap ) /* process all the apics */ printf( "/*I/O APICs:\tAPIC ID\tVersion\tState\t\tAddress*/\n" ); - for ( t = totalSize, c = count; c; c-- ) { + for ( c = count; c; c-- ) { if ( readType() == 2 ) ioApicEntry(); totalSize -= basetableEntryTypes[ 2 ].length; @@ -828,7 +828,7 @@ MPConfigTableHeader( uint32_t pap ) /* process all the I/O Ints */ printf( "/*I/O Ints:\tType\tPolarity Trigger\tBus ID\t IRQ\tAPIC ID\tPIN#\n*/" ); - for ( t = totalSize, c = count; c; c-- ) { + for ( c = count; c; c-- ) { if ( readType() == 3 ) intEntry(); totalSize -= basetableEntryTypes[ 3 ].length; @@ -836,7 +836,7 @@ MPConfigTableHeader( uint32_t pap ) /* process all the Local Ints */ printf( "/*Local Ints:\tType\tPolarity Trigger\tBus ID\t IRQ\tAPIC ID\tPIN#*/\n" ); - for ( t = totalSize, c = count; c; c-- ) { + for ( c = count; c; c-- ) { if ( readType() == 4 ) lintEntry(); totalSize -= basetableEntryTypes[ 4 ].length;

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New patch to review for coreboot: 2feda65 mptable: rename LAPIC_ADDR to LOCAL_APIC_ADDR
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1107 -gerrit commit 2feda65b869662c41e964db3b9a15198cf7357d4 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 08:54:51 2012 +0200 mptable: rename LAPIC_ADDR to LOCAL_APIC_ADDR It was renamed in coreboot, so have mptable generate correct code. Change-Id: I9579209f9f47b756d8ccab63b6f942d22d53d79d Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- util/mptable/mptable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/mptable/mptable.c b/util/mptable/mptable.c index ce775dd..92ba544 100644 --- a/util/mptable/mptable.c +++ b/util/mptable/mptable.c @@ -311,7 +311,7 @@ char *preamble[] = { "", " mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);", "", -" mptable_init(mc, \"TODO \", LAPIC_ADDR);", +" mptable_init(mc, \"TODO \", LOCAL_APIC_ADDR);", "", " smp_write_processors(mc);", "",

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New patch to review for coreboot: 52a6933 libpayload: reg_base reading for USB EHCI driver
by Anton Kochkov 20 Jun '12

20 Jun '12

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1106 -gerrit commit 52a69339c11dd9df23b8e7d3df0f1ecea7a6cbf2 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Wed Jun 20 04:03:37 2012 +0400 libpayload: reg_base reading for USB EHCI driver Added reading registers base address for USB EHCI driver in ehci_init() function. Change-Id: I59443ca9823588d70822b4f14486caf217a5ac26 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- payloads/libpayload/drivers/usb/ehci.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 1094c78..31d176e 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -623,6 +623,7 @@ ehci_init (pcidev_t addr) controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; controller->bus_address = addr; + controller->reg_base = pci_read_config32 (controller->bus_address, 0x10); for (i = 0; i < 128; i++) { controller->devices[i] = 0; }

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New patch to review for coreboot: b9f4b09 libpayload: Fix detach_contoller in the USB driver
by Anton Kochkov 20 Jun '12

20 Jun '12

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1105 -gerrit commit b9f4b09e465b23cbaab10be2b637a6c82ae1e4cd Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Wed Jun 20 03:57:18 2012 +0400 libpayload: Fix detach_contoller in the USB driver Fixed usb controllers linked list walking in detach_controller() function Change-Id: Ia97c7ec814f75d2b1bfe185f160fb4cd32aa6fdb Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- payloads/libpayload/drivers/usb/usb.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 07735a2..42c73f3 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -63,6 +63,7 @@ detach_controller (hci_t *controller) it->next = controller->next; return; } + it = it->next; } } }

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Patch merged into coreboot/master: 44d75d5 Enable Intel PECI on Model 6fx CPUs
by gerrit＠coreboot.org 19 Jun '12

19 Jun '12

the following patch was just integrated into master: commit 44d75d5ad414de65861f7f9e59fb0bd7891ca138 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jun 19 18:00:01 2012 +0200 Enable Intel PECI on Model 6fx CPUs Those CPUs support the PECI (Platform Environment Control Interface), so enable it. This interface is commonly used for tasks like fan control. Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Jun 19 18:31:43 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Jun 19 18:23:17 2012, giving +2 See http://review.coreboot.org/1104 for details. -gerrit

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New patch to review for coreboot: 44d75d5 Enable Intel PECI on Model 6fx CPUs
by Sven Schnelle 19 Jun '12

19 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1104 -gerrit commit 44d75d5ad414de65861f7f9e59fb0bd7891ca138 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jun 19 18:00:01 2012 +0200 Enable Intel PECI on Model 6fx CPUs Those CPUs support the PECI (Platform Environment Control Interface), so enable it. This interface is commonly used for tasks like fan control. Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/cpu/intel/model_6fx/model_6fx_init.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 033dfe6..106719e 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -127,6 +127,8 @@ static void configure_c_states(void) } #define IA32_MISC_ENABLE 0x1a0 +#define IA32_PECI_CTL 0x5a0 + static void configure_misc(void) { msr_t msr; @@ -170,6 +172,12 @@ static void configure_misc(void) msr.lo |= vid_max; wrmsr(IA32_PERF_CTL, msr); + + /* Enable PECI */ + msr = rdmsr(IA32_PECI_CTL); + msr.lo |= 1; + wrmsr(IA32_PECI_CTL, msr); + } #define PIC_SENS_CFG 0x1aa

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Re: [coreboot] ASUS M4A79XTD EVO - AMD RD790
by Christopher West 18 Jun '12

18 Jun '12

By the looks of it the early serial setup was part of the original m4a78-em port. This has been slightly altered to take into account the new superio device. I've check to the best of my knowledge that the address and data are correct for the superio. Is there anything specific that I can check for to make sure the early serial is correctly setup? Thanks, Chris > You will need to make changes to romstage.c and enable the > early_serial etc there. > > Marc

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Re: [coreboot] ASUS M4A79XTD EVO - AMD RD790
by Christopher West 18 Jun '12

18 Jun '12

That's good news, thanks Marc. I'll elaborate on what I've done so far then. I have a second flash chip which I'm using for coreboot and hot swapping on the motherboard for programming and running. I've tested builds of a few different Asus boards and found the m4a78-em does slightly more than the others which is not much, it doesn't boot and has no serial coms. Using the m4a78-em as a starting point, I have done the following; Modified the devicetree.cb file using information from lspci and lshw. Update the Kconfig for the different socket and memory. Constructed the IRQ table using getpir. Cloned the superio chip ITE it8718f to the it8720f. This all successfully builds and programs. So when I try and boot coreboot the machine does nothing and no info gets sent across the serial console. This is where I've ground to a halt, I would appreciate some advice on what can I do next? Thanks, Chris On Mon, 2012-06-18 at 09:11 -0600, Marc Jones wrote: > On Mon, Jun 18, 2012 at 2:41 AM, Christopher West > <chris.pn.west(a)gmail.com> wrote: > > All, > > > > I'm attempting to port my Asus M4A79XTD EVO again and I've come up > > against a dead stop, I think the problem is due to the motherboard > > having an AMD RD790 Northbridge. > > > > Would I be correct in assuming that this chip is not currently > > supported? > > > > If not is there anything that I can do to port it? > > > > Thanks, > > Chris W > > > > Hi Chris, > > I suspect that the 780 code would be very close to what you need for > the 790. I think that AMD has released the required documents. Make > sure that you are prepared to recover the flash for broken images > before you start. If you have specific questions, please post them or > join the irc channel. > > Regards, > Marc > > >

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ASUS M4A79XTD EVO - AMD RD790
by Christopher West 18 Jun '12

18 Jun '12

All, I'm attempting to port my Asus M4A79XTD EVO again and I've come up against a dead stop, I think the problem is due to the motherboard having an AMD RD790 Northbridge. Would I be correct in assuming that this chip is not currently supported? If not is there anything that I can do to port it? Thanks, Chris W

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coreboot June 2012