coreboot June 2012

coreboot@coreboot.org

41 participants
241 discussions

bios chip
by Julian Shulika 13 Jun '12

13 Jun '12

Hello,everyone! I'm tired to remove bios chip LPC from motherboard for flashing updated firmware coreboot all time and I broke bios socket twice. Is there any flash device I can use instead of bios chip and flash it from other host directly?

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Re: [coreboot] crossgcc: make[2]: iasl: command not found
by Paul Menzel 13 Jun '12

13 Jun '12

Am Dienstag, den 12.06.2012, 16:42 -0600 schrieb Marc Jones: > On Thu, Jun 7, 2012 at 5:01 PM, Paul Menzel wrote: > > with a current clone of coreboot > > > > $ git describe > > 4.0-2451-g2d1758b > > > > and > > > > $ make crossgcc > > Working around non-functional -combine > > Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011) > > > > Will skip GDB ... ok > > Downloading tar balls ... > > * gmp-5.0.5.tar.bz2 (downloading) > > * mpfr-3.1.0.tar.bz2 (downloading) > > * mpc-0.9.tar.gz (downloading) > > * libelf-0.8.13.tar.gz (downloading) > > * gcc-core-4.6.3.tar.bz2 (downloading) > > * binutils-2.22.tar.bz2 (downloading) > > * acpica-unix-20120420.tar.gz (downloading) > > > > Downloaded tar balls ... ok > > Unpacking and patching ... > > * gmp-5.0.5.tar.bz2 > > * mpfr-3.1.0.tar.bz2 > > * mpc-0.9.tar.gz > > * libelf-0.8.13.tar.gz > > * gcc-core-4.6.3.tar.bz2 > > * binutils-2.22.tar.bz2 > > * acpica-unix-20120420.tar.gz > > Unpacked and patched ... ok > > Building GMP 5.0.5 ... ok > > Building MPFR 3.1.0 ... ok > > Building MPC 0.9 ... ok > > Building libelf 0.8.13 ... ok > > Building binutils 2.22 ... ok > > Building GCC 4.6.3 ... ok > > Skipping Expat (Python scripting not enabled) > > Skipping Python (Python scripting not enabled) > > Skipping GDB (GDB support not enabled) > > Building IASL 20120420 ... ok > > Cleaning up... ok > > > > You can now run your i386-elf cross toolchain from /opt/src/coreboot/util/crossgcc/xgcc. > > $ make menuconfig # for ASRock E350M1 with SeaBIOS master and 4 MB image > > $ make > > > > I got the following error. > > > > […] > > Checking out SeaBIOS revision origin/master > > Switched to branch 'master' > > Deleted branch coreboot (was e66fb31). > > Branch coreboot set up to track remote branch master from > > origin. > > Switched to a new branch 'coreboot' > > CONFIG SeaBIOS origin/master > > Working around non-functional -combine > > Build default config > > # > > # configuration written > > to /opt/src/coreboot/build/seabios/.config > > # > > MAKE SeaBIOS origin/master > > Working around non-functional -combine > > Build Kconfig config file > > /opt/src/coreboot/build/seabios/.config:89:warning: override: > > reassigning to symbol COREBOOT > > /opt/src/coreboot/build/seabios/.config:90:warning: override: > > reassigning to symbol DEBUG_SERIAL > > /opt/src/coreboot/build/seabios/.config:95:warning: override: > > reassigning to symbol VGAHOOKS > > # > > # configuration written > > to /opt/src/coreboot/build/seabios/.config > > # > > Compiling DSDT > > make[2]: iasl: Kommando nicht gefunden > > make[2]: *** [src/acpi-dsdt.hex] Fehler 127 > > make[1]: *** [build] Fehler 2 > > make: *** [seabios] Fehler 2 > > > > The file `.xcompile` also contains the correct definition for `IASL`. > > > > IASL:=/opt/src/coreboot/util/crossgcc/xgcc/bin/iasl > > > > Running that file works too so no `noexec` flag or something else seems > > to be at fault. […] > I think that the stable version of seabios doesn't pick up the version > from coreboot. Check the git log for: > > commit 74f96123e7e37c219403b50e39dabc8e8c450948 > Author: Marc Jones <marc.jones(a)se-eng.com> > Date: Sun Apr 29 11:20:53 2012 -0600 Marc, thank you for your suggestion. With that commit the error is gone. Strangely as seen above I had chosen SeaBIOS master in Kconfig, but it looks like it was still at stable release at Git tag rel-1.7.0. commit a0263083cb4cda172832fbc916dc1417ee930574 Author: Kevin O'Connor <kevin(a)koconnor.net> Date: Sat Apr 14 20:22:18 2012 -0400 Misc compile fixes for gcc v3.4. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> > You can put a softlink to it into you path to get around this. Not necessary anymore thanks to your fix. Thanks, Paul

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Re: [coreboot] One ROM for multiple devices
by Peter Stuge 12 Jun '12

12 Jun '12

Steve Goodrich wrote: > I would like to see is some mechanism in both coreboot and SeaBIOS > that would allow a given ROM to be used for multiple devices. .. > Since this problem exists in both codebases, is it reasonable to > come up with a solution that will work in both codebases? I think this should happen in CBFS. The proposal is basically a special case symlink. It would be nice to have generic symlinks instead. Another special case solution yet still CBFS-centered could be to search for wildcard option ROMs at runtime. (V and D below are hexits, while x is a literal x.) 1. pciVVVV,DDDD.rom 2. pciVVVV,DDDx.rom 3. pciVVVV,DDxx.rom 4. pciVVVV,Dxxx.rom 5. pciVVVV,xxxx.rom 6. pciVVVx,xxxx.rom 7. pciVVxx,xxxx.rom 8. pciVxxx,xxxx.rom 9. pcixxxx,xxxx.rom 6 through 9 may be debatable, but I'm not neccessarily against them! //Peter

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Re: [coreboot] One ROM for multiple devices
by Kevin O'Connor 12 Jun '12

12 Jun '12

On Tue, Jun 12, 2012 at 05:06:11PM -0600, Steve Goodrich wrote: > Please be aware that this is cross-posted to both the SeaBIOS and coreboot > mailing lists. I know this is generally frowned upon, but I believe the > subject is valid for discussion in both forums. > > > I have a coreboot/SeaBIOS image containing an option ROM that works for > multiple graphics devices (seven or eight of them). These graphics devices > come from the same vendor but each device has its own (unique) PCI Device > ID. If I'm going to load the driver from SeaBIOS, I need to have a copy of > the option ROM file, each with the name of the target PCI device (e.g. > "pci1234,5678.rom"). Having seven or eight copies in the BIOS image file is > a waste of space. For the SeaBIOS case, is there any reason you can't simply place the rom in a cbfs file "vgaroms/myrom.rom"? -Kevin

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crossgcc: make[2]: iasl: command not found
by Paul Menzel 12 Jun '12

12 Jun '12

Dear coreboot folks, with a current clone of coreboot $ git describe 4.0-2451-g2d1758b and $ make crossgcc Working around non-functional -combine Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011) Will skip GDB ... ok Downloading tar balls ... * gmp-5.0.5.tar.bz2 (downloading) * mpfr-3.1.0.tar.bz2 (downloading) * mpc-0.9.tar.gz (downloading) * libelf-0.8.13.tar.gz (downloading) * gcc-core-4.6.3.tar.bz2 (downloading) * binutils-2.22.tar.bz2 (downloading) * acpica-unix-20120420.tar.gz (downloading) Downloaded tar balls ... ok Unpacking and patching ... * gmp-5.0.5.tar.bz2 * mpfr-3.1.0.tar.bz2 * mpc-0.9.tar.gz * libelf-0.8.13.tar.gz * gcc-core-4.6.3.tar.bz2 * binutils-2.22.tar.bz2 * acpica-unix-20120420.tar.gz Unpacked and patched ... ok Building GMP 5.0.5 ... ok Building MPFR 3.1.0 ... ok Building MPC 0.9 ... ok Building libelf 0.8.13 ... ok Building binutils 2.22 ... ok Building GCC 4.6.3 ... ok Skipping Expat (Python scripting not enabled) Skipping Python (Python scripting not enabled) Skipping GDB (GDB support not enabled) Building IASL 20120420 ... ok Cleaning up... ok You can now run your i386-elf cross toolchain from /opt/src/coreboot/util/crossgcc/xgcc. $ make menuconfig # for ASRock E350M1 with SeaBIOS master and 4 MB image $ make I got the following error. […] Checking out SeaBIOS revision origin/master Switched to branch 'master' Deleted branch coreboot (was e66fb31). Branch coreboot set up to track remote branch master from origin. Switched to a new branch 'coreboot' CONFIG SeaBIOS origin/master Working around non-functional -combine Build default config # # configuration written to /opt/src/coreboot/build/seabios/.config # MAKE SeaBIOS origin/master Working around non-functional -combine Build Kconfig config file /opt/src/coreboot/build/seabios/.config:89:warning: override: reassigning to symbol COREBOOT /opt/src/coreboot/build/seabios/.config:90:warning: override: reassigning to symbol DEBUG_SERIAL /opt/src/coreboot/build/seabios/.config:95:warning: override: reassigning to symbol VGAHOOKS # # configuration written to /opt/src/coreboot/build/seabios/.config # Compiling DSDT make[2]: iasl: Kommando nicht gefunden make[2]: *** [src/acpi-dsdt.hex] Fehler 127 make[1]: *** [build] Fehler 2 make: *** [seabios] Fehler 2 The file `.xcompile` also contains the correct definition for `IASL`. IASL:=/opt/src/coreboot/util/crossgcc/xgcc/bin/iasl Running that file works too so no `noexec` flag or something else seems to be at fault. Thanks, Paul

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Patch merged into coreboot/master: 1a649e8 Update SB800 CIMX FADT
by gerrit＠coreboot.org 12 Jun '12

12 Jun '12

the following patch was just integrated into master: commit 1a649e859f956360dbb01b1e5e10fc6ab99f4dbd Author: Martin Roth <martin(a)se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT - Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 & C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth <martin(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri May 25 22:40:06 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Jun 12 23:35:15 2012, giving +2 See http://review.coreboot.org/1055 for details. -gerrit

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Re: [coreboot] VGA Option ROM
by Kevin O'Connor 12 Jun '12

12 Jun '12

On Fri, Jun 08, 2012 at 08:15:30AM -0700, ron minnich wrote: > I wonder if we need another option :-( to configure the rom but not run it? Shouldn't coreboot do that when CONFIG_VGA_BRIDGE_SETUP is set, but CONFIG_VGA_ROM_RUN is not? -Kevin

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Patch merged into coreboot/master: bd563e6 udelay: add missing bus frequency
by gerrit＠coreboot.org 12 Jun '12

12 Jun '12

the following patch was just integrated into master: commit bd563e66681569f8b010f43a2289aa9d82537ec3 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 10 19:03:36 2012 +0200 udelay: add missing bus frequency commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Sun Jun 10 19:34:46 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jun 12 10:01:15 2012, giving +2 See http://review.coreboot.org/1099 for details. -gerrit

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Re: [coreboot] PCIe devices not enabled on amd/persimmon
by Bao, Zheng 12 Jun '12

12 Jun '12

Don't worry. If the hardware is ok, you can try my last patch which was sent to list and CC to you. I am pretty sure it can work. Joe From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Sharp Sent: Tuesday, June 12, 2012 2:58 AM To: She Kairui Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon I can now confirm this. Despite the hardware documentation for the board clearly showing the PCIe slot as being on the south bridge, it is not. I got a PCIe extension cable this morning that would actually fit, and the device plugged in shows to be a child of device 6.0, which is the third PCIe port on the northbridge/cpu. Sigh. This is a big bummer for me, as my employer has a design based on persimmon, except all the devices are on the southbridge instead of the northbridge, and we are struggling to get coreboot to see them and yet not hang. I know it can be done, because the BIOS does enable all the devices and boots, so it's just coreboot that isn't quite getting it right. Cheers, a On Sat, Jun 9, 2012 at 11:10 AM, She Kairui <shekairui(a)gmail.com<mailto:shekairui@gmail.com>> wrote: 2012/6/9, Andy Sharp <andywyse6(a)gmail.com<mailto:andywyse6@gmail.com>>: > It's a persimmon board ~:^) > > I'd be happy to test any patches. Meanwhile, I'm working on a patch to > properly enable the southbridge PCIe devices so they can be scanned. > Wolfgang (Wolfie?) is quite correct, the code that enables/deresets those > PCIe ports happens after the bus is scanned. When nothing shows up on the > bus scan, the code powers down those devices right after it [too late] > powers them up. Broken. > > This persimmon board is made by iBASE. and is a mini-ITX. It has a PCIe > slot and a mini-PCIe card socket on the sb800 PCIe ports. I have a persimmon Rev. D board, I found NONE of the PCIe devices is from SB800 GPP. You can double check it by booting from the factory BIOS. Thanks -- Kerry Sheh > I may have earlier said that it had a USB3 ctlr, that was my bad. So many twisty > passages.... > > I'll try out various combinations of the various patches you good folks > have been throwing my way, plus some of my own ideas and let the list know > what happens. > > Cheers, > > a > > > > On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave(a)se-eng.com<mailto:dave@se-eng.com>> wrote: > >> There shouldn't be any need to guess if it is a Persimmon. On a >> Persimmon board, next to the SATA connectors there should be >> printing that says "DB FT1". >> >> The Persimmon can also have up to two PCIe Ethernet chips on it. >> >> dave >> >> ----- Original Message ----- >> > From: "Zheng Bao" <Zheng.Bao(a)amd.com<mailto:Zheng.Bao@amd.com>> >> > To: "Andy Sharp" <andywyse6(a)gmail.com<mailto:andywyse6@gmail.com>> >> > Cc: "coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>" <coreboot(a)coreboot.org<mailto:coreboot@coreboot.org>> >> > Sent: Friday, June 8, 2012 5:37:58 AM >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon >> > >> > Hi, Andy, >> > The persimmon board I have got doesn't have any PCIe slot or onboard >> > PCIe device attached to SB800. And I am wondering if you actually >> > use a inagua board, which has the same APU & SB with persimmon and 2 >> > minipcie slots other than that. >> > >> > Let us assume you are testing on Inagua. >> > Here is my patch for the PCIe on SB800. There was a bug. It is just a >> > workaround patch, not ready for submitting. >> > >> > This patch can fix the sb800/pcie issue on Inagua. If you have your >> > work based on persimmon, please note the devicetree.cb should be >> > modify as Inagua. >> > The dev15func[0123] should be enabled and the gpp_configuration >> > should be 4. >> > >> > Joe >> > >> > diff --git a/src/southbridge/amd/cimx/sb800/late.c >> > b/src/southbridge/amd/cimx/sb800/late.c >> > index 0ce82b3..34cd937 100644 >> > --- a/src/southbridge/amd/cimx/sb800/late.c >> > +++ b/src/southbridge/amd/cimx/sb800/late.c >> > @@ -29,6 +29,7 @@ >> > #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ >> > #include "cfg.h" /* sb800 Cimx configuration */ >> > #include "chip.h" /* struct >> southbridge_amd_cimx_sb800_config */ >> > +#include "smbus.h" >> > #include "sb_cimx.h" /* AMD CIMX wrapper entries */ >> > >> > >> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = { >> > .set_resources = pci_dev_set_resources, >> > .enable_resources = pci_bus_enable_resources, >> > .init = pci_init, >> > + .enable = 0, >> > .scan_bus = pci_scan_bridge, >> > .reset_bus = pci_bus_reset, >> > .ops_pci = &lops_pci, >> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = { >> > .reset_bus = pci_bus_reset, >> > .ops_pci = &lops_pci, >> > }; >> > - >> > +#if 0 >> > /* 0:15:0 PCIe PortA */ >> > static const struct pci_driver PORTA_driver __pci_driver = { >> > .ops = &bridge_ops, >> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver >> > __pci_driver = { >> > .vendor = PCI_VENDOR_ID_ATI, >> > .device = PCI_DEVICE_ID_ATI_SB800_PCIED, >> > }; >> > - >> > +#endif >> > >> > /** >> > * South Bridge CIMx ramstage entry point wrapper. >> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev) >> > switch (dev->path.pci.devfn) { >> > case (0x11 << 3) | 0: /* 0:11.0 SATA */ >> > /* the first sb800 device */ >> > + abcfg_reg(0xc0, 0x1FF, 0x0F4); >> > sb800_cimx_config(sb_config); >> > >> > if (dev->enabled) { >> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev) >> > sb_config->GppLinkConfig = >> sb_chip->gpp_configuration; >> > } >> > break; >> > + case (0x15 << 3) | 1: >> > + case (0x15 << 3) | 2: >> > + case (0x15 << 3) | 3: >> > + //abcfg_reg(0xc0, 0xF0, 0x00); >> > + break; >> > >> > case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ >> > sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; >> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev) >> > /* call the CIMX entry at the last sb800 device, >> > * so make sure the mainboard devicetree is complete >> > */ >> > + abcfg_reg(0xc0, 0x100, 0x100); >> > #if CONFIG_HAVE_ACPI_RESUME >> > if (acpi_slp_type != 3) >> > sb_Before_Pci_Init(); >> > >> > >> > >> > >> > From: coreboot-bounces(a)coreboot.org<mailto:coreboot-bounces@coreboot.org> >> > [mailto:coreboot-bounces@coreboot.org<mailto:coreboot-bounces@coreboot.org>] On Behalf Of Andy Sharp >> > Sent: Friday, June 08, 2012 8:57 AM >> > To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon >> > >> > Hi Steve, >> > >> > Makes no [substantive] difference. All that does is cause 4 extra >> > lines to be added to the console output: >> > >> > . >> > . >> > . >> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling >> > it. >> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling >> > it. >> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling >> > it. >> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling >> > it. >> > . >> > . >> > . >> > >> > >> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich >> > <steve.goodrich(a)se-eng.com<mailto:steve.goodrich@se-eng.com>> wrote: >> > ARG.. Thanks, Outlook. :P >> > >> > Andy, >> > >> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon >> > folder. Mine shows: >> > >> > device pci 15.0 off end # PCIe PortA >> > device pci 15.1 off end # PCIe PortB >> > device pci 15.2 off end # PCIe PortC >> > device pci 15.3 off end # PCIe PortD >> > >> > I'm not 100% certain, but I suspect that changing these from "off" to >> > "on" will enable the devices. Try the change and see if the console >> > output starts reflecting the devices you're looking for. >> > >> > -- Steve G. >> > >> > >> > >> > From: coreboot-bounces(a)coreboot.org<mailto:coreboot-bounces@coreboot.org> >> > [mailto:coreboot-bounces@coreboot.org<mailto:coreboot-bounces@coreboot.org>] On Behalf Of Andy Sharp >> > Sent: Thursday, June 07, 2012 2:31 PM >> > To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> >> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon >> > >> > Howdy, >> > >> > I've got an AMD/persimmon board, with the agesa family 14 northbridge >> > on the CPU, and the SB800 southbridge. Both have 4 PCIe ports on >> > them, but coreboot isn't enabling or enumerating any of the PCIe >> > devices on the SB800. Does anyone have any ideas for me? The two >> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot. >> > >> > >> > Pasting the console output below for those interested: >> > >> > >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 >> > starting... >> > POST: 0x34 >> > BSP Family_Model: 00500f20 >> > cpu_init_detectedx = 00000000 >> > POST: 0x35 >> > agesawrapper_amdinitmmio passed. >> > POST: 0x37 >> > agesawrapper_amdinitreset passed. >> > POST: 0x39 >> > agesawrapper_amdinitearly POST: 0x34 >> > BSP Family_Model: 00500f20 >> > cpu_init_detectedx = 00000001 >> > POST: 0x35 >> > agesawrapper_amdinitmmio passed. >> > POST: 0x37 >> > agesawrapper_amdinitreset passed. >> > POST: 0x39 >> > agesawrapper_amdinitearly passed. >> > SLP_TYP type was 0 >> > POST: 0x40 >> > agesawrapper_amdinitpost >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > >> > EventLog: EventClass = 2, EventInfo = 8040100. >> > Param1 = a00a, Param2 = 0. >> > Param3 = 0, Param4 = 0. >> > SLP_TYP type was 0 >> > error level: 4 >> > POST: 0x42 >> > agesawrapper_amdinitenv SLP_TYP type was 0 >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 >> > SLP_TYP type was 0 >> > SLP_TYP type was 0 >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 >> > SLP_TYP type was 0 >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 >> > SLP_TYP type was 0 >> > SLP_TYP type was 0 >> > SLP_TYP type was 0 >> > passed. >> > POST: 0x43 >> > POST: 0x44 >> > POST: 0x50 >> > Loading image. >> > CBFS: Looking for 'fallback/coreboot_ram' >> > CBFS: found. >> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), >> > entry @ 0x200000 >> > Jumping to image. >> > POST: 0x80 >> > POST: 0x39 >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 >> > booting... >> > POST: 0x40 >> > Enumerating buses... >> > Show all devs...Before device enumeration. >> > Root Device: enabled 1 >> > APIC_CLUSTER: 0: enabled 1 >> > APIC: 00: enabled 1 >> > PCI_DOMAIN: 0000: enabled 1 >> > PCI: 00:00.0: enabled 1 >> > PCI: 00:01.0: enabled 1 >> > PCI: 00:01.1: enabled 1 >> > PCI: 00:04.0: enabled 1 >> > PCI: 00:05.0: enabled 0 >> > PCI: 00:06.0: enabled 0 >> > PCI: 00:07.0: enabled 0 >> > PCI: 00:08.0: enabled 0 >> > PCI: 00:11.0: enabled 1 >> > PCI: 00:12.0: enabled 1 >> > PCI: 00:12.1: enabled 1 >> > PCI: 00:12.2: enabled 1 >> > PCI: 00:13.0: enabled 1 >> > PCI: 00:13.1: enabled 1 >> > PCI: 00:13.2: enabled 1 >> > PCI: 00:14.0: enabled 1 >> > I2C: 00:50: enabled 1 >> > I2C: 00:51: enabled 1 >> > PCI: 00:14.1: enabled 1 >> > PCI: 00:14.2: enabled 1 >> > PCI: 00:14.3: enabled 1 >> > PNP: 004e.0: enabled 0 >> > PNP: 004e.3: enabled 0 >> > PNP: 004e.4: enabled 0 >> > PNP: 004e.5: enabled 1 >> > PNP: 004e.6: enabled 0 >> > PNP: 004e.a: enabled 0 >> > PNP: 004e.10: enabled 1 >> > PNP: 004e.11: enabled 0 >> > PCI: 00:14.4: enabled 1 >> > PCI: 00:14.5: enabled 1 >> > PCI: 00:15.0: enabled 0 >> > PCI: 00:15.1: enabled 0 >> > PCI: 00:15.2: enabled 0 >> > PCI: 00:15.3: enabled 0 >> > PCI: 00:16.0: enabled 0 >> > PCI: 00:16.2: enabled 0 >> > PCI: 00:18.0: enabled 1 >> > PCI: 00:18.1: enabled 1 >> > PCI: 00:18.2: enabled 1 >> > PCI: 00:18.3: enabled 1 >> > PCI: 00:18.4: enabled 1 >> > PCI: 00:18.5: enabled 1 >> > PCI: 00:18.6: enabled 1 >> > PCI: 00:18.7: enabled 1 >> > Compare with tree... >> > Root Device: enabled 1 >> > APIC_CLUSTER: 0: enabled 1 >> > APIC: 00: enabled 1 >> > PCI_DOMAIN: 0000: enabled 1 >> > PCI: 00:00.0: enabled 1 >> > PCI: 00:01.0: enabled 1 >> > PCI: 00:01.1: enabled 1 >> > PCI: 00:04.0: enabled 1 >> > PCI: 00:05.0: enabled 0 >> > PCI: 00:06.0: enabled 0 >> > PCI: 00:07.0: enabled 0 >> > PCI: 00:08.0: enabled 0 >> > PCI: 00:11.0: enabled 1 >> > PCI: 00:12.0: enabled 1 >> > PCI: 00:12.1: enabled 1 >> > PCI: 00:12.2: enabled 1 >> > PCI: 00:13.0: enabled 1 >> > PCI: 00:13.1: enabled 1 >> > PCI: 00:13.2: enabled 1 >> > PCI: 00:14.0: enabled 1 >> > I2C: 00:50: enabled 1 >> > I2C: 00:51: enabled 1 >> > PCI: 00:14.1: enabled 1 >> > PCI: 00:14.2: enabled 1 >> > PCI: 00:14.3: enabled 1 >> > PNP: 004e.0: enabled 0 >> > PNP: 004e.3: enabled 0 >> > PNP: 004e.4: enabled 0 >> > PNP: 004e.5: enabled 1 >> > PNP: 004e.6: enabled 0 >> > PNP: 004e.a: enabled 0 >> > PNP: 004e.10: enabled 1 >> > PNP: 004e.11: enabled 0 >> > PCI: 00:14.4: enabled 1 >> > PCI: 00:14.5: enabled 1 >> > PCI: 00:15.0: enabled 0 >> > PCI: 00:15.1: enabled 0 >> > PCI: 00:15.2: enabled 0 >> > PCI: 00:15.3: enabled 0 >> > PCI: 00:16.0: enabled 0 >> > PCI: 00:16.2: enabled 0 >> > PCI: 00:18.0: enabled 1 >> > PCI: 00:18.1: enabled 1 >> > PCI: 00:18.2: enabled 1 >> > PCI: 00:18.3: enabled 1 >> > PCI: 00:18.4: enabled 1 >> > PCI: 00:18.5: enabled 1 >> > PCI: 00:18.6: enabled 1 >> > PCI: 00:18.7: enabled 1 >> > Mainboard Persimmon Enable. >> > SLP_TYP type was 0 >> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000 >> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = >> > 0x00000000 >> > persimmon_enable: uma size 0x18000000, memory start 0x67000000 >> > scan_static_bus for Root Device >> > APIC_CLUSTER: 0 enabled >> > PCI_DOMAIN: 0000 enabled >> > APIC_CLUSTER: 0 scanning... >> > AP siblings=1 >> > CPU: APIC: 00 enabled >> > CPU: APIC: 01 enabled >> > PCI_DOMAIN: 0000 scanning... >> > PCI: pci_scan_bus for bus 00 >> > POST: 0x24 >> > PCI: 00:00.0 [1022/1510] ops >> > PCI: 00:00.0 [1022/1510] enabled >> > PCI: 00:01.0 [1002/9804] enabled >> > Capability: type 0x01 @ 0x50 >> > Capability: type 0x10 @ 0x58 >> > Capability: type 0x05 @ 0xa0 >> > Capability: type 0x0d @ 0xb0 >> > Capability: type 0x08 @ 0xb8 >> > Capability: type 0x01 @ 0x50 >> > Capability: type 0x10 @ 0x58 >> > PCI: 00:04.0 subordinate bus PCI Express >> > PCI: 00:04.0 [1022/1512] enabled >> > sb800_enable() SLP_TYP type was 0 >> > PCI: 00:11.0 [1002/4393] ops >> > PCI: 00:11.0 [1002/4393] enabled >> > sb800_enable() PCI: 00:12.0 [1002/4397] ops >> > PCI: 00:12.0 [1002/4397] enabled >> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling >> > it. >> > sb800_enable() PCI: 00:12.2 [1002/4396] ops >> > PCI: 00:12.2 [1002/4396] enabled >> > sb800_enable() PCI: 00:13.0 [1002/4397] ops >> > PCI: 00:13.0 [1002/4397] enabled >> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling >> > it. >> > sb800_enable() PCI: 00:13.2 [1002/4396] ops >> > PCI: 00:13.2 [1002/4396] enabled >> > sb800_enable() sm_init(). >> > IOAPIC: Clearing IOAPIC at 0xfec00000 >> > IOAPIC: 23 interrupts >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 >> > IOAPIC: Initializing IOAPIC at 0xfec00000 >> > IOAPIC: Bootstrap Processor Local APIC = 0x00 >> > IOAPIC: ID = 0x02 >> > IOAPIC: 23 interrupts >> > IOAPIC: Enabling interrupts on FSB >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 >> > PCI: 00:14.0 [1002/4385] enabled >> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling >> > it. >> > sb800_enable() hda enabled >> > PCI: 00:14.2 [1002/4383] ops >> > PCI: 00:14.2 [1002/4383] enabled >> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops >> > PCI: 00:14.3 [1002/439d] enabled >> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops >> > PCI: 00:14.4 [1002/4384] enabled >> > sb800_enable() PCI: 00:14.5 [1002/4399] ops >> > PCI: 00:14.5 [1002/4399] enabled >> > sb800_enable() sb800_enable() sb800_enable() sb800_enable() >> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled >> > PCI: 00:18.1 [1022/1701] enabled >> > PCI: 00:18.2 [1022/1702] enabled >> > PCI: 00:18.3 [1022/1703] enabled >> > PCI: 00:18.4 [1022/1704] enabled >> > PCI: 00:18.5 [1022/1718] enabled >> > PCI: 00:18.6 [1022/1716] enabled >> > PCI: 00:18.7 [1022/1719] enabled >> > POST: 0x25 >> > PCI: Left over static devices: >> > PCI: 00:01.1 >> > PCI: Check your devicetree.cb. >> > do_pci_scan_bridge for PCI: 00:04.0 >> > PCI: pci_scan_bus for bus 01 >> > POST: 0x24 >> > PCI: 01:00.0 [10ec/8168] enabled >> > POST: 0x25 >> > PCI: pci_scan_bus returning with max=001 >> > POST: 0x55 >> > >> > -- >> > coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> >> > http://www.coreboot.org/mailman/listinfo/coreboot >> > >> > >> > -- >> > coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> >> > http://www.coreboot.org/mailman/listinfo/coreboot >> >

1 0

Re: [coreboot] PCIe devices not enabled on amd/persimmon
by Andy Sharp 11 Jun '12

11 Jun '12

I can now confirm this. Despite the hardware documentation for the board clearly showing the PCIe slot as being on the south bridge, it is not. I got a PCIe extension cable this morning that would actually fit, and the device plugged in shows to be a child of device 6.0, which is the third PCIe port on the northbridge/cpu. Sigh. This is a big bummer for me, as my employer has a design based on persimmon, except all the devices are on the southbridge instead of the northbridge, and we are struggling to get coreboot to see them and yet not hang. I know it can be done, because the BIOS does enable all the devices and boots, so it's just coreboot that isn't quite getting it right. Cheers, a On Sat, Jun 9, 2012 at 11:10 AM, She Kairui <shekairui(a)gmail.com> wrote: > 2012/6/9, Andy Sharp <andywyse6(a)gmail.com>: > > It's a persimmon board ~:^) > > > > I'd be happy to test any patches. Meanwhile, I'm working on a patch to > > properly enable the southbridge PCIe devices so they can be scanned. > > Wolfgang (Wolfie?) is quite correct, the code that enables/deresets > those > > PCIe ports happens after the bus is scanned. When nothing shows up on > the > > bus scan, the code powers down those devices right after it [too late] > > powers them up. Broken. > > > > This persimmon board is made by iBASE. and is a mini-ITX. It has a PCIe > > slot and a mini-PCIe card socket on the sb800 PCIe ports. > I have a persimmon Rev. D board, I found NONE of the PCIe devices is > from SB800 GPP. > You can double check it by booting from the factory BIOS. > Thanks > > -- > Kerry Sheh > > I may have earlier said that it had a USB3 ctlr, that was my bad. So > many twisty > > passages.... > > > > I'll try out various combinations of the various patches you good folks > > have been throwing my way, plus some of my own ideas and let the list > know > > what happens. > > > > Cheers, > > > > a > > > > > > > > On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave(a)se-eng.com> wrote: > > > >> There shouldn't be any need to guess if it is a Persimmon. On a > >> Persimmon board, next to the SATA connectors there should be > >> printing that says "DB FT1". > >> > >> The Persimmon can also have up to two PCIe Ethernet chips on it. > >> > >> dave > >> > >> ----- Original Message ----- > >> > From: "Zheng Bao" <Zheng.Bao(a)amd.com> > >> > To: "Andy Sharp" <andywyse6(a)gmail.com> > >> > Cc: "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> > >> > Sent: Friday, June 8, 2012 5:37:58 AM > >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon > >> > > >> > Hi, Andy, > >> > The persimmon board I have got doesn't have any PCIe slot or onboard > >> > PCIe device attached to SB800. And I am wondering if you actually > >> > use a inagua board, which has the same APU & SB with persimmon and 2 > >> > minipcie slots other than that. > >> > > >> > Let us assume you are testing on Inagua. > >> > Here is my patch for the PCIe on SB800. There was a bug. It is just a > >> > workaround patch, not ready for submitting. > >> > > >> > This patch can fix the sb800/pcie issue on Inagua. If you have your > >> > work based on persimmon, please note the devicetree.cb should be > >> > modify as Inagua. > >> > The dev15func[0123] should be enabled and the gpp_configuration > >> > should be 4. > >> > > >> > Joe > >> > > >> > diff --git a/src/southbridge/amd/cimx/sb800/late.c > >> > b/src/southbridge/amd/cimx/sb800/late.c > >> > index 0ce82b3..34cd937 100644 > >> > --- a/src/southbridge/amd/cimx/sb800/late.c > >> > +++ b/src/southbridge/amd/cimx/sb800/late.c > >> > @@ -29,6 +29,7 @@ > >> > #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ > >> > #include "cfg.h" /* sb800 Cimx configuration */ > >> > #include "chip.h" /* struct > >> southbridge_amd_cimx_sb800_config */ > >> > +#include "smbus.h" > >> > #include "sb_cimx.h" /* AMD CIMX wrapper entries */ > >> > > >> > > >> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = { > >> > .set_resources = pci_dev_set_resources, > >> > .enable_resources = pci_bus_enable_resources, > >> > .init = pci_init, > >> > + .enable = 0, > >> > .scan_bus = pci_scan_bridge, > >> > .reset_bus = pci_bus_reset, > >> > .ops_pci = &lops_pci, > >> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = { > >> > .reset_bus = pci_bus_reset, > >> > .ops_pci = &lops_pci, > >> > }; > >> > - > >> > +#if 0 > >> > /* 0:15:0 PCIe PortA */ > >> > static const struct pci_driver PORTA_driver __pci_driver = { > >> > .ops = &bridge_ops, > >> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver > >> > __pci_driver = { > >> > .vendor = PCI_VENDOR_ID_ATI, > >> > .device = PCI_DEVICE_ID_ATI_SB800_PCIED, > >> > }; > >> > - > >> > +#endif > >> > > >> > /** > >> > * South Bridge CIMx ramstage entry point wrapper. > >> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev) > >> > switch (dev->path.pci.devfn) { > >> > case (0x11 << 3) | 0: /* 0:11.0 SATA */ > >> > /* the first sb800 device */ > >> > + abcfg_reg(0xc0, 0x1FF, 0x0F4); > >> > sb800_cimx_config(sb_config); > >> > > >> > if (dev->enabled) { > >> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev) > >> > sb_config->GppLinkConfig = > >> sb_chip->gpp_configuration; > >> > } > >> > break; > >> > + case (0x15 << 3) | 1: > >> > + case (0x15 << 3) | 2: > >> > + case (0x15 << 3) | 3: > >> > + //abcfg_reg(0xc0, 0xF0, 0x00); > >> > + break; > >> > > >> > case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ > >> > sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; > >> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev) > >> > /* call the CIMX entry at the last sb800 device, > >> > * so make sure the mainboard devicetree is complete > >> > */ > >> > + abcfg_reg(0xc0, 0x100, 0x100); > >> > #if CONFIG_HAVE_ACPI_RESUME > >> > if (acpi_slp_type != 3) > >> > sb_Before_Pci_Init(); > >> > > >> > > >> > > >> > > >> > From: coreboot-bounces(a)coreboot.org > >> > [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Sharp > >> > Sent: Friday, June 08, 2012 8:57 AM > >> > To: coreboot(a)coreboot.org > >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon > >> > > >> > Hi Steve, > >> > > >> > Makes no [substantive] difference. All that does is cause 4 extra > >> > lines to be added to the console output: > >> > > >> > . > >> > . > >> > . > >> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling > >> > it. > >> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling > >> > it. > >> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling > >> > it. > >> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling > >> > it. > >> > . > >> > . > >> > . > >> > > >> > > >> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich > >> > <steve.goodrich(a)se-eng.com> wrote: > >> > ARG.. Thanks, Outlook. :P > >> > > >> > Andy, > >> > > >> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon > >> > folder. Mine shows: > >> > > >> > device pci 15.0 off end # PCIe PortA > >> > device pci 15.1 off end # PCIe PortB > >> > device pci 15.2 off end # PCIe PortC > >> > device pci 15.3 off end # PCIe PortD > >> > > >> > I'm not 100% certain, but I suspect that changing these from "off" to > >> > "on" will enable the devices. Try the change and see if the console > >> > output starts reflecting the devices you're looking for. > >> > > >> > -- Steve G. > >> > > >> > > >> > > >> > From: coreboot-bounces(a)coreboot.org > >> > [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Sharp > >> > Sent: Thursday, June 07, 2012 2:31 PM > >> > To: coreboot(a)coreboot.org > >> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon > >> > > >> > Howdy, > >> > > >> > I've got an AMD/persimmon board, with the agesa family 14 northbridge > >> > on the CPU, and the SB800 southbridge. Both have 4 PCIe ports on > >> > them, but coreboot isn't enabling or enumerating any of the PCIe > >> > devices on the SB800. Does anyone have any ideas for me? The two > >> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot. > >> > > >> > > >> > Pasting the console output below for those interested: > >> > > >> > > >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 > >> > starting... > >> > POST: 0x34 > >> > BSP Family_Model: 00500f20 > >> > cpu_init_detectedx = 00000000 > >> > POST: 0x35 > >> > agesawrapper_amdinitmmio passed. > >> > POST: 0x37 > >> > agesawrapper_amdinitreset passed. > >> > POST: 0x39 > >> > agesawrapper_amdinitearly POST: 0x34 > >> > BSP Family_Model: 00500f20 > >> > cpu_init_detectedx = 00000001 > >> > POST: 0x35 > >> > agesawrapper_amdinitmmio passed. > >> > POST: 0x37 > >> > agesawrapper_amdinitreset passed. > >> > POST: 0x39 > >> > agesawrapper_amdinitearly passed. > >> > SLP_TYP type was 0 > >> > POST: 0x40 > >> > agesawrapper_amdinitpost > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > > >> > EventLog: EventClass = 2, EventInfo = 8040100. > >> > Param1 = a00a, Param2 = 0. > >> > Param3 = 0, Param4 = 0. > >> > SLP_TYP type was 0 > >> > error level: 4 > >> > POST: 0x42 > >> > agesawrapper_amdinitenv SLP_TYP type was 0 > >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 > >> > SLP_TYP type was 0 > >> > SLP_TYP type was 0 > >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 > >> > SLP_TYP type was 0 > >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000 > >> > SLP_TYP type was 0 > >> > SLP_TYP type was 0 > >> > SLP_TYP type was 0 > >> > passed. > >> > POST: 0x43 > >> > POST: 0x44 > >> > POST: 0x50 > >> > Loading image. > >> > CBFS: Looking for 'fallback/coreboot_ram' > >> > CBFS: found. > >> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), > >> > entry @ 0x200000 > >> > Jumping to image. > >> > POST: 0x80 > >> > POST: 0x39 > >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 > >> > booting... > >> > POST: 0x40 > >> > Enumerating buses... > >> > Show all devs...Before device enumeration. > >> > Root Device: enabled 1 > >> > APIC_CLUSTER: 0: enabled 1 > >> > APIC: 00: enabled 1 > >> > PCI_DOMAIN: 0000: enabled 1 > >> > PCI: 00:00.0: enabled 1 > >> > PCI: 00:01.0: enabled 1 > >> > PCI: 00:01.1: enabled 1 > >> > PCI: 00:04.0: enabled 1 > >> > PCI: 00:05.0: enabled 0 > >> > PCI: 00:06.0: enabled 0 > >> > PCI: 00:07.0: enabled 0 > >> > PCI: 00:08.0: enabled 0 > >> > PCI: 00:11.0: enabled 1 > >> > PCI: 00:12.0: enabled 1 > >> > PCI: 00:12.1: enabled 1 > >> > PCI: 00:12.2: enabled 1 > >> > PCI: 00:13.0: enabled 1 > >> > PCI: 00:13.1: enabled 1 > >> > PCI: 00:13.2: enabled 1 > >> > PCI: 00:14.0: enabled 1 > >> > I2C: 00:50: enabled 1 > >> > I2C: 00:51: enabled 1 > >> > PCI: 00:14.1: enabled 1 > >> > PCI: 00:14.2: enabled 1 > >> > PCI: 00:14.3: enabled 1 > >> > PNP: 004e.0: enabled 0 > >> > PNP: 004e.3: enabled 0 > >> > PNP: 004e.4: enabled 0 > >> > PNP: 004e.5: enabled 1 > >> > PNP: 004e.6: enabled 0 > >> > PNP: 004e.a: enabled 0 > >> > PNP: 004e.10: enabled 1 > >> > PNP: 004e.11: enabled 0 > >> > PCI: 00:14.4: enabled 1 > >> > PCI: 00:14.5: enabled 1 > >> > PCI: 00:15.0: enabled 0 > >> > PCI: 00:15.1: enabled 0 > >> > PCI: 00:15.2: enabled 0 > >> > PCI: 00:15.3: enabled 0 > >> > PCI: 00:16.0: enabled 0 > >> > PCI: 00:16.2: enabled 0 > >> > PCI: 00:18.0: enabled 1 > >> > PCI: 00:18.1: enabled 1 > >> > PCI: 00:18.2: enabled 1 > >> > PCI: 00:18.3: enabled 1 > >> > PCI: 00:18.4: enabled 1 > >> > PCI: 00:18.5: enabled 1 > >> > PCI: 00:18.6: enabled 1 > >> > PCI: 00:18.7: enabled 1 > >> > Compare with tree... > >> > Root Device: enabled 1 > >> > APIC_CLUSTER: 0: enabled 1 > >> > APIC: 00: enabled 1 > >> > PCI_DOMAIN: 0000: enabled 1 > >> > PCI: 00:00.0: enabled 1 > >> > PCI: 00:01.0: enabled 1 > >> > PCI: 00:01.1: enabled 1 > >> > PCI: 00:04.0: enabled 1 > >> > PCI: 00:05.0: enabled 0 > >> > PCI: 00:06.0: enabled 0 > >> > PCI: 00:07.0: enabled 0 > >> > PCI: 00:08.0: enabled 0 > >> > PCI: 00:11.0: enabled 1 > >> > PCI: 00:12.0: enabled 1 > >> > PCI: 00:12.1: enabled 1 > >> > PCI: 00:12.2: enabled 1 > >> > PCI: 00:13.0: enabled 1 > >> > PCI: 00:13.1: enabled 1 > >> > PCI: 00:13.2: enabled 1 > >> > PCI: 00:14.0: enabled 1 > >> > I2C: 00:50: enabled 1 > >> > I2C: 00:51: enabled 1 > >> > PCI: 00:14.1: enabled 1 > >> > PCI: 00:14.2: enabled 1 > >> > PCI: 00:14.3: enabled 1 > >> > PNP: 004e.0: enabled 0 > >> > PNP: 004e.3: enabled 0 > >> > PNP: 004e.4: enabled 0 > >> > PNP: 004e.5: enabled 1 > >> > PNP: 004e.6: enabled 0 > >> > PNP: 004e.a: enabled 0 > >> > PNP: 004e.10: enabled 1 > >> > PNP: 004e.11: enabled 0 > >> > PCI: 00:14.4: enabled 1 > >> > PCI: 00:14.5: enabled 1 > >> > PCI: 00:15.0: enabled 0 > >> > PCI: 00:15.1: enabled 0 > >> > PCI: 00:15.2: enabled 0 > >> > PCI: 00:15.3: enabled 0 > >> > PCI: 00:16.0: enabled 0 > >> > PCI: 00:16.2: enabled 0 > >> > PCI: 00:18.0: enabled 1 > >> > PCI: 00:18.1: enabled 1 > >> > PCI: 00:18.2: enabled 1 > >> > PCI: 00:18.3: enabled 1 > >> > PCI: 00:18.4: enabled 1 > >> > PCI: 00:18.5: enabled 1 > >> > PCI: 00:18.6: enabled 1 > >> > PCI: 00:18.7: enabled 1 > >> > Mainboard Persimmon Enable. > >> > SLP_TYP type was 0 > >> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000 > >> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = > >> > 0x00000000 > >> > persimmon_enable: uma size 0x18000000, memory start 0x67000000 > >> > scan_static_bus for Root Device > >> > APIC_CLUSTER: 0 enabled > >> > PCI_DOMAIN: 0000 enabled > >> > APIC_CLUSTER: 0 scanning... > >> > AP siblings=1 > >> > CPU: APIC: 00 enabled > >> > CPU: APIC: 01 enabled > >> > PCI_DOMAIN: 0000 scanning... > >> > PCI: pci_scan_bus for bus 00 > >> > POST: 0x24 > >> > PCI: 00:00.0 [1022/1510] ops > >> > PCI: 00:00.0 [1022/1510] enabled > >> > PCI: 00:01.0 [1002/9804] enabled > >> > Capability: type 0x01 @ 0x50 > >> > Capability: type 0x10 @ 0x58 > >> > Capability: type 0x05 @ 0xa0 > >> > Capability: type 0x0d @ 0xb0 > >> > Capability: type 0x08 @ 0xb8 > >> > Capability: type 0x01 @ 0x50 > >> > Capability: type 0x10 @ 0x58 > >> > PCI: 00:04.0 subordinate bus PCI Express > >> > PCI: 00:04.0 [1022/1512] enabled > >> > sb800_enable() SLP_TYP type was 0 > >> > PCI: 00:11.0 [1002/4393] ops > >> > PCI: 00:11.0 [1002/4393] enabled > >> > sb800_enable() PCI: 00:12.0 [1002/4397] ops > >> > PCI: 00:12.0 [1002/4397] enabled > >> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling > >> > it. > >> > sb800_enable() PCI: 00:12.2 [1002/4396] ops > >> > PCI: 00:12.2 [1002/4396] enabled > >> > sb800_enable() PCI: 00:13.0 [1002/4397] ops > >> > PCI: 00:13.0 [1002/4397] enabled > >> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling > >> > it. > >> > sb800_enable() PCI: 00:13.2 [1002/4396] ops > >> > PCI: 00:13.2 [1002/4396] enabled > >> > sb800_enable() sm_init(). > >> > IOAPIC: Clearing IOAPIC at 0xfec00000 > >> > IOAPIC: 23 interrupts > >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 > >> > IOAPIC: Initializing IOAPIC at 0xfec00000 > >> > IOAPIC: Bootstrap Processor Local APIC = 0x00 > >> > IOAPIC: ID = 0x02 > >> > IOAPIC: 23 interrupts > >> > IOAPIC: Enabling interrupts on FSB > >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 > >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 > >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 > >> > PCI: 00:14.0 [1002/4385] enabled > >> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling > >> > it. > >> > sb800_enable() hda enabled > >> > PCI: 00:14.2 [1002/4383] ops > >> > PCI: 00:14.2 [1002/4383] enabled > >> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops > >> > PCI: 00:14.3 [1002/439d] enabled > >> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops > >> > PCI: 00:14.4 [1002/4384] enabled > >> > sb800_enable() PCI: 00:14.5 [1002/4399] ops > >> > PCI: 00:14.5 [1002/4399] enabled > >> > sb800_enable() sb800_enable() sb800_enable() sb800_enable() > >> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled > >> > PCI: 00:18.1 [1022/1701] enabled > >> > PCI: 00:18.2 [1022/1702] enabled > >> > PCI: 00:18.3 [1022/1703] enabled > >> > PCI: 00:18.4 [1022/1704] enabled > >> > PCI: 00:18.5 [1022/1718] enabled > >> > PCI: 00:18.6 [1022/1716] enabled > >> > PCI: 00:18.7 [1022/1719] enabled > >> > POST: 0x25 > >> > PCI: Left over static devices: > >> > PCI: 00:01.1 > >> > PCI: Check your devicetree.cb. > >> > do_pci_scan_bridge for PCI: 00:04.0 > >> > PCI: pci_scan_bus for bus 01 > >> > POST: 0x24 > >> > PCI: 01:00.0 [10ec/8168] enabled > >> > POST: 0x25 > >> > PCI: pci_scan_bus returning with max=001 > >> > POST: 0x55 > >> > > >> > -- > >> > coreboot mailing list: coreboot(a)coreboot.org > >> > http://www.coreboot.org/mailman/listinfo/coreboot > >> > > >> > > >> > -- > >> > coreboot mailing list: coreboot(a)coreboot.org > >> > http://www.coreboot.org/mailman/listinfo/coreboot > >> > > >

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coreboot June 2012