coreboot June 2012

coreboot@coreboot.org

41 participants
241 discussions

Start a nNew thread

Trac reminder: list of new ticket(s)
by coreboot tracker 18 Jun '12

18 Jun '12

1 0

New patch to review for coreboot: 8b6008f i5000: enforce hard reset
by Sven Schnelle 18 Jun '12

18 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1103 -gerrit commit 8b6008f20e6a1aaed4512e4a506b7c49a945ba0b Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 17 14:23:35 2012 +0200 i5000: enforce hard reset Not doing a hard reset leaves the BOFL0 register cleared, which prevents the BSP selection from working. To make sure we start with known values, use the SPAD0 register for soft reset detection. If there's a value other than 0, do a hard reset. Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/halt_second_bsp.S | 31 ++++++++++++++++++++++++- 1 files changed, 30 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index a1a1b15..2dc533a 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -2,6 +2,26 @@ movl %eax, %ebp + /* check if SPAD0 is cleared. If yes, it means this was a hard reset */ + movl $0x800080d0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + je no_reset + + /* perform hard reset */ + movw $0xcf9, %dx + movw $0x06, %ax + outw %ax, %dx + +loop0: hlt + jmp loop + +no_reset: + /* Read the semaphore register of i5000 (BOFL0). If it returns zero, it means there was already another read by another CPU */ @@ -25,5 +45,14 @@ loop: hlt jmp loop -1: /* Restore BIST */ +1: /* set magic value for soft reset detection */ + movl $0x800080d0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + movl $0x12345678, %eax + outl %eax, %dx + + /* Restore BIST */ mov %ebp, %eax

3 2

Patch merged into coreboot/master: 8b6008f i5000: enforce hard reset
by gerrit＠coreboot.org 18 Jun '12

18 Jun '12

the following patch was just integrated into master: commit 8b6008f20e6a1aaed4512e4a506b7c49a945ba0b Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 17 14:23:35 2012 +0200 i5000: enforce hard reset Not doing a hard reset leaves the BOFL0 register cleared, which prevents the BSP selection from working. To make sure we start with known values, use the SPAD0 register for soft reset detection. If there's a value other than 0, do a hard reset. Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Sun Jun 17 14:59:10 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Mon Jun 18 09:03:35 2012, giving +2 See http://review.coreboot.org/1103 for details. -gerrit

1 0

Patch merged into coreboot/master: a71f045 llshell: fix build without romcc
by gerrit＠coreboot.org 14 Jun '12

14 Jun '12

the following patch was just integrated into master: commit a71f045e44f42a09c318bb46086616b329ffacc8 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Jun 14 14:19:09 2012 +0200 llshell: fix build without romcc Without that fix we have: LINK cbfs/fallback/romstage_null.debug build/generated/crt0.romstage.o: In function `ramtest': romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt' collect2: ld returned 1 exit status make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1 On the M4A785T-M which doesn't have CONFIG_ROMCC. Change-Id: I49eded1d18e996afe9441b85dae04ae30c760dd6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Build-Tested: build bot (Jenkins) at Thu Jun 14 16:20:50 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Thu Jun 14 21:21:05 2012, giving +2 See http://review.coreboot.org/1101 for details. -gerrit

1 0

New patch to review for coreboot: 5a0f3f4 M4A785-M and M4A785T-M: Add support for llshell
by Denis Carikli 14 Jun '12

14 Jun '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1102 -gerrit commit 5a0f3f476fd4780495bfe8ba04fb96bf4d646795 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Jun 14 14:21:09 2012 +0200 M4A785-M and M4A785T-M: Add support for llshell Change-Id: Ia9ee1bcd363896a8618407149fafdd354e6c0a88 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785-m/romstage.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f0be2f7..338edf4 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -50,6 +50,7 @@ #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#include "arch/llshell.h" static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -221,6 +222,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); + +#if CONFIG_LLSHELL + llshell(); +#endif + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }

1 0

New patch to review for coreboot: a71f045 llshell: fix build without romcc
by Denis Carikli 14 Jun '12

14 Jun '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1101 -gerrit commit a71f045e44f42a09c318bb46086616b329ffacc8 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Jun 14 14:19:09 2012 +0200 llshell: fix build without romcc Without that fix we have: LINK cbfs/fallback/romstage_null.debug build/generated/crt0.romstage.o: In function `ramtest': romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt' collect2: ld returned 1 exit status make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1 On the M4A785T-M which doesn't have CONFIG_ROMCC. Change-Id: I49eded1d18e996afe9441b85dae04ae30c760dd6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/llshell/ramtest.inc | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/llshell/ramtest.inc b/src/arch/x86/llshell/ramtest.inc index c02cf45..49abd4a 100644 --- a/src/arch/x86/llshell/ramtest.inc +++ b/src/arch/x86/llshell/ramtest.inc @@ -112,8 +112,10 @@ ramtest: jmp 3b 5: CONSOLE_INFO_TX_STRING($rt_toomany) +#if CONFIG_ROMCC post_code(0xf1) jmp .Lhlt +#endif 6: CONSOLE_INFO_TX_STRING($rt_done)

1 0

P965 / ICH8R coreboot support
by Mihai Marchidann 14 Jun '12

14 Jun '12

Hello, I would like to know if it is feasible to seek coreboot support for the LGA775 socket and motherboards based on the P965 and ICH8R chipsets and controllers. These motherboards, such as ASUS P5B-DE and P5B Deluxe Wifi-AP, are still offered for sale and their top processors are still competitive despite a few Intel CPU refreshes in the last 3-4 years. I am wondering if the following datasheets and specifications would suffice to start working on this port. http://ark.intel.com/products/chipsets/22754/config/26953 http://ark.intel.com/products/27687/Intel-82801HR-IO-Controller http://www.intel.com/content/www/us/en/io/intel-io-controller-hub-8-datashe… http://ark.intel.com/products/27730/Intel-82P965-Memory-Controller http://www.intel.com/Assets/PDF/datasheet/313053.pdf http://ark.intel.com/products/29765/Intel-Core2-Quad-Processor-Q6600-%288M-… http://www.intel.com/design/processor/datashts/315592.htm http://www.intel.com/design/processor/specupdt/315593.htm http://download.intel.com/design/processor/datashts/31559205.pdf http://www.intel.com/Assets/PDF/designguide/302666.pdf http://download.intel.com/design/processor/designex/315594.pdf http://www.intel.com/Assets/en_US/PDF/designguide/314917.pdf I would appreciate any advice and help. Thank you. Best regards, Mihai Marchidann

1 0

One ROM for multiple devices
by Steve Goodrich 13 Jun '12

13 Jun '12

Please be aware that this is cross-posted to both the SeaBIOS and coreboot mailing lists. I know this is generally frowned upon, but I believe the subject is valid for discussion in both forums. I have a coreboot/SeaBIOS image containing an option ROM that works for multiple graphics devices (seven or eight of them). These graphics devices come from the same vendor but each device has its own (unique) PCI Device ID. If I'm going to load the driver from SeaBIOS, I need to have a copy of the option ROM file, each with the name of the target PCI device (e.g. "pci1234,5678.rom"). Having seven or eight copies in the BIOS image file is a waste of space. Stefan R. submitted a solution to coreboot to enable mapping one ROM's vendor/device ID to another and this solution has worked well for coreboot-centric uses. Unfortunately, this does not address the problem in SeaBIOS. I have started working on a solution that extends what Stefan has done, but moves the data into a single "translate" file in CBFS. This file contains simple data to allow coreboot and/or SeaBIOS to take a PCI device's vendor/device info and retrieve alternate vendor/device values. Since both coreboot and SeaBIOS understand CBFS, the basic translation code would be identical. The data file consists of sets of four 16-bit binary values: u16 vendor1, device1; // translate FROM this PCI v/d u16 vendor2, device2; // translate TO this PCI v/d If you have a single ROM which could support three devices, you would have two sets of data: 0x1234, 0x0001, 0x1234, 0x0002 0x1234, 0x0001, 0x1234, 0x0003 This data would let the ROM for vendor 0x1234, device 0x0001 support devices 0x0002 and 0x0003. NOTE: there is no data for device 0x0001, since it would be handled without translation. The code would work something like this: sprintf(name, "pci%04x,%04x.rom", pci->vendor, pci->device); rom = cbfs_findfile(name); // load the file if (!rom) { // ROM not found... try translation ven = pci->vendor; dev = pci->device; if (translate_findFirst(&ven, &dev)) { do { sprintf(name, "pci%04x,%04x.rom", ven, dev); rom = cbfs_findfile(name); // load the file while ((rom == null) && translate_findNext(&ven, &dev)); } } I'm not tied to the findFirst/findNext mechanism nor to the specific format of the data. What I would like to see is some mechanism in both coreboot and SeaBIOS that would allow a given ROM to be used for multiple devices. In coreboot this would affect the map_oprom_vendev() function. In SeaBIOS this would affect both lookup_hardcode() and map_pcirom(). Since this problem exists in both codebases, is it reasonable to come up with a solution that will work in both codebases? Thoughts? -- Steve G.

3 2

P965 / ICH8R coreboot support
by Mihai Marchidann 13 Jun '12

13 Jun '12

1 0

crossgcc: `make clean` fails for SeaBIOS because IASL definition is not passed
by Paul Menzel 13 Jun '12

13 Jun '12

Dear coreboot folks, running `make clean` I get the following behavior (SeaBIOS 2062f2ba). coreboot$ make clean The SeaBIOS project requires the 'iasl' package be installed. Many Linux distributions have this package. Try: sudo yum install iasl Or: sudo apt-get install iasl Please install iasl and retry. Makefile:87: *** "Please upgrade the build environment". Schluss. coreboot$ cd build/seabios/ coreboot/build/seabios$ make clean The SeaBIOS project requires the 'iasl' package be installed. Many Linux distributions have this package. Try: sudo yum install iasl Or: sudo apt-get install iasl Please install iasl and retry. Makefile:87: *** "Please upgrade the build environment". Schluss. $ more Makefile […] IASL:=iasl # Default targets -include $(KCONFIG_CONFIG) target-y = $(OUT) $(OUT)bios.bin target-$(CONFIG_BUILD_VGABIOS) += $(OUT)vgabios.bin all: $(target-y) # Make definitions .PHONY : all clean distclean FORCE vpath %.c src vgasrc vpath %.S src vgasrc ################ Common build rules # Verify the build environment works. TESTGCC:=$(shell CC="$(CC)" LD="$(LD)" IASL="$(IASL)" tools/test-build.sh) ifeq "$(TESTGCC)" "-1" $(error "Please upgrade the build environment") endif So is there a way that the environment variables from coreboot are passed to SeaBIOS? `make` with a SeaBIOS containing Marc’s commit 74f96123 »Add IASL definition to the Makefile.« works fine. Thanks, Paul

1 0

← Newer
1
...
13
14
15
16
17
18
19
...
25
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot June 2012