coreboot April 2012

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459 discussions

New patch to review for coreboot: e6089c3 Add vsa processor to cbfs-files

by Patrick Georgi

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/960 -gerrit commit e6089c31deb1712509edd11c15081a4a189b325a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 23:15:17 2012 +0200 Add vsa processor to cbfs-files Change-Id: I548e86084acc51b0471160d37439385f524224cf Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile.inc | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index c179784..534b985 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -108,6 +108,14 @@ cbfs-files-processor-nvramtool= \ printf " CREATE $(2) (from $(1))\n"; $(objutil)/nvramtool/nvramtool -y $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout -D $(2).tmp -p $(1) && mv $(2).tmp $(2)) ####################################################################### +# Link VSA binary to ELF-ish stage +# arg1: source file +# arg2: binary file name +cbfs-files-processor-vsa= \ + $(eval $(2): $(1) ; \ + printf " CREATE $(2) (from $(1))\n"; $(OBJCOPY) --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 $(1) $(2).tmp && $(LD) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(2).tmp -o $(2)) + +####################################################################### # Add handler for arbitrary files in CBFS $(call add-special-class,cbfs-files) cbfs-files-handler= \

8 years, 5 months

New patch to review for coreboot: 2558f47 Support adding stages with cbfs-files

by Patrick Georgi

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/961 -gerrit commit 2558f479d59042d9748ba931fa2436cc07faa933 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 23:53:56 2012 +0200 Support adding stages with cbfs-files stages have special cbfstool syntax, which we need to support. Change-Id: I119255246af818f010acfc7ec2091a6184e74eb3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 45a90ac..a5116c0 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -58,8 +58,8 @@ extract_nth=$(word $(1), $(subst |, ,$(2))) ifneq ($(CONFIG_UPDATE_IMAGE),y) prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \ - $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \ + $(CBFSTOOL) $@.tmp add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage) $(call extract_nth,1,$(file)) \ + $(call extract_nth,2,$(file)) $(if $(filter-out stage,$(call extract_nth,3,$(file))),$(call extract_nth,3,$(file))) \ $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))

8 years, 5 months

New patch to review for coreboot: 63385c6 Make geode_lx use the vsa from blobs repository

by Patrick Georgi

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/959 -gerrit commit 63385c66126389fec8b6abc5923ec477442b360b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 22:56:30 2012 +0200 Make geode_lx use the vsa from blobs repository ... or fail if repository is not enabled. Change-Id: I0a1e6d6fed852ec7edf96ace8346ae6b23838a56 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/geode_lx/Kconfig | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index e5462c6..777dc94 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -19,9 +19,11 @@ config GEODE_VSA bool default y select PCI_OPTION_ROM_RUN_REALMODE + select REQUIRES_BLOB config GEODE_VSA_FILE bool "Add a VSA image" + default y help Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM. @@ -32,7 +34,7 @@ config GEODE_VSA_FILE config VSA_FILENAME string "AMD Geode LX VSA path and filename" depends on GEODE_VSA_FILE - default "gpl_vsa_lx_102.bin" + default "3rdparty/cpu/amd/geode_lx/gpl_vsa_lx_102.bin" help The path and filename of the file to use as VSA.

8 years, 5 months

New patch to review for coreboot: 88e6526 abuild: Add option to use binary files

by Patrick Georgi

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/958 -gerrit commit 88e65268cac4b433bc7dbd9b428d8b971f62b3df Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 22:55:28 2012 +0200 abuild: Add option to use binary files abuild -B enables the use of the blob repository. Change-Id: I2dd823d3b024ad249d72d668657bf6a6e92145cf Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/abuild/abuild | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 5b8d73d..e514db6 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -218,6 +218,11 @@ function create_config echo "CONFIG_CCACHE=y" >> ${build_dir}/config.build fi + if [ "$enable_blobs" = "true" ]; then + printf "(blobs enabled) " + echo "CONFIG_USE_BLOBS=y" >> ${build_dir}/config.build + fi + if [ "$scanbuild" = "true" ]; then printf "(scan-build enabled) " echo "CONFIG_SCANBUILD_ENABLE=y" >> ${build_dir}/config.build @@ -534,6 +539,7 @@ function myhelp printf " [-l|--loglevel <num>] set loglevel\n" printf " [-u|--update] update existing image\n" printf " [-P|--prefix <name>] file name prefix in CBFS\n" + printf " [-B|--blobs] Allow using binary files\n" printf " [lbroot] absolute path to coreboot sources\n" printf " (defaults to $ROOT)\n\n" } @@ -571,7 +577,7 @@ getopt - > /dev/null 2>/dev/null || gcc -o util/abuild/getopt util/abuild/getopt getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,verbose,help,all,target:,payloads:,test,cpus:,silent,junit,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache -o Vvhat:p:Tc:sJxCl:rP:uy -- "$@"` + args=`getopt -l version,verbose,help,all,target:,payloads:,test,cpus:,silent,junit,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache,blobs -o Vvhat:p:Tc:sJxCl:rP:uyB -- "$@"` eval set -- $args else # Detected non-GNU getopt @@ -605,6 +611,7 @@ while true ; do -l|--loglevel) shift; loglevel="$1"; shift;; -u|--update) shift; update="true";; -P|--prefix) shift; cbfs_prefix="$1"; shift;; + -B|--blobs) shift; enable_blobs="true";; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;;

8 years, 5 months

Patch merged into coreboot/master: 6cdd072 Add support for Sandybridge base Samsung ChromeBox

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 6cdd0725a167cda3f8058abdbade479a03b459c3 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 23:20:58 2012 +0200 Add support for Sandybridge base Samsung ChromeBox Change-Id: Ic93ad2749834c8f7a2ca1651d343561f2a496312 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Apr 28 02:23:07 2012, giving +1 See http://review.coreboot.org/953 for details. -gerrit

8 years, 5 months

Patch merged into coreboot/master: b5b33b3 Add support for Sandybridge based Samsung ChromeBook

by gerrit＠coreboot.org

the following patch was just integrated into master: commit b5b33b3c165f7c4130acd2373a931e0471db5b2a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 23:19:58 2012 +0200 Add support for Sandybridge based Samsung ChromeBook Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Apr 28 02:05:48 2012, giving +1 See http://review.coreboot.org/952 for details. -gerrit

8 years, 5 months

Patch merged into coreboot/master: 79dbd7c Add support for Intel Emerald Lake 2 CRB

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 79dbd7c183d0c822632c8d48be5ee52a588214b2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 23:16:30 2012 +0200 Add support for Intel Emerald Lake 2 CRB This adds support for Intel's Emerald Lake 2 board. Change-Id: Ifaeeac9d52fe655324ee29df5f7187b89b35f73a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Apr 28 01:48:52 2012, giving +1 See http://review.coreboot.org/951 for details. -gerrit

8 years, 5 months

Patch merged into coreboot/master: 6a01210 Fix up Sandybridge C state generation code

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 6a012104bf8e7a8c46ee7c6cff8d0f2df6e50d6e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 23:13:39 2012 +0200 Fix up Sandybridge C state generation code This code fixes the sandybridge C state generation code to work with the current version of the ACPI code generator. Change-Id: I56ae1185dc0694c06976236523fdcbe5c1795b01 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Apr 28 01:31:44 2012, giving +1 See http://review.coreboot.org/950 for details. -gerrit

8 years, 5 months

Patch merged into coreboot/master: f4bae7b acpigen: make acpigen_write_CST_package_entry non-static

by gerrit＠coreboot.org

the following patch was just integrated into master: commit f4bae7b934e4ba8fc018c368c88e6af0f7a5780b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 23:12:08 2012 +0200 acpigen: make acpigen_write_CST_package_entry non-static It's used by Sandybridge specific C state generation code. Change-Id: Ia6f1e14e748841a9646fd93d0a18f9e8f2a55e29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Apr 28 01:15:26 2012, giving +1 See http://review.coreboot.org/949 for details. -gerrit

8 years, 5 months

Patch merged into coreboot/master: 14b402f Sandybridge: Temporarily disable MRC cache finding code

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 14b402f91453491918235eaff0dd3287cbd4ae4e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 22:54:10 2012 +0200 Sandybridge: Temporarily disable MRC cache finding code This code is still using libfdt which was denied for inclusion in coreboot, so it won't compile as is. Without MRC cache, waking from suspend won't work, and cold boots are significantly slower (adds around 300-400ms per channel IIRC). A rework of this code is currently in the works, but will take a little bit more time (and should not hold back the mainboards being merged) Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Apr 28 02:55:24 2012, giving +1 See http://review.coreboot.org/948 for details. -gerrit

8 years, 5 months

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coreboot April 2012