coreboot April 2012

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New patch to review for coreboot: 84981fe Update PCIe Root Port _PRT to handle re-mapped functions
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/978 -gerrit commit 84981fe4c4542eecf8e834e19ba38f505515a3c0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 27 09:55:45 2012 -0700 Update PCIe Root Port _PRT to handle re-mapped functions The chipset enforces static-defined interrupt swizzling on PCIe root ports so if a port is remapped to a different function it needs to still report the proper interrupt map to the OS instead of assuming that function number is equivalent to root port number. This change also includes an update to the PCH function disable register which was incorrect for CPT/PPT and would cause unpredictable behavior if used. The kernel command line was changed to add 'nomsi' in order to force PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure that the mapping is correct. LUMPY current: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/acpi/pch.asl | 32 ++- src/southbridge/intel/bd82x6x/acpi/pcie.asl | 294 ++++++++++------------ src/southbridge/intel/bd82x6x/acpi/pcie_port.asl | 30 +++ 3 files changed, 188 insertions(+), 168 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 3e6651d..8632ad8 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -211,26 +211,32 @@ Scope(\) , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) - , 2, // Reserved - SATD, 1, // SATA disable + , 1, // Reserved + PCID, 1, // PCI bridge disable + SA1D, 1, // SATA1 disable SMBD, 1, // SMBUS disable HDAD, 1, // Azalia disable - , 2, // Reserved - ILND, 1, // Internal LAN disable - US1D, 1, // UHCI #1 disable - US2D, 1, // UHCI #2 disable - US3D, 1, // UHCI #3 disable - US4D, 1, // UHCI #4 disable - , 2, // Reserved + , 8, // Reserved + EH2D, 1, // EHCI #2 disable LPBD, 1, // LPC bridge disable - EHCD, 1, // EHCI disable - Offset(0x341a), // FD Root Ports + EH1D, 1, // EHCI #1 disable RP1D, 1, // Root Port 1 disable RP2D, 1, // Root Port 2 disable RP3D, 1, // Root Port 3 disable - RP4D, 1 // Root Port 4 disable + RP4D, 1, // Root Port 4 disable + RP5D, 1, // Root Port 5 disable + RP6D, 1, // Root Port 6 disable + RP7D, 1, // Root Port 7 disable + RP8D, 1, // Root Port 8 disable + TTRD, 1, // Thermal sensor registers disable + SA2D, 1, // SATA2 disable + Offset(0x3428), // FD2 (Function Disable 2) + BDFD, 1, // Display BDF + ME1D, 1, // ME Interface 1 disable + ME2D, 1, // ME Interface 2 disable + IDRD, 1, // IDE redirect disable + KTCT, 1, // Keyboard Text redirect disable } - } // High Definition Audio (Azalia) 0:1b.0 diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl index f6b93bf..934cf78 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,216 +20,199 @@ * MA 02110-1301 USA */ -/* Intel Cougar Point PCH PCIe support */ +/* Intel 6/7 Series PCH PCIe support */ // PCI Express Ports +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 19 }, + Package() { 0x0000ffff, 2, 0, 16 }, + Package() { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package() { + Package() { 0x0000ffff, 0, 0, 19 }, + Package() { 0x0000ffff, 1, 0, 16 }, + Package() { 0x0000ffff, 2, 0, 17 }, + Package() { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) + + Switch (ToInteger (Arg0)) { + /* PCIe Root Port 1 and 5 */ + Case (Package() { 1, 5 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + /* PCIe Root Port 2 and 6 */ + Case (Package() { 2, 6 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + /* PCIe Root Port 3 and 7 */ + Case (Package() { 3, 7 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + /* PCIe Root Port 4 and 8 */ + Case (Package() { 4, 8 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + Device (RP01) { - NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) + Name (_ADR, 0x001c0000) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } Device (RP02) { - NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) + Name (_ADR, 0x001c0001) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } Device (RP03) { - NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } - }) + Name (_ADR, 0x001c0002) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } Device (RP04) { - NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) + Name (_ADR, 0x001c0003) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } Device (RP05) { - NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) + Name (_ADR, 0x001c0004) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } Device (RP06) { - NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) + Name (_ADR, 0x001c0005) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } Device (RP07) { - NAME(_ADR, 0x001c0006) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } - }) + Name (_ADR, 0x001c0006) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } Device (RP08) { - NAME(_ADR, 0x001c0007) // FIXME: Have a macro for PCI Devices -> ACPI notation? - //#include "pcie_port.asl" - Method(_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } - }) + Name (_ADR, 0x001c0007) - } + #include "pcie_port.asl" + Method (_PRT) + { + Return (IRQM (RPPN)) } } - - diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl new file mode 100644 index 0000000..fedd9c9 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Included in each PCIe Root Port device */ + +OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) +Field (RPCS, AnyAcc, NoLock, Preserve) +{ + Offset (0x4c), // Link Capabilities + , 24, + RPPN, 8, // Root Port Number +}

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New patch to review for coreboot: 9bf656b Fix SATA port map to only enable port 0
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/977 -gerrit commit 9bf656b94d245b89d388fc63ff5512f32ad7b4ee Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 30 16:42:07 2012 -0700 Fix SATA port map to only enable port 0 The sata controller comes up in legacy/normal mode and is currently put into AHCI mode in romstage. If that is removed and the controller is left alone until the ramstage driver (like we do on Stumpy/Lumpy) then the resource allocator will have configured the device for IDE mode with an IO address in BAR5. Then when the ramstage driver puts the controller into AHCI mode it will not have the correct resources to do the rest of the AHCI setup. So the controller mode needs to be changed in the enable stage rather than in the init phase. This same register contains the port map and it is a R/WO (write once) field so the configured port map must be written at the same time. For non-AHCI mode the devicetree map was ignored before but it is used now. Since the port map register is now written at enable step it does not need to be written again during init. With this change the sata port map can be reduced to just port 0 and then U-boot does not have to probe all available ports. Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/sata.c | 29 ++++++++++++++++++++++------- 1 files changed, 22 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index ce5aea9..93dff91 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -48,8 +48,6 @@ static void sata_init(struct device *dev) if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); - /* Combine IDE - SATA configuration */ - pci_write_config16(dev, 0x90, 0x0000); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -88,9 +86,6 @@ static void sata_init(struct device *dev) u32 abar; printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); - /* Set Sata Controller Mode. */ - pci_write_config16(dev, 0x90, 0x0060 | - ((config->sata_port_map ^ 0x3f) << 8)); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ @@ -143,8 +138,6 @@ static void sata_init(struct device *dev) write32(abar + 0xa0, reg32); } else { printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); - /* Set Sata Controller Mode. No Mapping(?) */ - pci_write_config16(dev, 0x90, 0x0000); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -191,6 +184,27 @@ static void sata_init(struct device *dev) } } +static void sata_enable(device_t dev) +{ + /* Get the chip configuration */ + config_t *config = dev->chip_info; + u16 map = 0; + + if (!config) + return; + + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + if (config->sata_ahci) + map = 0x0060; + + map |= (config->sata_port_map ^ 0x3f) << 8; + + pci_write_config16(dev, 0x90, map); +} + static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -211,6 +225,7 @@ static struct device_operations sata_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, + .enable = sata_enable, .scan_bus = 0, .ops_pci = &sata_pci_ops, };

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New patch to review for coreboot: eb370e8 PantherPoint: Add additional PCI device IDs for SATA This includes IDs for the controller in normal mode and the desktop SKU IDs.
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/976 -gerrit commit eb370e842d0d89d58875d13a5610d796c5055a73 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Apr 24 10:00:41 2012 -0700 PantherPoint: Add additional PCI device IDs for SATA This includes IDs for the controller in normal mode and the desktop SKU IDs. Change-Id: I94c9d8d19a7a2ad9a0e560fa554c566b17c5d5ed Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/sata.c | 22 +++++++++++++++++++++- 1 files changed, 21 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 057b882..ce5aea9 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -238,7 +238,27 @@ static const struct pci_driver pch_sata_mobile_ahci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = 0x1c03, }; -static const struct pci_driver pch_sata_mobile_ahci_driver_a __pci_driver = { + +/* PantherPoint */ +static const struct pci_driver ppt_sata_desktop_normal_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e00, +}; + +static const struct pci_driver ppt_sata_mobile_normal_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e01, +}; + +static const struct pci_driver ppt_sata_desktop_ahci_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e02, +}; + +static const struct pci_driver ppt_sata_mobile_ahci_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x1e03,

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New patch to review for coreboot: 22fe62d Sandybridge: Display platform information early It is important to have the system configuration reported as early as possible to have a better idea what exact chipset the platform is running with.
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/975 -gerrit commit 22fe62dc4d4f662d067719bbac23dfb92891820e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 18 15:47:32 2012 -0700 Sandybridge: Display platform information early It is important to have the system configuration reported as early as possible to have a better idea what exact chipset the platform is running with. This change adds code to have an early coreboot module report the CPU and PCH information. CPU info includes the 32 bit feature information word, the symbolic processor brand string, and information about some features support, as obtained through CPUID instructions. The PCH information includes the symbolic device name and PCI device version. Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/raminit.c | 2 + .../intel/sandybridge/report_platform.c | 103 ++++++++++++++++++++ src/northbridge/intel/sandybridge/sandybridge.h | 1 + 4 files changed, 107 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index b72e9fa..79aa6ea 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -25,6 +25,7 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c romstage-y += udelay.c romstage-y += raminit.c romstage-y += early_init.c +romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index bbb743f..e1d5d26 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -318,6 +318,8 @@ void sdram_initialize(struct pei_data *pei_data) const char *target = "mrc.bin"; unsigned long entry; + report_platform_info(); + /* Wait for ME to be ready */ intel_early_me_init(); intel_early_me_uma_size(); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c new file mode 100644 index 0000000..d59cfe9 --- /dev/null +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/cpu.h> +#include <string.h> +#include "southbridge/intel/bd82x6x/pch.h" +#include <arch/io.h> +#include <arch/romcc_io.h> +#include "sandybridge.h" + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index; + char cpu_string[50]; /* 48 bytes are reported */ + int vt, txt, aes; + const char *mode[] = {"NOT ", ""}; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + } else { + u32 *p = (u32*) cpu_string; + for (i = 2; i <= 4 ; i++) { + cpuidr = cpuid(index + i); + *p++ = cpuidr.eax; + *p++ = cpuidr.ebx; + *p++ = cpuidr.ecx; + *p++ = cpuidr.edx; + } + } + cpuidr = cpuid(1); + printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_string); + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +/* The PCI id name match comes from Intel document 472178 */ +static struct { + u16 dev_id; + const char *dev_name; +} pch_table [] = { + {0x1E41, "Desktop Sample"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E44, "Z77"}, + {0x1E46, "Z75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E42, "Mobile Sample"}, + {0x1E55, "QM77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5d, "HM75"}, + {0x1E43, "SFF Sample"}, + {0x1E56, "QS77"}, +}; + +static void report_pch_info(void) +{ + int i; + u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); + + + const char *pch_type = "Unknown"; + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + printk (BIOS_DEBUG, "PCH type: %s rev id %x\n", + pch_type, pci_read_config8(PCH_LPC_DEV, 8)); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_pch_info(); +} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9ff6555..1aa3a11 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -218,6 +218,7 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); +void report_platform_info(void); #endif /* !__SMM__ */ #endif #endif

1 0

New patch to review for coreboot: 20e11fc Update Ivybridge GT power meter tables
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/974 -gerrit commit 20e11fca1ae27e041e0c8a4a1a6f5a6b4f5c2a05 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Apr 12 16:02:43 2012 -0700 Update Ivybridge GT power meter tables - New table for GT1 - Updates to GT2 17W table - New table for GT2 35W SKU - New table for GT2 Other This also includes a workaround to poll on a different register when deasserting force wake. On some SKUs the kernel is hanging when bringing up graphics unless this register is also polled. Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/sandybridge/gma.c | 168 ++++++++++++++++++++++++++++--- 1 files changed, 154 insertions(+), 14 deletions(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 181d901..499f347 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -79,6 +79,62 @@ struct gt_powermeter snb_pm_gt2[] = { }; struct gt_powermeter ivb_pm_gt1[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00021c00 }, + { 0xa808, 0x00000403 }, + { 0xa80c, 0x02001700 }, + { 0xa810, 0x05000200 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00690500 }, + { 0xa81c, 0x0000007f }, + { 0xa820, 0x01002501 }, + { 0xa824, 0x00000300 }, + { 0xa828, 0x01000331 }, + { 0xa82c, 0x0000000c }, + { 0xa830, 0x00010016 }, + { 0xa834, 0x01100101 }, + { 0xa838, 0x00010103 }, + { 0xa83c, 0x00041300 }, + { 0xa840, 0x00000b30 }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x7f000000 }, + { 0xa84c, 0x05000008 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000004 }, + { 0xa858, 0x00000007 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00010000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00001c00 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x06000000 }, + { 0xa910, 0x09000200 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00590000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x04002501 }, + { 0xa924, 0x00000100 }, + { 0xa928, 0x03000410 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00020000 }, + { 0xa934, 0x02070106 }, + { 0xa938, 0x00010100 }, + { 0xa93c, 0x00401c00 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x10000e00 }, + { 0xa94c, 0x02000004 }, + { 0xa950, 0x00000001 }, + { 0xa954, 0x00000004 }, + { 0xa960, 0x00060000 }, + { 0xaa3c, 0x00001c00 }, + { 0xaa54, 0x00000004 }, + { 0xaa60, 0x00060000 }, + { 0 } +}; + +struct gt_powermeter ivb_pm_gt2[] = { { 0xa800, 0x10000000 }, { 0xa804, 0x00033800 }, { 0xa808, 0x00000902 }, @@ -134,7 +190,7 @@ struct gt_powermeter ivb_pm_gt1[] = { { 0 } }; -struct gt_powermeter ivb_pm_gt2[] = { +struct gt_powermeter ivb_pm_gt2_17w[] = { { 0xa800, 0x20000000 }, { 0xa804, 0x000e3800 }, { 0xa808, 0x00000806 }, @@ -155,9 +211,9 @@ struct gt_powermeter ivb_pm_gt2[] = { { 0xa844, 0x00000000 }, { 0xa848, 0xff000000 }, { 0xa84c, 0x0a000010 }, - { 0xa850, 0x00000004 }, + { 0xa850, 0x00000002 }, { 0xa854, 0x00000008 }, - { 0xa858, 0x00000018 }, + { 0xa858, 0x0000000f }, { 0xa85c, 0x00000000 }, { 0xa860, 0x00020000 }, { 0xa248, 0x0000221e }, @@ -165,16 +221,72 @@ struct gt_powermeter ivb_pm_gt2[] = { { 0xa904, 0x00003800 }, { 0xa908, 0x00000000 }, { 0xa90c, 0x0c000000 }, - { 0xa910, 0x12000500 }, + { 0xa910, 0x12000800 }, { 0xa914, 0x00000000 }, { 0xa918, 0x00b20000 }, { 0xa91c, 0x00000000 }, { 0xa920, 0x08004b02 }, - { 0xa924, 0x00000200 }, - { 0xa928, 0x07000820 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, { 0xa92c, 0x00000000 }, { 0xa930, 0x00030000 }, - { 0xa934, 0x050f020d }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +struct gt_powermeter ivb_pm_gt2_35w[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00030400 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000300 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, { 0xa938, 0x00020300 }, { 0xa93c, 0x00903900 }, { 0xa940, 0x00000000 }, @@ -269,6 +381,12 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write(0xa188, 0xffff0001); if (!gtt_poll(0x130040, (1 << 0), (1 << 0))) return; + /* + * HACK: also poll on 0x130090, for some reason graphics does + * not work on all SKUs unless this register is polled at boot. + */ + if (!gtt_poll(0x130090, (1 << 0), (1 << 0))) + return; } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { @@ -297,17 +415,32 @@ static void gma_pm_init_pre_vbios(struct device *dev) } } else { u32 unit = MCHBAR32(0x5938) & 0xf; - u32 tdp = MCHBAR32(0x5930) & 0x7fff; - tdp /= (1 << unit); - if ((tdp <= 17) && !(reg32 & (1 << 13))) { - /* <=17W ULV and GT2 SKU */ - printk(BIOS_DEBUG, "IVB GT2 Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt2); - } else { + if (reg32 & (1 << 13)) { /* GT1 SKU */ printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt1); + } else { + /* GT2 SKU */ + u32 tdp = MCHBAR32(0x5930) & 0x7fff; + tdp /= (1 << unit); + + if (tdp <= 17) { + /* <=17W ULV */ + printk(BIOS_DEBUG, "IVB GT2 17W " + "Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt2_17w); + } else if ((tdp >= 25) && (tdp <= 35)) { + /* 25W-35W */ + printk(BIOS_DEBUG, "IVB GT2 35W " + "Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt2_35w); + } else { + /* All others */ + printk(BIOS_DEBUG, "IVB GT2 35W " + "Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt2_35w); + } } } @@ -441,6 +574,13 @@ static void gma_pm_init_post_vbios(struct device *dev) if (!gtt_poll(0x130040, (1 << 0), (0 << 0))) { return; } + /* + * HACK: also poll on 0x130090, for some reason graphics does + * not work on all SKUs unless this register is polled at boot. + */ + if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) { + return; + } gtt_write(0xa188, gtt_read(0xa188) | 1); }

1 0

New patch to review for coreboot: 8f492d6 Update ivybridge graphics initialization
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/973 -gerrit commit 8f492d6c487068317267a59a9a47c9be7b72a543 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Apr 9 12:05:18 2012 -0700 Update ivybridge graphics initialization - Add config options to set backlight registers - Update powermeter weight tables for IvyBridge GT1 and add a new table for GT2 SKU - Fix a few registers used during GPU PM init sequence Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/sandybridge/chip.h | 3 + src/northbridge/intel/sandybridge/gma.c | 309 ++++++++++++++++++++---------- 2 files changed, 213 insertions(+), 99 deletions(-) diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index b891884..bd89787 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -35,6 +35,9 @@ struct northbridge_intel_sandybridge_config { u16 gpu_panel_power_down_delay; /* T3 time sequence */ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + + u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ + u32 gpu_pch_backlight; /* PCH Backlight PWM value */ }; extern struct chip_operations northbridge_intel_sandybridge_ops; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 4aabb75..181d901 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -27,6 +27,169 @@ #include "chip.h" #include "sandybridge.h" +struct gt_powermeter { + u16 reg; + u32 value; +}; + +struct gt_powermeter snb_pm_gt1[] = { + { 0xa200, 0xcc000000 }, + { 0xa204, 0x07000040 }, + { 0xa208, 0x0000fe00 }, + { 0xa20c, 0x00000000 }, + { 0xa210, 0x17000000 }, + { 0xa214, 0x00000021 }, + { 0xa218, 0x0817fe19 }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0xcc000000 }, + { 0xa228, 0x07000040 }, + { 0xa22c, 0x0000fe00 }, + { 0xa230, 0x00000000 }, + { 0xa234, 0x17000000 }, + { 0xa238, 0x00000021 }, + { 0xa23c, 0x0817fe19 }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +struct gt_powermeter snb_pm_gt2[] = { + { 0xa200, 0x330000a6 }, + { 0xa204, 0x402d0031 }, + { 0xa208, 0x00165f83 }, + { 0xa20c, 0xf1000000 }, + { 0xa210, 0x00000000 }, + { 0xa214, 0x00160016 }, + { 0xa218, 0x002a002b }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0x330000a6 }, + { 0xa228, 0x402d0031 }, + { 0xa22c, 0x00165f83 }, + { 0xa230, 0xf1000000 }, + { 0xa234, 0x00000000 }, + { 0xa238, 0x00160016 }, + { 0xa23c, 0x002a002b }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +struct gt_powermeter ivb_pm_gt1[] = { + { 0xa800, 0x10000000 }, + { 0xa804, 0x00033800 }, + { 0xa808, 0x00000902 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x12000400 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20800 }, + { 0xa81c, 0x00000002 }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00010032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x0000151d }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x20001b00 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000000 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003500 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000500 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000200 }, + { 0xa928, 0x07000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x050f020d }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +struct gt_powermeter ivb_pm_gt2[] = { + { 0xa800, 0x20000000 }, + { 0xa804, 0x000e3800 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000800 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000004 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000018 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000500 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000200 }, + { 0xa928, 0x07000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x050f020d }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do * the mapping ourselfes @@ -63,6 +226,12 @@ static inline void gtt_write(u32 reg, u32 data) write32(gtt_res->base + reg, data); } +static inline void gtt_write_powermeter(struct gt_powermeter *pm) +{ + for (; pm && pm->reg; pm++) + gtt_write(pm->reg, pm->value); +} + #define GTT_RETRY 1000 static int gtt_poll(u32 reg, u32 mask, u32 value) { @@ -98,7 +267,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) } else { gtt_write(0xa180, 1 << 5); gtt_write(0xa188, 0xffff0001); - if (!gtt_poll(0x130090, (1 << 0), (1 << 0))) + if (!gtt_poll(0x130040, (1 << 0), (1 << 0))) return; } @@ -111,112 +280,35 @@ static void gma_pm_init_pre_vbios(struct device *dev) if (bridge_silicon_revision() >= IVB_STEP_A0) { /* Display Reset Acknowledge Settings */ - gtt_write(0xa18c, 0x00000001); reg32 = gtt_read(0x45010); reg32 |= (1 << 1) | (1 << 0); gtt_write(0x45010, reg32); } /* 2: Get GT SKU from GTT+0x911c[13] */ + reg32 = gtt_read(0x911c); if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - reg32 = gtt_read(0x911c); if (reg32 & (1 << 13)) { - printk(BIOS_DEBUG, "GT1 Power Meter Weights\n"); - gtt_write(0xa200, 0xcc000000); - gtt_write(0xa204, 0x07000040); - gtt_write(0xa208, 0x0000fe00); - gtt_write(0xa20c, 0x00000000); - gtt_write(0xa210, 0x17000000); - gtt_write(0xa214, 0x00000021); - gtt_write(0xa218, 0x0817fe19); - gtt_write(0xa21c, 0x00000000); - gtt_write(0xa220, 0x00000000); - gtt_write(0xa224, 0xcc000000); - gtt_write(0xa228, 0x07000040); - gtt_write(0xa22c, 0x0000fe00); - gtt_write(0xa230, 0x00000000); - gtt_write(0xa234, 0x17000000); - gtt_write(0xa238, 0x00000021); - gtt_write(0xa23c, 0x0817fe19); - gtt_write(0xa240, 0x00000000); - gtt_write(0xa244, 0x00000000); - gtt_write(0xa248, 0x8000421e); + printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); + gtt_write_powermeter(snb_pm_gt1); } else { - printk(BIOS_DEBUG, "GT2 Power Meter Weights\n"); - gtt_write(0xa200, 0x330000a6); - gtt_write(0xa204, 0x402d0031); - gtt_write(0xa208, 0x00165f83); - gtt_write(0xa20c, 0xf1000000); - gtt_write(0xa210, 0x00000000); - gtt_write(0xa214, 0x00160016); - gtt_write(0xa218, 0x002a002b); - gtt_write(0xa21c, 0x00000000); - gtt_write(0xa220, 0x00000000); - gtt_write(0xa224, 0x330000a6); - gtt_write(0xa228, 0x402d0031); - gtt_write(0xa22c, 0x00165f83); - gtt_write(0xa230, 0xf1000000); - gtt_write(0xa234, 0x00000000); - gtt_write(0xa238, 0x00160016); - gtt_write(0xa23c, 0x002a002b); - gtt_write(0xa240, 0x00000000); - gtt_write(0xa244, 0x00000000); - gtt_write(0xa248, 0x8000421e); + printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); + gtt_write_powermeter(snb_pm_gt2); } } else { - printk(BIOS_DEBUG, "IVB GT Power Meter Weights\n"); - gtt_write(0xa800, 0x00000000); - gtt_write(0xa804, 0x00023800); - gtt_write(0xa808, 0x00000902); - gtt_write(0xa80c, 0x0c002f00); - gtt_write(0xa810, 0x12000500); - gtt_write(0xa814, 0x00000000); - gtt_write(0xa818, 0x00b20000); - gtt_write(0xa81c, 0x00000002); - gtt_write(0xa820, 0x03004b02); - gtt_write(0xa824, 0x00000600); - gtt_write(0xa828, 0x07000773); - gtt_write(0xa82c, 0x00000000); - gtt_write(0xa830, 0x00010000); - gtt_write(0xa834, 0x0510020d); - gtt_write(0xa838, 0x00020100); - gtt_write(0xa83c, 0x00103700); - gtt_write(0xa840, 0x0000001d); - gtt_write(0xa844, 0x00000000); - gtt_write(0xa848, 0x20001b00); - gtt_write(0xa84c, 0x0a000010); - gtt_write(0xa850, 0x00000000); - gtt_write(0xa854, 0x00000008); - gtt_write(0xa858, 0x00000000); - gtt_write(0xa85c, 0x00000000); - gtt_write(0xa860, 0x00040000); - gtt_write(0xa248, 0x0000221e); - gtt_write(0xa900, 0x00000000); - gtt_write(0xa904, 0x00003500); - gtt_write(0xa908, 0x00000000); - gtt_write(0xa90c, 0x0c000000); - gtt_write(0xa910, 0x12000500); - gtt_write(0xa914, 0x00000000); - gtt_write(0xa918, 0x00b20000); - gtt_write(0xa91c, 0x00000000); - gtt_write(0xa920, 0x08004b02); - gtt_write(0xa924, 0x00000400); - gtt_write(0xa928, 0x07000820); - gtt_write(0xa92c, 0x00000000); - gtt_write(0xa930, 0x00030000); - gtt_write(0xa934, 0x050f020d); - gtt_write(0xa938, 0x00020300); - gtt_write(0xa93c, 0x00903900); - gtt_write(0xa940, 0x00000000); - gtt_write(0xa944, 0x00000000); - gtt_write(0xa948, 0x20001b00); - gtt_write(0xa94c, 0x0a000010); - gtt_write(0xa950, 0x00000000); - gtt_write(0xa954, 0x00000008); - gtt_write(0xa960, 0x00110000); - gtt_write(0xaa3c, 0x00003900); - gtt_write(0xaa54, 0x00000008); - gtt_write(0xaa60, 0x00110000); + u32 unit = MCHBAR32(0x5938) & 0xf; + u32 tdp = MCHBAR32(0x5930) & 0x7fff; + tdp /= (1 << unit); + + if ((tdp <= 17) && !(reg32 & (1 << 13))) { + /* <=17W ULV and GT2 SKU */ + printk(BIOS_DEBUG, "IVB GT2 Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt2); + } else { + /* GT1 SKU */ + printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt1); + } } /* 3: Gear ratio map */ @@ -339,9 +431,18 @@ static void gma_pm_init_post_vbios(struct device *dev) printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); /* 15: Deassert Force Wake */ - gtt_write(0xa18c, gtt_read(0xa18c) & ~1); - if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) - return; + if (bridge_silicon_revision() < IVB_STEP_C0) { + gtt_write(0xa18c, gtt_read(0xa18c) & ~1); + if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) { + return; + } + } else { + gtt_write(0xa188, 0x1fffe); + if (!gtt_poll(0x130040, (1 << 0), (0 << 0))) { + return; + } + gtt_write(0xa188, gtt_read(0xa188) | 1); + } /* 16: SW RC Control */ gtt_write(0xa094, 0x00060000); @@ -379,6 +480,16 @@ static void gma_pm_init_post_vbios(struct device *dev) reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; gtt_write(0xc7210, reg32); } + + /* Enable Backlight if needed */ + if (conf->gpu_cpu_backlight) { + gtt_write(0x48250, (1 << 31)); + gtt_write(0x48254, conf->gpu_cpu_backlight); + } + if (conf->gpu_pch_backlight) { + gtt_write(0xc8250, (1 << 31)); + gtt_write(0xc8254, conf->gpu_pch_backlight); + } } static void gma_func0_init(struct device *dev)

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New patch to review for coreboot: d3884c8 Fix TPM driver to work with multiple vendor TPMs
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/972 -gerrit commit d3884c83a8cc31b3b3bae3eee92e4d429d4c8d52 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 30 16:33:44 2012 -0700 Fix TPM driver to work with multiple vendor TPMs Port u-boot patch for low-level driver: - Fix bug in traversal of vendor name list. - Sending "command ready" needs additional logic to handle TPMs that need that bit set twice: once to empty the read FIFOs and once to actualy set command ready. Change-Id: I57c280266b2e966c5b90e4f9e968426a33b93cf1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/pc80/tpm.c | 85 ++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 75 insertions(+), 10 deletions(-) diff --git a/src/drivers/pc80/tpm.c b/src/drivers/pc80/tpm.c index 17e1ed7..c7b5081 100644 --- a/src/drivers/pc80/tpm.c +++ b/src/drivers/pc80/tpm.c @@ -127,13 +127,31 @@ struct vendor_name { const struct device_name* dev_names; }; +static const struct device_name atmel_devices[] = { + {0x3204, "AT97SC3204"}, + {0xffff} +}; + static const struct device_name infineon_devices[] = { - {0xb, "SLB9635 TT 1.2"}, - {0} + {0x000b, "SLB9635 TT 1.2"}, + {0xffff} +}; + +static const struct device_name nuvoton_devices[] = { + {0x00fe, "NPCT420AA V2"}, + {0xffff} +}; + +static const struct device_name stmicro_devices[] = { + {0x0000, "ST33ZP24" }, + {0xffff} }; static const struct vendor_name vendor_names[] = { + {0x1114, "Atmel", atmel_devices}, {0x15d1, "Infineon", infineon_devices}, + {0x1050, "Nuvoton", nuvoton_devices}, + {0x104a, "ST Microelectronics", stmicro_devices}, }; /* @@ -208,6 +226,44 @@ static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) } /* + * PC Client Specific TPM Interface Specification section 11.2.12: + * + * Software must be prepared to send two writes of a "1" to command ready + * field: the first to indicate successful read of all the data, thus + * clearing the data from the ReadFIFO and freeing the TPM's resources, + * and the second to indicate to the TPM it is about to send a new command. + * + * In practice not all TPMs behave the same so it is necessary to be + * flexible when trying to set command ready. + * + * Returns 0 on success if the TPM is ready for transactions. + * Returns TPM_TIMEOUT_ERR if the command ready bit does not get set. + */ +static int tis_command_ready(u8 locality) +{ + u32 status; + + /* 1st attempt to set command ready */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + /* Wait for response */ + status = tpm_read(locality, TIS_REG_STS); + + /* Check if command ready is set yet */ + if (status & TIS_STS_COMMAND_READY) + return 0; + + /* 2nd attempt to set command ready */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + /* Wait for command ready to get set */ + status = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_COMMAND_READY, TIS_STS_COMMAND_READY); + + return (status == TPM_TIMEOUT_ERR) ? TPM_TIMEOUT_ERR : 0; +} + +/* * Probe the TPM device and try determining its manufacturer/device name. * * Returns 0 on success (the device is found or was found during an earlier @@ -215,15 +271,17 @@ static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) */ static u32 tis_probe(void) { - u32 didvid = tpm_read(0, TIS_REG_DID_VID); - int i; const char *device_name = "unknown"; const char *vendor_name = device_name; + const struct device_name *dev; + u32 didvid; u16 vid, did; + int i; if (vendor_dev_id) return 0; /* Already probed. */ + didvid = tpm_read(0, TIS_REG_DID_VID); if (!didvid || (didvid == 0xffffffff)) { printf("%s: No TPM device found\n", __FUNCTION__); return TPM_DRIVER_ERR; @@ -238,11 +296,13 @@ static u32 tis_probe(void) u16 known_did; if (vid == vendor_names[i].vendor_id) { vendor_name = vendor_names[i].vendor_name; + } else { + continue; } - while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) { + dev = &vendor_names[i].dev_names[j]; + while ((known_did = dev->dev_id) != 0xffff) { if (known_did == did) { - device_name = - vendor_names[i].dev_names[j].dev_name; + device_name = dev->dev_name; break; } j++; @@ -250,7 +310,7 @@ static u32 tis_probe(void) break; } /* this will have to be converted into debug printout */ - TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name); + printf("Found TPM %s by %s\n", device_name, vendor_name); return 0; } @@ -446,7 +506,8 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) } /* Tell the TPM that we are done. */ - tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + if (tis_command_ready(locality) == TPM_TIMEOUT_ERR) + return TPM_DRIVER_ERR; *len = offset; return 0; @@ -492,7 +553,11 @@ int tis_open(void) return TPM_DRIVER_ERR; } - tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + /* Certain TPMs seem to need some delay here or they hang... */ + udelay(10); + + if (tis_command_ready(locality) == TPM_TIMEOUT_ERR) + return TPM_DRIVER_ERR; return 0; }

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New patch to review for coreboot: dc5c7e0 Don't disable ACPI in the S3 resume path
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/971 -gerrit commit dc5c7e0b63d9b8b3429ae6fb929cbb39efec4159 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Apr 9 12:31:43 2012 -0700 Don't disable ACPI in the S3 resume path The OS does not re-execute the APMC 'enable ACPI' SMI on resume so this has the potential to leave things in an unknown state. Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/lpc.c | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 9a3dc99..dddab6a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -396,15 +396,18 @@ static void pch_lock_smm(struct device *dev) u8 reg8; #endif + if (acpi_slp_type != 3) { #if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(0xe1, 0xb2); // Enable ACPI mode - printk(BIOS_DEBUG, "done.\n"); + printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); + outb(0xe1, 0xb2); // Enable ACPI mode + printk(BIOS_DEBUG, "done.\n"); #else - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(0x1e, 0xb2); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(0x1e, 0xb2); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); #endif + } + /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */

1 0

New patch to review for coreboot: 448a583 Only send ME Dram Init Done message on Sandybridge
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/970 -gerrit commit 448a58332fe61afe811862167486c6ec291963ba Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Apr 9 12:30:43 2012 -0700 Only send ME Dram Init Done message on Sandybridge This is done inside the SystemAgent binary on Ivybridge. Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/sandybridge/raminit.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index dcf9f63..bbb743f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -27,6 +27,7 @@ #include <cbfs.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> +#include <device/pci_def.h> #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" @@ -365,7 +366,13 @@ void sdram_initialize(struct pei_data *pei_data) version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); - intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + /* Send ME init done for SandyBridge here. This is done + * inside the SystemAgent binary on IvyBridge. */ + if (BASE_REV_SNB == + (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) + intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + else + intel_early_me_status(); report_memory_config();

1 0

New patch to review for coreboot: e3e901d Modify DMI init for IvyBridge
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/969 -gerrit commit e3e901db657591603411402a1ceb581873480442 Author: Vincent Palatin <vpalatin(a)chromium.org> Date: Wed Mar 28 16:10:29 2012 -0700 Modify DMI init for IvyBridge The ASPM setting for the Direct Media Interface should no longer be done on Ivybridge/PantherPoint based systems. Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c Signed-off-by: Vincent Palatin <vpalatin(a)chromium.org> --- src/northbridge/intel/sandybridge/northbridge.c | 18 +++++++++++------- 1 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e3334c4..b1f7c72 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -347,10 +347,12 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x1d0) = 0xffffffff; /* Steps prior to DMI ASPM */ - reg32 = DMIBAR32(0x250); - reg32 &= ~((1 << 22)|(1 << 20)); - reg32 |= (1 << 21); - DMIBAR32(0x250) = reg32; + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + reg32 = DMIBAR32(0x250); + reg32 &= ~((1 << 22)|(1 << 20)); + reg32 |= (1 << 21); + DMIBAR32(0x250) = reg32; + } reg32 = DMIBAR32(0x238); reg32 |= (1 << 29); @@ -372,9 +374,11 @@ static void northbridge_dmi_init(struct device *dev) } /* Enable ASPM on SNB link, should happen before PCH link */ - reg32 = DMIBAR32(0xd04); - reg32 |= (1 << 4); - DMIBAR32(0xd04) = reg32; + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + reg32 = DMIBAR32(0xd04); + reg32 |= (1 << 4); + DMIBAR32(0xd04) = reg32; + } reg32 = DMIBAR32(0x88); reg32 |= (1 << 1) | (1 << 0);

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coreboot April 2012