coreboot April 2012

coreboot@coreboot.org

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459 discussions

New patch to review for coreboot: e1b81de add new LPC controller device ID value
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/968 -gerrit commit e1b81deaf1c17cb2c6723b8a35a595e0e6edf162 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Apr 7 02:11:36 2012 +0000 add new LPC controller device ID value This adds the PCI device id of the LPC controller identifying the QPRJ/QS stepping of the Panther Point southbridge. Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/southbridge/intel/bd82x6x/lpc.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 1ecaf8f..9a3dc99 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -676,3 +676,8 @@ static const struct pci_driver c216_lpc __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = 0x1e55, }; +static const struct pci_driver hm75_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e5d, +};

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New patch to review for coreboot: ea39273 Clean up Emerald Lake 2 mainboard directory
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/967 -gerrit commit ea39273f80f64da5992b79e86ec950d6e0a3b420 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Mar 30 14:33:02 2012 -0700 Clean up Emerald Lake 2 mainboard directory Change-Id: I4a64a56dda22050a31232807096e15565a665377 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/mainboard/intel/emeraldlake2/gpio.h | 6 +++--- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/intel/emeraldlake2/thermal.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h index c458c83..05b9164 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.h +++ b/src/mainboard/intel/emeraldlake2/gpio.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef LINK_GPIO_H -#define LINK_GPIO_H +#ifndef EMERALDLAKE2_GPIO_H +#define EMERALDLAKE2_GPIO_H #include "southbridge/intel/bd82x6x/gpio.h" @@ -84,7 +84,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_map link_gpio_map = { +const struct pch_gpio_map emeraldlake2_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 23d1d6b..753d1d7 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -242,7 +242,7 @@ void main(unsigned long bist) /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&link_gpio_map); + setup_pch_gpios(&emeraldlake2_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ diff --git a/src/mainboard/intel/emeraldlake2/thermal.h b/src/mainboard/intel/emeraldlake2/thermal.h index deb40c2..883849d 100644 --- a/src/mainboard/intel/emeraldlake2/thermal.h +++ b/src/mainboard/intel/emeraldlake2/thermal.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef LINK_THERMAL_H -#define LINK_THERMAL_H +#ifndef EMERALDLAKE2_THERMAL_H +#define EMERALDLAKE2_THERMAL_H /* Fan is OFF */ #define FAN4_THRESHOLD_OFF 0

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New patch to review for coreboot: d7f3d69 Allow more CPU cores on Emerald Lake 2 CRB
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/966 -gerrit commit d7f3d6996e3d67f69533a69d773e4fde897d347a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Mar 28 13:19:15 2012 -0700 Allow more CPU cores on Emerald Lake 2 CRB The Emerald Lake 2 CRB can potentially have more than 8 CPU cores, so update the number of max cores accordingly. Change-Id: Ia42ed8a84916f66dfbfdf2a72cbbed5cea61899b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 9916aaa..002ae2a 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -37,7 +37,7 @@ config IRQ_SLOT_COUNT config MAX_CPUS int - default 8 + default 16 config MAX_PHYSICAL_CPUS int

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New patch to review for coreboot: db4ce07 Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/965 -gerrit commit db4ce0735688cb695465e162974d88f95e8a4833 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 29 18:04:56 2012 -0700 Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2. The Emerald Lake 2 CRB wasn't designed with ChromeOS in mind, so there aren't any actual developer mode, recovery mode, or write protect switches, let alone GPIOs to read them from. Instead, I've commandeered signals connected to GPIOs which are for other things but which aren't used by hardware or, for instance, the EC to do something Coreboot doesn't control. The recovery mode switch is connected to GPIO 22 and is called BIOS_REC on the schematic. The name is at least very reminiscent of the right thing even if it's supposed to be used for something else. There's a jumper on the board labelled J8G1 which can force the line to ground, and if not, there's a switch on the front of the case which toggles its value. "RECOVER" is for recovery mode and "KEEP" is for normal mode. The developer mode switch is connected to GPIO 57 and is called SV_DET on the schematic. It's connected to a jumper labelled J8E2 on the board and, as far as I can tell, can't be controlled in any other way. When the jumper is in place and the pins are shorted, developer mode is selected. When the jumper is removed, normal mode is selected. The write protect is connected to GPIO 48 which is called BIOS_RESP on the schematic. It's connected to a jumper labelled J8E3 which, like j8E2, seems to be the only way to control the line it's on. When the jumper is in place, write protect is "disabled", and when it's in place it's "enabled" even though there's no functional difference. The input for the recovery mode switch was chosen because of the name it already had on the CRB, BIOS recovery, and because there's a switch to control it on the front of the case which makes it easy to get at. The jumpers for developer mode and recovery mode were chosen because there weren't very many options available, and of those these were next to each other which should make them easier to find and work with. It might be a good idea to wire toggle switches up to the pins of those jumpers so they'll be easy to identify, can be labelled, and would be easier to work with than little jumpers in the middle of the motherboard. Change-Id: Ib2c3dc05077dacfbede596dae143ed81a99dbebd Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 6 +- src/mainboard/intel/emeraldlake2/chromeos.c | 44 ++++++++------------ src/mainboard/intel/emeraldlake2/gpio.h | 4 ++ 3 files changed, 24 insertions(+), 30 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl index 65202cb..81ead2e 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl @@ -65,9 +65,9 @@ Device (CRHW) Method(GPIO, 0, Serialized) { Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect + Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button + Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch + Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect Package() { 0x100, 0, 9, "CougarPoint" }, // debug header gpio Package() { 0x101, 0, 10, "CougarPoint" }, // debug header gpio 1 Package() { 0x102, 0, 12, "CougarPoint" }, // debug header gpio 2 diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 0acd20f..850af7b 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -45,36 +45,30 @@ void fill_lb_gpios(struct lb_gpios *gpios) if (!gpio_base) return; -#if 0 // Dev mode is hardcoded on, so we don't need to read these GPIOs. u32 gp_lvl = inl(gpio_base + 0x0c); -#endif u32 gp_lvl2 = inl(gpio_base + 0x38); - u32 gp_lvl3 = inl(gpio_base + 0x48); + /* u32 gp_lvl3 = inl(gpio_base + 0x48); */ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); gpios->count = GPIO_COUNT; - /* Write Protect: GPIO68 = CHP3_SPI_WP */ - gpios->gpios[0].port = 68; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = (gp_lvl3 >> (68-64)) & 1; + /* Write Protect: GPIO48 */ + gpios->gpios[0].port = 48; + gpios->gpios[0].polarity = ACTIVE_LOW; + gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1; strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); - /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = 42; + /* Recovery: GPIO22 */ + gpios->gpios[1].port = 22; gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = (gp_lvl2 >> (42-32)) & 1; + gpios->gpios[1].value = (gp_lvl >> 22) & 1; strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: GPIO17 = KBC3_DVP_MODE */ - gpios->gpios[2].port = 17; + /* Developer: GPIO57 */ + gpios->gpios[2].port = 57; gpios->gpios[2].polarity = ACTIVE_HIGH; -#if 0 // Dev mode is hardcoded on. - gpios->gpios[2].value = (gp_lvl >> 17) & 1; -#else - gpios->gpios[2].value = 1; -#endif + gpios->gpios[2].value = (gp_lvl2 >> (57-32)) & 1; strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); /* Hard code the lid switch GPIO to open. */ @@ -93,7 +87,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { -#if 0 // Dev mode is hardcoded on. device_t dev; #ifdef __PRE_RAM__ dev = PCI_DEV(0, 0x1f, 0); @@ -101,13 +94,10 @@ int get_developer_mode_switch(void) dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); #endif u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl = inl(gpio_base + 0x0c); + u32 gp_lvl2 = inl(gpio_base + 0x38); - /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ - return (gp_lvl >> 17) & 1; -#else - return 1; -#endif + /* Developer: GPIO17, active high */ + return (gp_lvl2 >> (57-32)) & 1; } int get_recovery_mode_switch(void) @@ -119,9 +109,9 @@ int get_recovery_mode_switch(void) dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); #endif u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl2 = inl(gpio_base + 0x38); + u32 gp_lvl = inl(gpio_base + 0x0c); - /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - return !((gp_lvl2 >> (42-32)) & 1); + /* Recovery: GPIO22, active low */ + return !((gp_lvl >> 22) & 1); } diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h index bec34aa..c458c83 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.h +++ b/src/mainboard/intel/emeraldlake2/gpio.h @@ -34,6 +34,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio12 = GPIO_MODE_GPIO, .gpio15 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, .gpio24 = GPIO_MODE_GPIO, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, @@ -49,6 +50,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio12 = GPIO_DIR_INPUT, .gpio15 = GPIO_DIR_INPUT, .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, .gpio27 = GPIO_DIR_INPUT, }; @@ -60,11 +62,13 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio36 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, .gpio57 = GPIO_MODE_GPIO, .gpio60 = GPIO_MODE_GPIO, }; const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio48 = GPIO_DIR_INPUT, .gpio57 = GPIO_DIR_INPUT, };

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New patch to review for coreboot: 887793d Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/964 -gerrit commit 887793df39d78bcdab65cb965a98fcd31b88fca4 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 29 17:58:52 2012 -0700 Set up the Emerald Lake 2 SMI and SCI sources based on the schematic. This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my best interpretation of the schematic. It may not be correct, but it doesn't seem to cause any problems either. Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/mainboard/intel/emeraldlake2/devicetree.cb | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 2631cfc..686fe2e 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -45,8 +45,10 @@ chip northbridge/intel/sandybridge # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi1_routing" = "0" + register "gpi1_routing" = "1" register "gpi14_routing" = "2" + register "alt_gp_smi_en" = "0x0002" + register "gpe0_en" = "0x4000" register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1"

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Patch merged into coreboot/master: 88e6526 abuild: Add option to use binary files
by gerrit＠coreboot.org 30 Apr '12

30 Apr '12

the following patch was just integrated into master: commit 88e65268cac4b433bc7dbd9b428d8b971f62b3df Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 22:55:28 2012 +0200 abuild: Add option to use binary files abuild -B enables the use of the blob repository. Change-Id: I2dd823d3b024ad249d72d668657bf6a6e92145cf Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/958 for details. -gerrit

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Patch merged into coreboot/master: 85c53cc Add Kconfig options to handle the blobs repository
by gerrit＠coreboot.org 30 Apr '12

30 Apr '12

the following patch was just integrated into master: commit 85c53ccd199b2790957234537e4deb0afdff9876 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 21:06:10 2012 +0200 Add Kconfig options to handle the blobs repository One option to allow using the repo (defaults to no), one to let boards state that they require it in the current configuration. The build system checks out the repo if allowed, and fails if the repo is requested by the configuration but not desired by the user. Change-Id: If71d80b329cf528aa467fcb0b4d9d7c7434aab27 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/957 for details. -gerrit

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Patch merged into coreboot/master: 248b15c Add 3rdparty as submodule
by gerrit＠coreboot.org 30 Apr '12

30 Apr '12

the following patch was just integrated into master: commit 248b15cc4a4dff6570acf1b32485f03ec326d19f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 20:11:34 2012 +0200 Add 3rdparty as submodule The build system will make sure only to fetch this if desired by the user. Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/956 for details. -gerrit

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New patch to review for coreboot: faffebf Fix Sandybridge/Ivybridge mainboards according to code review
by Stefan Reinauer 30 Apr '12

30 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/963 -gerrit commit faffebf1bf40107559cf965e5d547c2a82d6db87 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 30 14:57:51 2012 -0700 Fix Sandybridge/Ivybridge mainboards according to code review This fixes a few cosmetics with the following three boards: - Intel Emerald Lake 2 - Samsung ChromeBook - Samsung ChromeBox The following issues were fixed: - rely on include path in ASL code instead of specifying relative paths - use updated ALIGN_CURRENT in acpi_tables.c - use preprocessor defines instead of hard coded values where possible Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/acpi/superio.asl | 2 +- src/mainboard/intel/emeraldlake2/acpi_tables.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 18 +++++++++--------- src/mainboard/samsung/lumpy/acpi/superio.asl | 2 +- src/mainboard/samsung/lumpy/acpi_tables.c | 2 +- src/mainboard/samsung/lumpy/romstage.c | 18 +++++++++--------- src/mainboard/samsung/stumpy/acpi/superio.asl | 2 +- src/mainboard/samsung/stumpy/acpi_tables.c | 2 +- src/mainboard/samsung/stumpy/romstage.c | 18 +++++++++--------- src/northbridge/intel/sandybridge/sandybridge.h | 1 + 10 files changed, 34 insertions(+), 33 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl index f803aaf..a50c4b3 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl @@ -32,4 +32,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "../../../../superio/smsc/sio1007/acpi/superio.asl" +#include "superio/smsc/sio1007/acpi/superio.asl" diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index c84ac46..01d4b54 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -180,7 +180,7 @@ unsigned long acpi_fill_srat(unsigned long current) void smm_setup_structures(void *gnvs, void *tcg, void *smi1); -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +#define ALIGN_CURRENT current = (ALIGN(current, 16)) unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 23d1d6b..0cf113b 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -188,17 +188,17 @@ void main(unsigned long bist) #endif struct pei_data pei_data = { pei_version: PEI_VERSION, - mchbar: 0xfed10000, - dmibar: 0xfed18000, - epbar: 0xfed19000, - pciexbar: 0xf0000000, - smbusbar: 0x400, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + smbusbar: SMBUS_IO_BASE, wdbbar: 0x4000000, wdbsize: 0x1000, - hpet_address: 0xfed00000, - rcba: 0xfed1c000, - pmbase: 0x500, - gpiobase: 0x480, + hpet_address: HPET_ADDR, + rcba: DEFAULT_RCBABASE, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, thermalbase: 0xfed08000, system_type: 0, // 0 Mobile, 1 Desktop/Server tseg_size: CONFIG_SMM_TSEG_SIZE, diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl index 465fa54..01d9447 100644 --- a/src/mainboard/samsung/lumpy/acpi/superio.asl +++ b/src/mainboard/samsung/lumpy/acpi/superio.asl @@ -35,4 +35,4 @@ #define SIO_ENABLE_SMBX // pnp 2e.9: Enable Mailbox #define SIO_SMBX_IO0 0xa00 // pnp 2e.9: io 0xa00 -#include "../../../../superio/smsc/mec1308/acpi/superio.asl" +#include "superio/smsc/mec1308/acpi/superio.asl" diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index a9eeb74..46fdf31 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -177,7 +177,7 @@ unsigned long acpi_fill_srat(unsigned long current) void smm_setup_structures(void *gnvs, void *tcg, void *smi1); -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +#define ALIGN_CURRENT current = (ALIGN(current, 16)) unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 7aa4746..82856f6 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -151,17 +151,17 @@ void main(unsigned long bist) #endif struct pei_data pei_data = { - .mchbar = 0xfed10000, - .dmibar = 0xfed18000, - .epbar = 0xfed19000, - .pciexbar = 0xf0000000, - .smbusbar = 0x400, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = 0xfed00000, - .rcba = 0xfed1c000, - .pmbase = 0x500, - .gpiobase = 0x480, + .hpet_address = HPET_ADDR, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, diff --git a/src/mainboard/samsung/stumpy/acpi/superio.asl b/src/mainboard/samsung/stumpy/acpi/superio.asl index 24bc8cf..75869ca 100644 --- a/src/mainboard/samsung/stumpy/acpi/superio.asl +++ b/src/mainboard/samsung/stumpy/acpi/superio.asl @@ -32,4 +32,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "../../../../superio/ite/it8772f/acpi/superio.asl" +#include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 686e7dc..68da59d 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -181,7 +181,7 @@ unsigned long acpi_fill_srat(unsigned long current) void smm_setup_structures(void *gnvs, void *tcg, void *smi1); -#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +#define ALIGN_CURRENT current = (ALIGN(current, 16)) unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index c7c392d..10a9d7b 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -186,17 +186,17 @@ void main(unsigned long bist) }; #endif struct pei_data pei_data = { - mchbar: 0xfed10000, - dmibar: 0xfed18000, - epbar: 0xfed19000, - pciexbar: 0xf0000000, - smbusbar: 0x400, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + smbusbar: SMBUS_IO_BASE, wdbbar: 0x4000000, wdbsize: 0x1000, - hpet_address: 0xfed00000, - rcba: 0xfed1c000, - pmbase: 0x500, - gpiobase: 0x480, + hpet_address: HPET_ADDR, + rcba: DEFAULT_RCBABASE, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, thermalbase: 0xfed08000, system_type: 0, // 0 Mobile, 1 Desktop/Server tseg_size: CONFIG_SMM_TSEG_SIZE, diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9ff6555..c7bea98 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -51,6 +51,7 @@ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_RCBABASE 0xfed1c000 #include "../../../southbridge/intel/bd82x6x/pch.h"

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New patch to review for coreboot: 68ae60f Move VSA support from x86 to Geode
by Patrick Georgi 30 Apr '12

30 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/962 -gerrit commit 68ae60f6d9bcef7e365a3a00fbe78111e7da7ee6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 23:56:58 2012 +0200 Move VSA support from x86 to Geode Instead of the special case in the generic Makefile.inc, use cbfs-files in the CPU directories. Change-Id: I71d9c8dff906c9a516ac0dd09a315f8956075592 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 9 --------- src/cpu/amd/geode_gx2/Makefile.inc | 4 ++++ src/cpu/amd/geode_lx/Makefile.inc | 4 ++++ 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a5116c0..5486bb1 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -49,9 +49,6 @@ endif ifeq ($(CONFIG_AP_CODE_IN_CAR),y) COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf endif -ifeq ($(CONFIG_GEODE_VSA_FILE),y) -COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_VSA_FILENAME) -endif extract_nth=$(word $(1), $(subst |, ,$(2))) @@ -96,12 +93,6 @@ ifeq ($(CONFIG_PAYLOAD_FILO),y) @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) endif -ifeq ($(CONFIG_GEODE_VSA_FILE),y) - @printf " VSA $(CONFIG_VSA_FILENAME)\n" - $(OBJCOPY) --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 $(CONFIG_VSA_FILENAME) $(obj)/vsa.o - $(LD) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(obj)/vsa.o -o $(obj)/vsa.elf - $(CBFSTOOL) $@.tmp add-stage $(obj)/vsa.elf vsa -endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index b70537a..d3777a6 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -7,3 +7,7 @@ driver-y += geode_gx2_init.c ramstage-y += cpubug.c cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc + +cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa +vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa +vsa-type = stage diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index a5e1281..4b2b37c 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -7,3 +7,7 @@ driver-y += geode_lx_init.c ramstage-y += cpubug.c cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc + +cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa +vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa +vsa-type = stage

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coreboot April 2012