New patch to review for coreboot: faffebf Fix Sandybridge/Ivybridge mainboards according to code review

[Stefan Reinauer]

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/963

-gerrit

commit faffebf1bf40107559cf965e5d547c2a82d6db87
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date:   Mon Apr 30 14:57:51 2012 -0700

    Fix Sandybridge/Ivybridge mainboards according to code review
    
    This fixes a few cosmetics with the following three boards:
    
     - Intel Emerald Lake 2
     - Samsung ChromeBook
     - Samsung ChromeBox
    
    The following issues were fixed:
    
     - rely on include path in ASL code instead of specifying relative
       paths
     - use updated ALIGN_CURRENT in acpi_tables.c
     - use preprocessor defines instead of hard coded values where possible
    
    Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
    Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
---
 src/mainboard/intel/emeraldlake2/acpi/superio.asl |    2 +-
 src/mainboard/intel/emeraldlake2/acpi_tables.c    |    2 +-
 src/mainboard/intel/emeraldlake2/romstage.c       |   18 +++++++++---------
 src/mainboard/samsung/lumpy/acpi/superio.asl      |    2 +-
 src/mainboard/samsung/lumpy/acpi_tables.c         |    2 +-
 src/mainboard/samsung/lumpy/romstage.c            |   18 +++++++++---------
 src/mainboard/samsung/stumpy/acpi/superio.asl     |    2 +-
 src/mainboard/samsung/stumpy/acpi_tables.c        |    2 +-
 src/mainboard/samsung/stumpy/romstage.c           |   18 +++++++++---------
 src/northbridge/intel/sandybridge/sandybridge.h   |    1 +
 10 files changed, 34 insertions(+), 33 deletions(-)

diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl
b/src/mainboard/intel/emeraldlake2/acpi/superio.asl
index f803aaf..a50c4b3 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl
@@ -32,4 +32,4 @@
 #define SIO_GPIO_IO0      0x720  // pnp 2e.7: io 0x60
 #define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
 
-#include "../../../../superio/smsc/sio1007/acpi/superio.asl"
+#include "superio/smsc/sio1007/acpi/superio.asl"
diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c
b/src/mainboard/intel/emeraldlake2/acpi_tables.c
index c84ac46..01d4b54 100644
--- a/src/mainboard/intel/emeraldlake2/acpi_tables.c
+++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c
@@ -180,7 +180,7 @@ unsigned long acpi_fill_srat(unsigned long current)
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 
-#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c
b/src/mainboard/intel/emeraldlake2/romstage.c
index 23d1d6b..0cf113b 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -188,17 +188,17 @@ void main(unsigned long bist)
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,
-		mchbar: 0xfed10000,
-		dmibar: 0xfed18000,
-		epbar: 0xfed19000,
-		pciexbar: 0xf0000000,
-		smbusbar: 0x400,
+		mchbar: DEFAULT_MCHBAR,
+		dmibar: DEFAULT_DMIBAR,
+		epbar: DEFAULT_EPBAR,
+		pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+		smbusbar: SMBUS_IO_BASE,
 		wdbbar: 0x4000000,
 		wdbsize: 0x1000,
-		hpet_address: 0xfed00000,
-		rcba: 0xfed1c000,
-		pmbase: 0x500,
-		gpiobase: 0x480,
+		hpet_address: HPET_ADDR,
+		rcba: DEFAULT_RCBABASE,
+		pmbase: DEFAULT_PMBASE,
+		gpiobase: DEFAULT_GPIOBASE,
 		thermalbase: 0xfed08000,
 		system_type: 0, // 0 Mobile, 1 Desktop/Server
 		tseg_size: CONFIG_SMM_TSEG_SIZE,
diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl
b/src/mainboard/samsung/lumpy/acpi/superio.asl
index 465fa54..01d9447 100644
--- a/src/mainboard/samsung/lumpy/acpi/superio.asl
+++ b/src/mainboard/samsung/lumpy/acpi/superio.asl
@@ -35,4 +35,4 @@
 #define SIO_ENABLE_SMBX          // pnp 2e.9: Enable Mailbox
 #define SIO_SMBX_IO0      0xa00  // pnp 2e.9: io 0xa00
 
-#include "../../../../superio/smsc/mec1308/acpi/superio.asl"
+#include "superio/smsc/mec1308/acpi/superio.asl"
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c
b/src/mainboard/samsung/lumpy/acpi_tables.c
index a9eeb74..46fdf31 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -177,7 +177,7 @@ unsigned long acpi_fill_srat(unsigned long current)
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 
-#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
diff --git a/src/mainboard/samsung/lumpy/romstage.c
b/src/mainboard/samsung/lumpy/romstage.c
index 7aa4746..82856f6 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -151,17 +151,17 @@ void main(unsigned long bist)
 #endif
 
 	struct pei_data pei_data = {
-		.mchbar = 0xfed10000,
-		.dmibar = 0xfed18000,
-		.epbar = 0xfed19000,
-		.pciexbar = 0xf0000000,
-		.smbusbar = 0x400,
+		.mchbar = DEFAULT_MCHBAR,
+		.dmibar = DEFAULT_DMIBAR,
+		.epbar = DEFAULT_EPBAR,
+		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+		.smbusbar = SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
-		.hpet_address = 0xfed00000,
-		.rcba = 0xfed1c000,
-		.pmbase = 0x500,
-		.gpiobase = 0x480,
+		.hpet_address = HPET_ADDR,
+		.rcba = DEFAULT_RCBABASE,
+		.pmbase = DEFAULT_PMBASE,
+		.gpiobase = DEFAULT_GPIOBASE,
 		.thermalbase = 0xfed08000,
 		.system_type = 0, // 0 Mobile, 1 Desktop/Server
 		.tseg_size = CONFIG_SMM_TSEG_SIZE,
diff --git a/src/mainboard/samsung/stumpy/acpi/superio.asl
b/src/mainboard/samsung/stumpy/acpi/superio.asl
index 24bc8cf..75869ca 100644
--- a/src/mainboard/samsung/stumpy/acpi/superio.asl
+++ b/src/mainboard/samsung/stumpy/acpi/superio.asl
@@ -32,4 +32,4 @@
 #define SIO_GPIO_IO0      0x720  // pnp 2e.7: io 0x60
 #define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
 
-#include "../../../../superio/ite/it8772f/acpi/superio.asl"
+#include "superio/ite/it8772f/acpi/superio.asl"
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c
b/src/mainboard/samsung/stumpy/acpi_tables.c
index 686e7dc..68da59d 100644
--- a/src/mainboard/samsung/stumpy/acpi_tables.c
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -181,7 +181,7 @@ unsigned long acpi_fill_srat(unsigned long current)
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 
-#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
diff --git a/src/mainboard/samsung/stumpy/romstage.c
b/src/mainboard/samsung/stumpy/romstage.c
index c7c392d..10a9d7b 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -186,17 +186,17 @@ void main(unsigned long bist)
 	};
 #endif
 	struct pei_data pei_data = {
-		mchbar: 0xfed10000,
-		dmibar: 0xfed18000,
-		epbar: 0xfed19000,
-		pciexbar: 0xf0000000,
-		smbusbar: 0x400,
+		mchbar: DEFAULT_MCHBAR,
+		dmibar: DEFAULT_DMIBAR,
+		epbar: DEFAULT_EPBAR,
+		pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+		smbusbar: SMBUS_IO_BASE,
 		wdbbar: 0x4000000,
 		wdbsize: 0x1000,
-		hpet_address: 0xfed00000,
-		rcba: 0xfed1c000,
-		pmbase: 0x500,
-		gpiobase: 0x480,
+		hpet_address: HPET_ADDR,
+		rcba: DEFAULT_RCBABASE,
+		pmbase: DEFAULT_PMBASE,
+		gpiobase: DEFAULT_GPIOBASE,
 		thermalbase: 0xfed08000,
 		system_type: 0, // 0 Mobile, 1 Desktop/Server
 		tseg_size: CONFIG_SMM_TSEG_SIZE,
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h
b/src/northbridge/intel/sandybridge/sandybridge.h
index 9ff6555..c7bea98 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -51,6 +51,7 @@
 #define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+#define DEFAULT_RCBABASE	0xfed1c000
 
 #include "../../../southbridge/intel/bd82x6x/pch.h"