coreboot April 2012

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Patch merged into coreboot/master: 624c4fe Add support for aligned allocation
by gerrit＠coreboot.org 12 Apr '12

12 Apr '12

the following patch was just integrated into master: commit 624c4fed563e3bc8e8fe900f1b8ad705a1700c37 Author: Ron Minnich <rminnich(a)gmail.com> Date: Wed Apr 11 10:30:15 2012 -0700 Add support for aligned allocation Add a memalign function and have malloc use it. Also, change the default alignment for malloc to u64-aligned. Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/887 for details. -gerrit

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Patch set updated for coreboot: a7ae186 Leverage the Pstate table created by AGESA.
by Zheng Bao 12 Apr '12

12 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/884 -gerrit commit a7ae186ed9dcd7edf501c14bde5480fdaff99c2a Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 12 11:27:26 2012 +0800 Leverage the Pstate table created by AGESA. The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts from 0. The dsdt should be aligned with that. This feature has only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi/cpstate.asl | 74 -------------- src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/dsdt.asl | 48 +++++++--- src/mainboard/amd/inagua/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/inagua/acpi_tables.c | 8 +- src/mainboard/amd/inagua/dsdt.asl | 24 ++++- src/mainboard/amd/persimmon/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/persimmon/acpi_tables.c | 8 +- src/mainboard/amd/persimmon/dsdt.asl | 24 ++++- src/mainboard/amd/south_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/south_station/acpi_tables.c | 12 +- src/mainboard/amd/south_station/dsdt.asl | 24 ++++- src/mainboard/amd/torpedo/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/torpedo/dsdt.asl | 18 ++-- src/mainboard/amd/union_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/union_station/acpi_tables.c | 12 +- src/mainboard/amd/union_station/dsdt.asl | 24 ++++- src/mainboard/asrock/e350m1/acpi/cpstate.asl | 75 -------------- src/mainboard/asrock/e350m1/acpi_tables.c | 12 +- src/mainboard/asrock/e350m1/dsdt.asl | 24 ++++- src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 75 -------------- src/mainboard/supermicro/h8qgi/acpi_tables.c | 8 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 115 +++++++++++----------- 23 files changed, 222 insertions(+), 746 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl deleted file mode 100644 index 64b3f16..0000000 --- a/src/mainboard/amd/dinar/acpi/cpstate.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index ee00e81..741ba99 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 1cbb05e..501ec78 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -51,37 +51,61 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x0 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } + Processor( + C004, /* name space name */ + 4, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C005, /* name space name */ + 5, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C006, /* name space name */ + 6, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C007, /* name space name */ + 7, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h. */ diff --git a/src/mainboard/amd/inagua/acpi/cpstate.asl b/src/mainboard/amd/inagua/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/inagua/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 8f47591..e521b4b 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 361adbb..7708676 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/acpi/cpstate.asl b/src/mainboard/amd/persimmon/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/persimmon/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 9526fea..00a08d2 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index b480c33..bd9ce74 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/acpi/cpstate.asl b/src/mainboard/amd/south_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/south_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 7f03a43..b18bcb2 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/acpi/cpstate.asl b/src/mainboard/amd/torpedo/acpi/cpstate.asl deleted file mode 100755 index 5eca9cc..0000000 --- a/src/mainboard/amd/torpedo/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index a8a731d..758fba5 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -51,36 +51,32 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/acpi/cpstate.asl b/src/mainboard/amd/union_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/union_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index fb2cfe8..7e49fd4 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/acpi/cpstate.asl b/src/mainboard/asrock/e350m1/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/asrock/e350m1/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 97533c1..c2ea1fb 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7314283..7b97a92 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 137a90d..2955eea 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -65,69 +65,68 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - P000, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0x00, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - //#include "acpi/cpstate.asl" } - Processor(P001, 0x01, 0x00000000, 0x00) {} - Processor(P002, 0x02, 0x00000000, 0x00) {} - Processor(P003, 0x03, 0x00000000, 0x00) {} - Processor(P004, 0x04, 0x00000000, 0x00) {} - Processor(P005, 0x05, 0x00000000, 0x00) {} - Processor(P006, 0x06, 0x00000000, 0x00) {} - Processor(P007, 0x07, 0x00000000, 0x00) {} - Processor(P008, 0x08, 0x00000000, 0x00) {} - Processor(P009, 0x09, 0x00000000, 0x00) {} - Processor(P00A, 0x0A, 0x00000000, 0x00) {} - Processor(P00B, 0x0B, 0x00000000, 0x00) {} - Processor(P00C, 0x0C, 0x00000000, 0x00) {} - Processor(P00D, 0x0D, 0x00000000, 0x00) {} - Processor(P00E, 0x0E, 0x00000000, 0x00) {} - Processor(P00F, 0x0F, 0x00000000, 0x00) {} - Processor(P010, 0x10, 0x00000000, 0x00) {} - Processor(P011, 0x11, 0x00000000, 0x00) {} - Processor(P012, 0x12, 0x00000000, 0x00) {} - Processor(P013, 0x13, 0x00000000, 0x00) {} - Processor(P014, 0x14, 0x00000000, 0x00) {} - Processor(P015, 0x15, 0x00000000, 0x00) {} - Processor(P016, 0x16, 0x00000000, 0x00) {} - Processor(P017, 0x17, 0x00000000, 0x00) {} - Processor(P018, 0x18, 0x00000000, 0x00) {} - Processor(P019, 0x19, 0x00000000, 0x00) {} - Processor(P01A, 0x1A, 0x00000000, 0x00) {} - Processor(P01B, 0x1B, 0x00000000, 0x00) {} - Processor(P01C, 0x1C, 0x00000000, 0x00) {} - Processor(P01D, 0x1D, 0x00000000, 0x00) {} - Processor(P01E, 0x1E, 0x00000000, 0x00) {} - Processor(P01F, 0x1F, 0x00000000, 0x00) {} - Processor(P020, 0x20, 0x00000000, 0x00) {} - Processor(P021, 0x21, 0x00000000, 0x00) {} - Processor(P022, 0x22, 0x00000000, 0x00) {} - Processor(P023, 0x23, 0x00000000, 0x00) {} - Processor(P024, 0x24, 0x00000000, 0x00) {} - Processor(P025, 0x25, 0x00000000, 0x00) {} - Processor(P026, 0x26, 0x00000000, 0x00) {} - Processor(P027, 0x27, 0x00000000, 0x00) {} - Processor(P028, 0x28, 0x00000000, 0x00) {} - Processor(P029, 0x29, 0x00000000, 0x00) {} - Processor(P02A, 0x2A, 0x00000000, 0x00) {} - Processor(P02B, 0x2B, 0x00000000, 0x00) {} - Processor(P02C, 0x2C, 0x00000000, 0x00) {} - Processor(P02D, 0x2D, 0x00000000, 0x00) {} - Processor(P02E, 0x2E, 0x00000000, 0x00) {} - Processor(P02F, 0x2F, 0x00000000, 0x00) {} - Alias (P000, CPU0) - Alias (P001, CPU1) - Alias (P002, CPU2) - Alias (P003, CPU3) - Alias (P004, CPU4) - Alias (P005, CPU5) - Alias (P006, CPU6) - Alias (P007, CPU7) - Alias (P008, CPU8) + Processor(C001, 0x01, 0x00000000, 0x00) {} + Processor(C002, 0x02, 0x00000000, 0x00) {} + Processor(C003, 0x03, 0x00000000, 0x00) {} + Processor(C004, 0x04, 0x00000000, 0x00) {} + Processor(C005, 0x05, 0x00000000, 0x00) {} + Processor(C006, 0x06, 0x00000000, 0x00) {} + Processor(C007, 0x07, 0x00000000, 0x00) {} + Processor(C008, 0x08, 0x00000000, 0x00) {} + Processor(C009, 0x09, 0x00000000, 0x00) {} + Processor(C00A, 0x0A, 0x00000000, 0x00) {} + Processor(C00B, 0x0B, 0x00000000, 0x00) {} + Processor(C00C, 0x0C, 0x00000000, 0x00) {} + Processor(C00D, 0x0D, 0x00000000, 0x00) {} + Processor(C00E, 0x0E, 0x00000000, 0x00) {} + Processor(C00F, 0x0F, 0x00000000, 0x00) {} + Processor(C010, 0x10, 0x00000000, 0x00) {} + Processor(C011, 0x11, 0x00000000, 0x00) {} + Processor(C012, 0x12, 0x00000000, 0x00) {} + Processor(C013, 0x13, 0x00000000, 0x00) {} + Processor(C014, 0x14, 0x00000000, 0x00) {} + Processor(C015, 0x15, 0x00000000, 0x00) {} + Processor(C016, 0x16, 0x00000000, 0x00) {} + Processor(C017, 0x17, 0x00000000, 0x00) {} + Processor(C018, 0x18, 0x00000000, 0x00) {} + Processor(C019, 0x19, 0x00000000, 0x00) {} + Processor(C01A, 0x1A, 0x00000000, 0x00) {} + Processor(C01B, 0x1B, 0x00000000, 0x00) {} + Processor(C01C, 0x1C, 0x00000000, 0x00) {} + Processor(C01D, 0x1D, 0x00000000, 0x00) {} + Processor(C01E, 0x1E, 0x00000000, 0x00) {} + Processor(C01F, 0x1F, 0x00000000, 0x00) {} + Processor(C020, 0x20, 0x00000000, 0x00) {} + Processor(C021, 0x21, 0x00000000, 0x00) {} + Processor(C022, 0x22, 0x00000000, 0x00) {} + Processor(C023, 0x23, 0x00000000, 0x00) {} + Processor(C024, 0x24, 0x00000000, 0x00) {} + Processor(C025, 0x25, 0x00000000, 0x00) {} + Processor(C026, 0x26, 0x00000000, 0x00) {} + Processor(C027, 0x27, 0x00000000, 0x00) {} + Processor(C028, 0x28, 0x00000000, 0x00) {} + Processor(C029, 0x29, 0x00000000, 0x00) {} + Processor(C02A, 0x2A, 0x00000000, 0x00) {} + Processor(C02B, 0x2B, 0x00000000, 0x00) {} + Processor(C02C, 0x2C, 0x00000000, 0x00) {} + Processor(C02D, 0x2D, 0x00000000, 0x00) {} + Processor(C02E, 0x2E, 0x00000000, 0x00) {} + Processor(C02F, 0x2F, 0x00000000, 0x00) {} + Alias (C000, CPU0) + Alias (C001, CPU1) + Alias (C002, CPU2) + Alias (C003, CPU3) + Alias (C004, CPU4) + Alias (C005, CPU5) + Alias (C006, CPU6) + Alias (C007, CPU7) + Alias (C008, CPU8) } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h */

1 0

Patch set updated for coreboot: 85f52c8 Fix messy code in ALIB
by Zheng Bao 12 Apr '12

12 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885 -gerrit commit 85f52c8e80831acb0de3898bdfad73081c091a49 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 12 11:28:11 2012 +0800 Fix messy code in ALIB The address return from PICK_ALIB is not protected by Coreboot. We need to use the "current", which is the correct way to allocate the ACPI table. Change-Id: I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 3 +-- src/mainboard/amd/inagua/acpi_tables.c | 6 ++---- src/mainboard/amd/persimmon/acpi_tables.c | 6 ++---- src/mainboard/amd/south_station/acpi_tables.c | 6 ++---- src/mainboard/amd/union_station/acpi_tables.c | 6 ++---- src/mainboard/asrock/e350m1/acpi_tables.c | 6 ++---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 3 +-- 7 files changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 741ba99..6fa9c6f 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index e521b4b..0588d04 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 00a08d2..789c11d 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7b97a92..e587334 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); }

1 0

Patch merged into coreboot/master: f8300b4 S3 code in vendorcode folder.
by gerrit＠coreboot.org 12 Apr '12

12 Apr '12

the following patch was just integrated into master: commit f8300b4e154e265ae2e281b61761428f487774b3 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:20:50 2012 +0800 S3 code in vendorcode folder. Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Apr 10 10:28:00 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Apr 12 00:16:34 2012, giving +2 See http://review.coreboot.org/622 for details. -gerrit

1 0

Patch merged into coreboot/master: a3650b6 Add Southbridge support for S3.
by gerrit＠coreboot.org 12 Apr '12

12 Apr '12

the following patch was just integrated into master: commit a3650b6cd356973f8b89c955533137be5cfa4b47 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:18:49 2012 +0800 Add Southbridge support for S3. 1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Apr 10 11:04:06 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Apr 12 00:14:06 2012, giving +2 See http://review.coreboot.org/621 for details. -gerrit

1 0

Patch merged into coreboot/master: 316c124 Unify IO APIC address specification
by gerrit＠coreboot.org 12 Apr '12

12 Apr '12

the following patch was just integrated into master: commit 316c124a98f563fe16721f37f98440b68491a249 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 18:54:37 2012 +0100 Unify IO APIC address specification Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sat Mar 10 09:29:32 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Apr 11 23:31:17 2012, giving +2 See http://review.coreboot.org/677 for details. -gerrit

1 0

Patch set updated for coreboot: 624c4fe Add support for aligned allocation
by Ronald G. Minnich 11 Apr '12

11 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/887 -gerrit commit 624c4fed563e3bc8e8fe900f1b8ad705a1700c37 Author: Ron Minnich <rminnich(a)gmail.com> Date: Wed Apr 11 10:30:15 2012 -0700 Add support for aligned allocation Add a memalign function and have malloc use it. Also, change the default alignment for malloc to u64-aligned. Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/include/stdlib.h | 1 + src/lib/malloc.c | 23 ++++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 5465c14..bd0ee30 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -12,6 +12,7 @@ #define MAX(a,b) ((a) > (b) ? (a) : (b)) #if !defined(__PRE_RAM__) +void *memalign(size_t boundary, size_t size); void *malloc(size_t size); void free(void *ptr); #endif diff --git a/src/lib/malloc.c b/src/lib/malloc.c index c10750d..2e700f7 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -11,29 +11,38 @@ extern unsigned char _heap, _eheap; static void *free_mem_ptr = &_heap; /* Start of heap */ static void *free_mem_end_ptr = &_eheap; /* End of heap */ -void *malloc(size_t size) +/* We don't restrict the boundary. This is firmware, + * you are supposed to know what you are doing. + */ +void *memalign(size_t boundary, size_t size) { void *p; - MALLOCDBG("%s Enter, size %ld, free_mem_ptr %p\n", __func__, size, free_mem_ptr); + MALLOCDBG("%s Enter, boundary %ld, size %ld, free_mem_ptr %p\n", + __func__, boundary, size, free_mem_ptr); /* Overzealous linker check */ if (free_mem_ptr <= 0) - die("Error! malloc: Free_mem_ptr <= 0"); + die("Error! memalign: Free_mem_ptr <= 0"); - free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, 4); + free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary); - p = (void *) free_mem_ptr; + p = free_mem_ptr; free_mem_ptr += size; if (free_mem_ptr >= free_mem_end_ptr) - die("Error! malloc: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); + die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); - MALLOCDBG("malloc %p\n", p); + MALLOCDBG("memalign %p\n", p); return p; } +void *malloc(size_t size) +{ + return memalign(sizeof(u64), size); +} + void free(void *where) { /* Don't care */

1 0

Patch merged into coreboot/master: 7f83ace Intel e7505: cleanups
by gerrit＠coreboot.org 11 Apr '12

11 Apr '12

the following patch was just integrated into master: commit 7f83ace920173381d4a6316a375b685735d424fa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 19:55:19 2012 +0300 Intel e7505: cleanups Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Apr 10 19:17:21 2012, giving +1 See http://review.coreboot.org/883 for details. -gerrit

1 0

Patch merged into coreboot/master: ddfe8df Intel e7505: renames only
by gerrit＠coreboot.org 11 Apr '12

11 Apr '12

the following patch was just integrated into master: commit ddfe8df0d5fa6466be8cb908aaaf5f08ad0293bc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 16:11:53 2012 +0300 Intel e7505: renames only Drop maybe-prefix in registers and tables. Have a name in place of PCI_DEV(x,y,z) to avoid confusion. Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Apr 10 15:30:35 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Apr 11 23:23:56 2012, giving +2 See http://review.coreboot.org/882 for details. -gerrit

1 0

New patch to review for coreboot: d08b499 Add support for aligned allocation
by Ronald G. Minnich 11 Apr '12

11 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/887 -gerrit commit d08b4997b8eb0d2677bc243650862a1cbda43105 Author: Ron Minnich <rminnich(a)gmail.com> Date: Wed Apr 11 10:30:15 2012 -0700 Add support for aligned allocation Add a memalign function and have malloc use it. Also, change the default alignment for malloc to u64-aligned. Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/include/stdlib.h | 1 + src/lib/malloc.c | 21 +++++++++++++++------ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 5465c14..bd0ee30 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -12,6 +12,7 @@ #define MAX(a,b) ((a) > (b) ? (a) : (b)) #if !defined(__PRE_RAM__) +void *memalign(size_t boundary, size_t size); void *malloc(size_t size); void free(void *ptr); #endif diff --git a/src/lib/malloc.c b/src/lib/malloc.c index c10750d..14219f6 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -11,29 +11,38 @@ extern unsigned char _heap, _eheap; static void *free_mem_ptr = &_heap; /* Start of heap */ static void *free_mem_end_ptr = &_eheap; /* End of heap */ -void *malloc(size_t size) +/* We don't restrict the boundary. This is firmware, + * you are supposed to know what you are doing. + */ +void *memalign(size_t boundary, size_t size) { void *p; - MALLOCDBG("%s Enter, size %ld, free_mem_ptr %p\n", __func__, size, free_mem_ptr); + MALLOCDBG("%s Enter, boundary %ld, size %ld, free_mem_ptr %p\n", + __func__, boundary, size, free_mem_ptr); /* Overzealous linker check */ if (free_mem_ptr <= 0) - die("Error! malloc: Free_mem_ptr <= 0"); + die("Error! memalign: Free_mem_ptr <= 0"); - free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, 4); + free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary); p = (void *) free_mem_ptr; free_mem_ptr += size; if (free_mem_ptr >= free_mem_end_ptr) - die("Error! malloc: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); + die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); - MALLOCDBG("malloc %p\n", p); + MALLOCDBG("memalign %p\n", p); return p; } +void *malloc(size_t size) +{ + return memalign(sizeof(u64), size); +} + void free(void *where) { /* Don't care */

1 0

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coreboot April 2012