coreboot April 2012

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459 discussions

Patch set updated for coreboot: 25fcc40 Convert AOpen DXPL Plus mainboard to CAR
by Kyösti Mälkki 11 Apr '12

11 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/886 -gerrit commit 25fcc40db87b15a123d70cf64297a3ed08b31979 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 11 12:19:03 2012 +0300 Convert AOpen DXPL Plus mainboard to CAR Tested on real hardware, mainboard with dual Xeon P4 HT CPUs requires cache-as-ram init code with AP SIPI protocol. Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI. Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/Kconfig | 18 ----------- src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 8 +++-- src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 2 +- src/mainboard/aopen/dxplplusu/devicetree.cb | 3 ++ src/mainboard/aopen/dxplplusu/dsdt.asl | 2 + src/mainboard/aopen/dxplplusu/romstage.c | 34 ++------------------- 6 files changed, 15 insertions(+), 52 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c3025d1..da03491 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select ROMCC - select HAVE_HARD_RESET # select HAVE_PIRQ_TABLE # select PIRQ_ROUTE select UDELAY_TSC @@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "DXPL Plus-U" -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - config IRQ_SLOT_COUNT int default 12 @@ -40,18 +30,10 @@ config BOARD_HAS_FADT bool default y -config LOGICAL_CPUS - bool - default n - config MAX_CPUS int default 4 -config MAX_PHYSICAL_CPUS - int - default 2 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 0effe93..463b6be 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -44,8 +44,8 @@ Name (PBRS, ResourceTemplate () /* Top Of Lowmemory to IOAPIC */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x02000000, 0xFEBFFFFF, - 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) + 0x00000000, 0x00000000, 0xFEBFFFFF, + 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic) }) @@ -54,11 +54,13 @@ Method (_CRS, 0, NotSerialized) /* Top Of Lowmemory to IOAPIC */ CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH) CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) And (\_SB.PCI0.TOLM, 0xF800, Local1) ShiftRight (Local1, 0x04, Local1) ShiftLeft (Local1, 0x14, MEML) - Subtract (0xFEC00000, MEML, LENM) + Subtract (IO_APIC_ADDR, 0x01, MEMH) + Subtract (IO_APIC_ADDR, MEML, LENM) Return (PBRS) } diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index bb8c321..a1a23f2 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -96,7 +96,7 @@ Device (ICH0) Name (MSBF, ResourceTemplate () { /* IOAPIC 0 */ - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,) IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index d465a82..94a38d7 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -24,6 +24,7 @@ chip northbridge/intel/e7505 device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 device lapic 0 on end + device lapic 6 on end end end @@ -79,6 +80,8 @@ chip northbridge/intel/e7505 end end device pci 1f.1 on end # IDE + register "ide0_enable" = "1" + register "ide1_enable" = "1" device pci 1f.3 on end # SMBus device pci 1f.5 on end # AC97 Audio device pci 1f.6 off end # AC97 Modem diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 31cfa88..095df06 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/ioapic.h> + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 573e0f1..73e445b 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -27,6 +27,8 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <cpu/x86/bist.h> +#include <spd.h> #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/early_smbus.c" @@ -35,13 +37,6 @@ #include "northbridge/intel/e7505/debug.c" #include "superio/smsc/lpc47m10x/early_serial.c" -#if !CONFIG_CACHE_AS_RAM -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#endif -#include "cpu/x86/bist.h" - -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) @@ -50,21 +45,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -/* Cache-As-Ram compiles for this board, but with the CPUs I have, - * it halts on boot while in Local Apic ID negotiation. - */ - -#if CONFIG_CACHE_AS_RAM -#define BOARD_MAIN(x) void main(x) -#define early_mtrr_init() do {} while (0) -#else -#define BOARD_MAIN(x) static void main(x) -#endif - #include "northbridge/intel/e7505/raminit.c" -// This function MUST appear last (ROMCC limitation) -BOARD_MAIN(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -75,12 +58,6 @@ BOARD_MAIN(unsigned long bist) }, }; - if (bist == 0) { - // Skip this if there was a built in self test failure - early_mtrr_init(); - enable_lapic(); - } - // Get the serial port running and print a welcome banner lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -94,8 +71,5 @@ BOARD_MAIN(unsigned long bist) sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } - // NOTE: ROMCC dies with an internal compiler error - // if the following line is removed. - print_debug("SDRAM is up.\r\n"); - + print_debug("SDRAM is up.\n"); }

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Re: [coreboot] ASUS M2V problems
by G 11 Apr '12

11 Apr '12

On Tue, Apr 10, 2012 at 5:26 PM, Marc Jones <marcj303(a)gmail.com> wrote: > On Tue, Apr 10, 2012 at 7:37 AM, G <tjmadwja(a)gmail.com> wrote: >> Hi, >> >> I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) >> motherboard, but so far I've had no luck. I'm currently trying to >> get the coreinfo payload running, as that seems like the simplest >> test case (I've also tried seabios, and failed). >> >> After flashing, when I boot, nothing happens. No beeps, the >> monitor remains in power-save mode, the keyboard doesn't respond >> to any keypresses (not even holding down several keys for a long >> time generates any beeps), no blinking status LEDs, nothing on >> the serial port. Nothing. >> >> I've tried with two different revisions, one from 2010-11-24 (the >> one that adds S3 support for ASUS M2V), and one from 2012-02-21 >> (all later revisions fail to compile with lots of different CBMEM >> problems). >> >> In the 2010-11-24 revision, I've had to add >> reg++; reg--; >> in src/northbridge/amd/amdk8/raminit_f_dqs.c:setup_mtrr_dqs() and >> regm3++; regm3--; >> in src/southbridge/via/vt8237r/vt8237_ctrl.c:vt8237_cfg() to get >> rid of warnings about unused variables. >> >> Flashing is done by simply running: >> ./flashrom -V -w coreboot.rom -c W39V040C >> >> Does anyone here have any idea what might be wrong? Anyone got a >> working .config, tips to use a certain known working revision, a >> know working version of flashrom (although flashing two different >> versions of ASUS's BIOS using flashrom works well, so I'm >> guessing neither flashrom nor my usage of it is to blame), a >> working coreboot.rom they can share, or anything else that might >> help me move forward? >> >> Using Debian unstable to build, if that's any help. >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > Hi, > > You will need to capture some output from coreboot to find where your > system is having problems. > > http://www.coreboot.org/FAQ#How_do_I_use_a_null-modem_cable_to_get_coreboot… Thanks for the reply, but unfortunately, as I wrote in my original mail, I get nothing on the serial port. When I boot the standard ASUS M2V BIOS, with a null-modem cable plugged in, then exactly as I power on the M2V system, minicom on the other end briefly (less than a second) switches from Offline to Online, and then back to Offline, and then the system continues to boot. Booting coreboot, minicom switches from Offline to Online exactly when I power on the M2V system, and then the minicom status on the other machine remains Online, but nothing ever arrives in the minicom terminal window, and nothing else happens (no beeps, not LEDs, nothing on the screen, just plain nothing). I have tested that the minicom connection over null-modem cable between my M2V computer and the other machine works after booting the standard ASUS M2V BIOS, although I then have HW flow control enabled, which is then disabled before trying to boot the coreboot BIOS. And yes, I have checked the serial port settings in the coreboot config and they are set to the correct values. So, anyone got a working .config and/or working coreboot.rom I can try? A known working coreboot revision I should download and compile? Or any other tips/pointers?

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New patch to review for coreboot: f95e0fe Convert AOpen DXPL Plus mainboard to CAR
by Kyösti Mälkki 11 Apr '12

11 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/886 -gerrit commit f95e0fe6634b6693ca2ea37b4383236a0b017f69 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 21:18:36 2012 +0300 Convert AOpen DXPL Plus mainboard to CAR Mainboard with hyper-threading P4 CPUs, requires a cache-as-ram init code with AP SIPI protocol. Also clean-up Kconfig and some ACPI. Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/Kconfig | 18 ----------- src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 8 +++-- src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 2 +- src/mainboard/aopen/dxplplusu/devicetree.cb | 1 + src/mainboard/aopen/dxplplusu/dsdt.asl | 2 + src/mainboard/aopen/dxplplusu/romstage.c | 34 ++------------------- 6 files changed, 13 insertions(+), 52 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c3025d1..da03491 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select ROMCC - select HAVE_HARD_RESET # select HAVE_PIRQ_TABLE # select PIRQ_ROUTE select UDELAY_TSC @@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "DXPL Plus-U" -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - config IRQ_SLOT_COUNT int default 12 @@ -40,18 +30,10 @@ config BOARD_HAS_FADT bool default y -config LOGICAL_CPUS - bool - default n - config MAX_CPUS int default 4 -config MAX_PHYSICAL_CPUS - int - default 2 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 0effe93..463b6be 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -44,8 +44,8 @@ Name (PBRS, ResourceTemplate () /* Top Of Lowmemory to IOAPIC */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x02000000, 0xFEBFFFFF, - 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) + 0x00000000, 0x00000000, 0xFEBFFFFF, + 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic) }) @@ -54,11 +54,13 @@ Method (_CRS, 0, NotSerialized) /* Top Of Lowmemory to IOAPIC */ CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH) CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) And (\_SB.PCI0.TOLM, 0xF800, Local1) ShiftRight (Local1, 0x04, Local1) ShiftLeft (Local1, 0x14, MEML) - Subtract (0xFEC00000, MEML, LENM) + Subtract (IO_APIC_ADDR, 0x01, MEMH) + Subtract (IO_APIC_ADDR, MEML, LENM) Return (PBRS) } diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index bb8c321..a1a23f2 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -96,7 +96,7 @@ Device (ICH0) Name (MSBF, ResourceTemplate () { /* IOAPIC 0 */ - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,) IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index d465a82..42c1571 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -24,6 +24,7 @@ chip northbridge/intel/e7505 device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 device lapic 0 on end + device lapic 6 on end end end diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 31cfa88..095df06 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/ioapic.h> + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 573e0f1..73e445b 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -27,6 +27,8 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <cpu/x86/bist.h> +#include <spd.h> #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/early_smbus.c" @@ -35,13 +37,6 @@ #include "northbridge/intel/e7505/debug.c" #include "superio/smsc/lpc47m10x/early_serial.c" -#if !CONFIG_CACHE_AS_RAM -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#endif -#include "cpu/x86/bist.h" - -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) @@ -50,21 +45,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -/* Cache-As-Ram compiles for this board, but with the CPUs I have, - * it halts on boot while in Local Apic ID negotiation. - */ - -#if CONFIG_CACHE_AS_RAM -#define BOARD_MAIN(x) void main(x) -#define early_mtrr_init() do {} while (0) -#else -#define BOARD_MAIN(x) static void main(x) -#endif - #include "northbridge/intel/e7505/raminit.c" -// This function MUST appear last (ROMCC limitation) -BOARD_MAIN(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -75,12 +58,6 @@ BOARD_MAIN(unsigned long bist) }, }; - if (bist == 0) { - // Skip this if there was a built in self test failure - early_mtrr_init(); - enable_lapic(); - } - // Get the serial port running and print a welcome banner lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -94,8 +71,5 @@ BOARD_MAIN(unsigned long bist) sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } - // NOTE: ROMCC dies with an internal compiler error - // if the following line is removed. - print_debug("SDRAM is up.\r\n"); - + print_debug("SDRAM is up.\n"); }

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New patch to review for coreboot: a9a03db Fix messy code in ALIB
by Zheng Bao 11 Apr '12

11 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885 -gerrit commit a9a03db0d3018a9f5b79fb942dccd29438eaf7f4 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 11 15:41:17 2012 +0800 Fix messy code in ALIB The address return from PICK_ALIB is not protected by Coreboot. We need to use the "current", which is the correct way to allocate the ACPI table. Change-Id: I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 3 +-- src/mainboard/amd/inagua/acpi_tables.c | 6 ++---- src/mainboard/amd/persimmon/acpi_tables.c | 6 ++---- src/mainboard/amd/south_station/acpi_tables.c | 6 ++---- src/mainboard/amd/union_station/acpi_tables.c | 6 ++---- src/mainboard/asrock/e350m1/acpi_tables.c | 6 ++---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 3 +-- 7 files changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 741ba99..6fa9c6f 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index e521b4b..0588d04 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 00a08d2..789c11d 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7b97a92..e587334 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); }

1 0

New patch to review for coreboot: e520f75 Leverage the Pstate table created by AGESA.
by Zheng Bao 11 Apr '12

11 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/884 -gerrit commit e520f750d05434957cdcc150c801006af5081fa9 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 11 14:24:30 2012 +0800 Leverage the Pstate table created by AGESA. The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME and n starts from 0. The dsdt should be aligned with that. This feature has only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/dsdt.asl | 48 ++++++++--- src/mainboard/amd/inagua/acpi_tables.c | 8 +- src/mainboard/amd/inagua/dsdt.asl | 24 ++++-- src/mainboard/amd/persimmon/acpi_tables.c | 8 +- src/mainboard/amd/persimmon/dsdt.asl | 24 ++++-- src/mainboard/amd/south_station/acpi_tables.c | 12 ++-- src/mainboard/amd/south_station/dsdt.asl | 24 ++++-- src/mainboard/amd/torpedo/dsdt.asl | 18 ++--- src/mainboard/amd/union_station/acpi_tables.c | 12 ++-- src/mainboard/amd/union_station/dsdt.asl | 24 ++++-- src/mainboard/asrock/e350m1/acpi_tables.c | 12 ++-- src/mainboard/asrock/e350m1/dsdt.asl | 24 ++++-- src/mainboard/supermicro/h8qgi/acpi_tables.c | 8 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 114 ++++++++++++------------ 15 files changed, 222 insertions(+), 146 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index ee00e81..741ba99 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 1cbb05e..501ec78 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -51,37 +51,61 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x0 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } + Processor( + C004, /* name space name */ + 4, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C005, /* name space name */ + 5, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C006, /* name space name */ + 6, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C007, /* name space name */ + 7, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h. */ diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 8f47591..e521b4b 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 361adbb..7708676 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 9526fea..00a08d2 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index b480c33..bd9ce74 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 7f03a43..b18bcb2 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index a8a731d..758fba5 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -51,36 +51,32 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index fb2cfe8..7e49fd4 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 97533c1..c2ea1fb 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7314283..7b97a92 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 137a90d..39ad9d8 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -65,69 +65,69 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - P000, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0x00, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { //#include "acpi/cpstate.asl" } - Processor(P001, 0x01, 0x00000000, 0x00) {} - Processor(P002, 0x02, 0x00000000, 0x00) {} - Processor(P003, 0x03, 0x00000000, 0x00) {} - Processor(P004, 0x04, 0x00000000, 0x00) {} - Processor(P005, 0x05, 0x00000000, 0x00) {} - Processor(P006, 0x06, 0x00000000, 0x00) {} - Processor(P007, 0x07, 0x00000000, 0x00) {} - Processor(P008, 0x08, 0x00000000, 0x00) {} - Processor(P009, 0x09, 0x00000000, 0x00) {} - Processor(P00A, 0x0A, 0x00000000, 0x00) {} - Processor(P00B, 0x0B, 0x00000000, 0x00) {} - Processor(P00C, 0x0C, 0x00000000, 0x00) {} - Processor(P00D, 0x0D, 0x00000000, 0x00) {} - Processor(P00E, 0x0E, 0x00000000, 0x00) {} - Processor(P00F, 0x0F, 0x00000000, 0x00) {} - Processor(P010, 0x10, 0x00000000, 0x00) {} - Processor(P011, 0x11, 0x00000000, 0x00) {} - Processor(P012, 0x12, 0x00000000, 0x00) {} - Processor(P013, 0x13, 0x00000000, 0x00) {} - Processor(P014, 0x14, 0x00000000, 0x00) {} - Processor(P015, 0x15, 0x00000000, 0x00) {} - Processor(P016, 0x16, 0x00000000, 0x00) {} - Processor(P017, 0x17, 0x00000000, 0x00) {} - Processor(P018, 0x18, 0x00000000, 0x00) {} - Processor(P019, 0x19, 0x00000000, 0x00) {} - Processor(P01A, 0x1A, 0x00000000, 0x00) {} - Processor(P01B, 0x1B, 0x00000000, 0x00) {} - Processor(P01C, 0x1C, 0x00000000, 0x00) {} - Processor(P01D, 0x1D, 0x00000000, 0x00) {} - Processor(P01E, 0x1E, 0x00000000, 0x00) {} - Processor(P01F, 0x1F, 0x00000000, 0x00) {} - Processor(P020, 0x20, 0x00000000, 0x00) {} - Processor(P021, 0x21, 0x00000000, 0x00) {} - Processor(P022, 0x22, 0x00000000, 0x00) {} - Processor(P023, 0x23, 0x00000000, 0x00) {} - Processor(P024, 0x24, 0x00000000, 0x00) {} - Processor(P025, 0x25, 0x00000000, 0x00) {} - Processor(P026, 0x26, 0x00000000, 0x00) {} - Processor(P027, 0x27, 0x00000000, 0x00) {} - Processor(P028, 0x28, 0x00000000, 0x00) {} - Processor(P029, 0x29, 0x00000000, 0x00) {} - Processor(P02A, 0x2A, 0x00000000, 0x00) {} - Processor(P02B, 0x2B, 0x00000000, 0x00) {} - Processor(P02C, 0x2C, 0x00000000, 0x00) {} - Processor(P02D, 0x2D, 0x00000000, 0x00) {} - Processor(P02E, 0x2E, 0x00000000, 0x00) {} - Processor(P02F, 0x2F, 0x00000000, 0x00) {} - Alias (P000, CPU0) - Alias (P001, CPU1) - Alias (P002, CPU2) - Alias (P003, CPU3) - Alias (P004, CPU4) - Alias (P005, CPU5) - Alias (P006, CPU6) - Alias (P007, CPU7) - Alias (P008, CPU8) + Processor(C001, 0x01, 0x00000000, 0x00) {} + Processor(C002, 0x02, 0x00000000, 0x00) {} + Processor(C003, 0x03, 0x00000000, 0x00) {} + Processor(C004, 0x04, 0x00000000, 0x00) {} + Processor(C005, 0x05, 0x00000000, 0x00) {} + Processor(C006, 0x06, 0x00000000, 0x00) {} + Processor(C007, 0x07, 0x00000000, 0x00) {} + Processor(C008, 0x08, 0x00000000, 0x00) {} + Processor(C009, 0x09, 0x00000000, 0x00) {} + Processor(C00A, 0x0A, 0x00000000, 0x00) {} + Processor(C00B, 0x0B, 0x00000000, 0x00) {} + Processor(C00C, 0x0C, 0x00000000, 0x00) {} + Processor(C00D, 0x0D, 0x00000000, 0x00) {} + Processor(C00E, 0x0E, 0x00000000, 0x00) {} + Processor(C00F, 0x0F, 0x00000000, 0x00) {} + Processor(C010, 0x10, 0x00000000, 0x00) {} + Processor(C011, 0x11, 0x00000000, 0x00) {} + Processor(C012, 0x12, 0x00000000, 0x00) {} + Processor(C013, 0x13, 0x00000000, 0x00) {} + Processor(C014, 0x14, 0x00000000, 0x00) {} + Processor(C015, 0x15, 0x00000000, 0x00) {} + Processor(C016, 0x16, 0x00000000, 0x00) {} + Processor(C017, 0x17, 0x00000000, 0x00) {} + Processor(C018, 0x18, 0x00000000, 0x00) {} + Processor(C019, 0x19, 0x00000000, 0x00) {} + Processor(C01A, 0x1A, 0x00000000, 0x00) {} + Processor(C01B, 0x1B, 0x00000000, 0x00) {} + Processor(C01C, 0x1C, 0x00000000, 0x00) {} + Processor(C01D, 0x1D, 0x00000000, 0x00) {} + Processor(C01E, 0x1E, 0x00000000, 0x00) {} + Processor(C01F, 0x1F, 0x00000000, 0x00) {} + Processor(C020, 0x20, 0x00000000, 0x00) {} + Processor(C021, 0x21, 0x00000000, 0x00) {} + Processor(C022, 0x22, 0x00000000, 0x00) {} + Processor(C023, 0x23, 0x00000000, 0x00) {} + Processor(C024, 0x24, 0x00000000, 0x00) {} + Processor(C025, 0x25, 0x00000000, 0x00) {} + Processor(C026, 0x26, 0x00000000, 0x00) {} + Processor(C027, 0x27, 0x00000000, 0x00) {} + Processor(C028, 0x28, 0x00000000, 0x00) {} + Processor(C029, 0x29, 0x00000000, 0x00) {} + Processor(C02A, 0x2A, 0x00000000, 0x00) {} + Processor(C02B, 0x2B, 0x00000000, 0x00) {} + Processor(C02C, 0x2C, 0x00000000, 0x00) {} + Processor(C02D, 0x2D, 0x00000000, 0x00) {} + Processor(C02E, 0x2E, 0x00000000, 0x00) {} + Processor(C02F, 0x2F, 0x00000000, 0x00) {} + Alias (C000, CPU0) + Alias (C001, CPU1) + Alias (C002, CPU2) + Alias (C003, CPU3) + Alias (C004, CPU4) + Alias (C005, CPU5) + Alias (C006, CPU6) + Alias (C007, CPU7) + Alias (C008, CPU8) } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h */

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[Honest Request] Use Coreboot as BIOS for Server and Storage motherboard
by Kiran Patil 11 Apr '12

11 Apr '12

Kudos OCP experts, I am resending this mail, since earlier mail is rejected due to size issues. To make this project true "Open Compute Project", this Coreboot BIOS software on Motherboard is essential. I request you to consider using Coreboot (www.coreboot.org) as BIOS for Server and Storage motherboards used in Open Compute Project. Thanks, Kiran.

1 0

Patch set updated for coreboot: 7f83ace Intel e7505: cleanups
by Kyösti Mälkki 10 Apr '12

10 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/883 -gerrit commit 7f83ace920173381d4a6316a375b685735d424fa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 19:55:19 2012 +0300 Intel e7505: cleanups Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/romstage.c | 2 - src/northbridge/intel/e7505/raminit.c | 89 +++++++++++++++-------------- src/northbridge/intel/e7505/reset_test.c | 18 ------ 3 files changed, 46 insertions(+), 63 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 92ce896..573e0f1 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -62,8 +62,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif #include "northbridge/intel/e7505/raminit.c" -#include "northbridge/intel/e7505/reset_test.c" -#include "lib/generic_sdram.c" // This function MUST appear last (ROMCC limitation) BOARD_MAIN(unsigned long bist) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 21ffba2..29eb42b 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -464,27 +464,25 @@ static const uint32_t pull_updown_offset_table[] = { Delay functions: -----------------------------------------------------------------------------*/ +/* Estimate that SLOW_DOWN_IO takes about 1 us */ #define SLOW_DOWN_IO inb(0x80) -//#define SLOW_DOWN_IO udelay(40); - - /* Estimate that SLOW_DOWN_IO takes about 50&76us */ - /* delay for 200us */ - -#if 1 -static void do_delay(void) +static inline void local_udelay(int i) { - int i; - for (i = 0; i < 16; i++) { + while (i--) { SLOW_DOWN_IO; } } -#define DO_DELAY do_delay() -#else -#define DO_DELAY \ - udelay(200) -#endif +static inline void local_mdelay(int i) +{ + i *= 1000; + while (i--) { + SLOW_DOWN_IO; + } +} +/* delay for 200us */ +#define DO_DELAY local_udelay(200) #define EXTRA_DELAY DO_DELAY /*----------------------------------------------------------------------------- @@ -913,8 +911,10 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. - if (command == RAM_COMMAND_NORMAL) + if (command == RAM_COMMAND_NORMAL) { + EXTRA_DELAY; return; + } // NOTE: for mode select commands, some of the location address bits are part of the command // Map JEDEC mode bits to E7505 @@ -949,7 +949,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dimm_start_64M_multiple = dimm_end_64M_multiple; } } - + EXTRA_DELAY; } /** @@ -1169,6 +1169,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller * If we're configured to use ECC, initialize the SDRAM and clear the E7501's * ECC error flags. */ +#ifdef __ROMCC__ static void initialize_ecc(void) { uint32_t dram_controller_mode; @@ -1202,6 +1203,7 @@ static void initialize_ecc(void) } } +#endif /** * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# @@ -1898,12 +1900,10 @@ Public interface: * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up * and running. * - * @param controllers Not used. * @param ctrl PCI addresses of memory controller functions, and SMBus * addresses of DIMM slots on the mainboard. */ -static void sdram_enable(int controllers, - const struct mem_controller *ctrl) +static void sdram_enable(const struct mem_controller *ctrl) { uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); uint32_t dram_controller_mode; @@ -1921,12 +1921,10 @@ static void sdram_enable(int controllers, /* 3. Apply NOP */ RAM_DEBUG_MESSAGE("Ram Enable 3\n"); do_ram_command(RAM_COMMAND_NOP, 0); - EXTRA_DELAY; /* 4 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 4\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* wait until the all banks idle state... */ /* 5. Issue EMRS to enable DLL */ @@ -1934,7 +1932,6 @@ static void sdram_enable(int controllers, do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); - EXTRA_DELAY; /* 6. Reset DLL */ RAM_DEBUG_MESSAGE("Ram Enable 6\n"); @@ -1949,33 +1946,17 @@ static void sdram_enable(int controllers, /* 7 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 7\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\n"); - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - /* And for good luck 6 more CBRs */ - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; + RAM_DEBUG_MESSAGE("Ram Enable 8\n"); + int i; + for(i=0; i<8; i++) + do_ram_command(RAM_COMMAND_CBR, 0); /* 9 mode register set */ RAM_DEBUG_MESSAGE("Ram Enable 9\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); - EXTRA_DELAY; /* 10 DDR Receive FIFO RE-Sync */ RAM_DEBUG_MESSAGE("Ram Enable 10\n"); @@ -1985,7 +1966,6 @@ static void sdram_enable(int controllers, /* 11 normal operation */ RAM_DEBUG_MESSAGE("Ram Enable 11\n"); do_ram_command(RAM_COMMAND_NORMAL, 0); - EXTRA_DELAY; // Reconfigure the row boundaries and Top of Low Memory // to match the true size of the DIMMs @@ -1996,7 +1976,11 @@ static void sdram_enable(int controllers, dram_controller_mode |= (1 << 29); pci_write_config32(MCHDEV, DRC, dram_controller_mode); EXTRA_DELAY; + +#ifdef __ROMCC__ + /* Problems with cache-as-ram, disable for now */ initialize_ecc(); +#endif dram_controller_mode = pci_read_config32(MCHDEV, DRC); /* FCS_EN */ dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit @@ -2069,3 +2053,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ram_handle_d060_2(); } +/** + * + * + */ +void sdram_initialize(int controllers, const struct mem_controller *memctrl) +{ + RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); + DUMPNORTH(); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(memctrl); +} + +static int bios_reset_detected(void) +{ + uint32_t dword = pci_read_config32(MCHDEV, DRC); + return !!(dword & DRC_DONE); +} diff --git a/src/northbridge/intel/e7505/reset_test.c b/src/northbridge/intel/e7505/reset_test.c deleted file mode 100644 index 1c0dad5..0000000 --- a/src/northbridge/intel/e7505/reset_test.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - /* If I have already booted once skip a bunch of initialization */ - /* To see if I have already booted I check to see if memory - * has been enabled. - */ -static int bios_reset_detected(void) { - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -}

1 0

New patch to review for coreboot: 3fdf815 Intel e7505: cleanups
by Kyösti Mälkki 10 Apr '12

10 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/883 -gerrit commit 3fdf815578294f606fe3e3d8918c56f8726ec135 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 18:46:14 2012 +0300 Intel e7505: cleanups Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/romstage.c | 2 - src/northbridge/intel/e7505/raminit.c | 87 +++++++++++++++--------------- src/northbridge/intel/e7505/reset_test.c | 18 ------ 3 files changed, 44 insertions(+), 63 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 92ce896..573e0f1 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -62,8 +62,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif #include "northbridge/intel/e7505/raminit.c" -#include "northbridge/intel/e7505/reset_test.c" -#include "lib/generic_sdram.c" // This function MUST appear last (ROMCC limitation) BOARD_MAIN(unsigned long bist) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 21ffba2..9eaaa92 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -464,27 +464,25 @@ static const uint32_t pull_updown_offset_table[] = { Delay functions: -----------------------------------------------------------------------------*/ +/* Estimate that SLOW_DOWN_IO takes about 1 us */ #define SLOW_DOWN_IO inb(0x80) -//#define SLOW_DOWN_IO udelay(40); - - /* Estimate that SLOW_DOWN_IO takes about 50&76us */ - /* delay for 200us */ - -#if 1 -static void do_delay(void) +static inline void local_udelay(int i) { - int i; - for (i = 0; i < 16; i++) { + while (i--) { SLOW_DOWN_IO; } } -#define DO_DELAY do_delay() -#else -#define DO_DELAY \ - udelay(200) -#endif +static inline void local_mdelay(int i) +{ + i *= 1000; + while (i--) { + SLOW_DOWN_IO; + } +} +/* delay for 200us */ +#define DO_DELAY local_udelay(200) #define EXTRA_DELAY DO_DELAY /*----------------------------------------------------------------------------- @@ -913,8 +911,10 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. - if (command == RAM_COMMAND_NORMAL) + if (command == RAM_COMMAND_NORMAL) { + EXTRA_DELAY; return; + } // NOTE: for mode select commands, some of the location address bits are part of the command // Map JEDEC mode bits to E7505 @@ -949,7 +949,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dimm_start_64M_multiple = dimm_end_64M_multiple; } } - + EXTRA_DELAY; } /** @@ -1898,12 +1898,10 @@ Public interface: * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up * and running. * - * @param controllers Not used. * @param ctrl PCI addresses of memory controller functions, and SMBus * addresses of DIMM slots on the mainboard. */ -static void sdram_enable(int controllers, - const struct mem_controller *ctrl) +static void sdram_enable(const struct mem_controller *ctrl) { uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); uint32_t dram_controller_mode; @@ -1921,12 +1919,10 @@ static void sdram_enable(int controllers, /* 3. Apply NOP */ RAM_DEBUG_MESSAGE("Ram Enable 3\n"); do_ram_command(RAM_COMMAND_NOP, 0); - EXTRA_DELAY; /* 4 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 4\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* wait until the all banks idle state... */ /* 5. Issue EMRS to enable DLL */ @@ -1934,7 +1930,6 @@ static void sdram_enable(int controllers, do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); - EXTRA_DELAY; /* 6. Reset DLL */ RAM_DEBUG_MESSAGE("Ram Enable 6\n"); @@ -1949,33 +1944,17 @@ static void sdram_enable(int controllers, /* 7 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 7\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\n"); - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - /* And for good luck 6 more CBRs */ - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; + RAM_DEBUG_MESSAGE("Ram Enable 8\n"); + int i; + for(i=0; i<8; i++) + do_ram_command(RAM_COMMAND_CBR, 0); /* 9 mode register set */ RAM_DEBUG_MESSAGE("Ram Enable 9\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); - EXTRA_DELAY; /* 10 DDR Receive FIFO RE-Sync */ RAM_DEBUG_MESSAGE("Ram Enable 10\n"); @@ -1985,7 +1964,6 @@ static void sdram_enable(int controllers, /* 11 normal operation */ RAM_DEBUG_MESSAGE("Ram Enable 11\n"); do_ram_command(RAM_COMMAND_NORMAL, 0); - EXTRA_DELAY; // Reconfigure the row boundaries and Top of Low Memory // to match the true size of the DIMMs @@ -1996,7 +1974,11 @@ static void sdram_enable(int controllers, dram_controller_mode |= (1 << 29); pci_write_config32(MCHDEV, DRC, dram_controller_mode); EXTRA_DELAY; + +#if 0 + /* Problems with cache-as-ram, disable for now */ initialize_ecc(); +#endif dram_controller_mode = pci_read_config32(MCHDEV, DRC); /* FCS_EN */ dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit @@ -2069,3 +2051,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ram_handle_d060_2(); } +/** + * + * + */ +void sdram_initialize(int controllers, const struct mem_controller *memctrl) +{ + RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); + DUMPNORTH(); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(memctrl); +} + +static int bios_reset_detected(void) +{ + uint32_t dword = pci_read_config32(MCHDEV, DRC); + return !!(dword & DRC_DONE); +} diff --git a/src/northbridge/intel/e7505/reset_test.c b/src/northbridge/intel/e7505/reset_test.c deleted file mode 100644 index 1c0dad5..0000000 --- a/src/northbridge/intel/e7505/reset_test.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - /* If I have already booted once skip a bunch of initialization */ - /* To see if I have already booted I check to see if memory - * has been enabled. - */ -static int bios_reset_detected(void) { - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -}

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Re: [coreboot] Patch merged into coreboot/master: c35c461 Invalidate cache before first jump
by Bao, Zheng 10 Apr '12

10 Apr '12

Hi, It is unstable. In most cases, it hangs at this wbinvd. Once it pass that instruction, it will hang at when AP cores are launched. Joe > -----Original Message----- > From: Marc Jones [mailto:marcj303@gmail.com] > Sent: Friday, April 06, 2012 11:27 PM > To: Bao, Zheng > Cc: coreboot(a)coreboot.org; Marc Jones > Subject: Re: [coreboot] Patch merged into coreboot/master: c35c461 > Invalidate cache before first jump > > Can you be more descriptive to how it fails? Does it hang on that > instruction? > > Marc > > > On Fri, Apr 6, 2012 at 5:38 AM, Bao, Zheng <Zheng.Bao(a)amd.com> wrote: > > Actually, it hurts my board. > > AMD trinity fam15 + Hudson. > > > > Zheng > > > >> -----Original Message----- > >> From: coreboot-bounces(a)coreboot.org [mailto:coreboot- > >> bounces(a)coreboot.org] On Behalf Of gerrit(a)coreboot.org > >> Sent: Friday, April 06, 2012 5:03 AM > >> To: coreboot(a)coreboot.org > >> Subject: [coreboot] Patch merged into coreboot/master: c35c461 > >> Invalidate cache before first jump > >> > >> the following patch was just integrated into master: > >> commit c35c461bb2146ab949062f22e265406deef178d2 > >> Author: Stefan Reinauer <reinauer(a)chromium.org> > >> Date: ? Tue Apr 3 16:09:46 2012 -0700 > >> > >> ? ? Invalidate cache before first jump > >> > >> ? ? Some CPUs (Sandybridge) seem to require this, and it does not > hurt > >> ? ? on other CPUs. > >> > >> ? ? Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d > >> ? ? Signed-off-by: Stefan Reinauer <reinauer(a)google.com> > >> > >> Build-Tested: build bot (Jenkins) at Thu Apr ?5 23:02:43 2012, > giving > >> +1 > >> See http://review.coreboot.org/869 for details. > >> > >> -gerrit > >> > >> -- > >> coreboot mailing list: coreboot(a)coreboot.org > >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > http://se-eng.com

3 3

ASUS M2V problems
by G 10 Apr '12

10 Apr '12

Hi, I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) motherboard, but so far I've had no luck. I'm currently trying to get the coreinfo payload running, as that seems like the simplest test case (I've also tried seabios, and failed). After flashing, when I boot, nothing happens. No beeps, the monitor remains in power-save mode, the keyboard doesn't respond to any keypresses (not even holding down several keys for a long time generates any beeps), no blinking status LEDs, nothing on the serial port. Nothing. I've tried with two different revisions, one from 2010-11-24 (the one that adds S3 support for ASUS M2V), and one from 2012-02-21 (all later revisions fail to compile with lots of different CBMEM problems). In the 2010-11-24 revision, I've had to add reg++; reg--; in src/northbridge/amd/amdk8/raminit_f_dqs.c:setup_mtrr_dqs() and regm3++; regm3--; in src/southbridge/via/vt8237r/vt8237_ctrl.c:vt8237_cfg() to get rid of warnings about unused variables. Flashing is done by simply running: ./flashrom -V -w coreboot.rom -c W39V040C Does anyone here have any idea what might be wrong? Anyone got a working .config, tips to use a certain known working revision, a know working version of flashrom (although flashing two different versions of ASUS's BIOS using flashrom works well, so I'm guessing neither flashrom nor my usage of it is to blame), a working coreboot.rom they can share, or anything else that might help me move forward? Using Debian unstable to build, if that's any help.

1 0

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coreboot April 2012