coreboot April 2012

coreboot@coreboot.org

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459 discussions

Patch merged into coreboot/master: 65aff4f hexdump: fix compiler warning
by gerrit＠coreboot.org 07 Apr '12

07 Apr '12

the following patch was just integrated into master: commit 65aff4f8d15fec36023e22a25a1f48b331a9353e Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 7 16:28:26 2012 +0530 hexdump: fix compiler warning Fixed "warning: format not a string literal and no format arguments" Change-Id: If752a37f268c90f782c6e831e5477ea804e48026 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Apr 7 13:17:23 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sat Apr 7 19:57:41 2012, giving +2 See http://review.coreboot.org/878 for details. -gerrit

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New patch to review for coreboot: ae30789 drivers/i2c: Add description in Kconfig file
by Vikram Narayanan 07 Apr '12

07 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/879 -gerrit commit ae307898e74c38a5a065b0a1983d69084d00ccfd Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 7 16:47:06 2012 +0530 drivers/i2c: Add description in Kconfig file Change-Id: Ibf44a0e1c44bae11febf7cfc503582e4a1033c02 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/drivers/i2c/adm1026/Kconfig | 5 ++++- src/drivers/i2c/adm1027/Kconfig | 5 ++++- src/drivers/i2c/adt7463/Kconfig | 5 ++++- src/drivers/i2c/i2cmux/Kconfig | 5 ++++- src/drivers/i2c/i2cmux2/Kconfig | 5 ++++- src/drivers/i2c/lm63/Kconfig | 5 ++++- src/drivers/i2c/w83795/Kconfig | 5 ++++- 7 files changed, 28 insertions(+), 7 deletions(-) diff --git a/src/drivers/i2c/adm1026/Kconfig b/src/drivers/i2c/adm1026/Kconfig index 8168b29..141766c 100644 --- a/src/drivers/i2c/adm1026/Kconfig +++ b/src/drivers/i2c/adm1026/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADM1026 - bool + bool "ADM1026" + default n + help + Support for ADM1026-Thermal System Management Fan Controller IC diff --git a/src/drivers/i2c/adm1027/Kconfig b/src/drivers/i2c/adm1027/Kconfig index c135726..f77fdd8 100644 --- a/src/drivers/i2c/adm1027/Kconfig +++ b/src/drivers/i2c/adm1027/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADM1027 - bool + bool "ADM1027" + default n + help + Support for ADM1027-Remote Thermal Controller and Voltage Monitor diff --git a/src/drivers/i2c/adt7463/Kconfig b/src/drivers/i2c/adt7463/Kconfig index b942341..70d6a25 100644 --- a/src/drivers/i2c/adt7463/Kconfig +++ b/src/drivers/i2c/adt7463/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADT7463 - bool + bool "ADT7463" + default n + help + Support for ADT7463-Remote Thermal Controller and Voltage Monitor diff --git a/src/drivers/i2c/i2cmux/Kconfig b/src/drivers/i2c/i2cmux/Kconfig index 57bb278..4a08c77 100644 --- a/src/drivers/i2c/i2cmux/Kconfig +++ b/src/drivers/i2c/i2cmux/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_I2CMUX - bool + bool "PCA9556 SMBus mux" + default n + help + Support for PCA9556 SMBus IC diff --git a/src/drivers/i2c/i2cmux2/Kconfig b/src/drivers/i2c/i2cmux2/Kconfig index 0213e55..a37a80e 100644 --- a/src/drivers/i2c/i2cmux2/Kconfig +++ b/src/drivers/i2c/i2cmux2/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_I2CMUX2 - bool + bool "PCA9554 SMBus mux" + default n + help + Support for PCA9554 SMBus IC diff --git a/src/drivers/i2c/lm63/Kconfig b/src/drivers/i2c/lm63/Kconfig index 120ee0d..433fe37 100644 --- a/src/drivers/i2c/lm63/Kconfig +++ b/src/drivers/i2c/lm63/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_LM63 - bool + bool "LM63" + default n + help + Support for National Semiconductor LM63 diff --git a/src/drivers/i2c/w83795/Kconfig b/src/drivers/i2c/w83795/Kconfig index 80856e2..bdaf2b6 100644 --- a/src/drivers/i2c/w83795/Kconfig +++ b/src/drivers/i2c/w83795/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_W83795 - bool + bool "W83795" + default n + help + Support for Nuvoton W83795G

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New patch to review for coreboot: 65aff4f hexdump: fix compiler warning
by Vikram Narayanan 07 Apr '12

07 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/878 -gerrit commit 65aff4f8d15fec36023e22a25a1f48b331a9353e Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 7 16:28:26 2012 +0530 hexdump: fix compiler warning Fixed "warning: format not a string literal and no format arguments" Change-Id: If752a37f268c90f782c6e831e5477ea804e48026 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- util/nvramtool/hexdump.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/util/nvramtool/hexdump.c b/util/nvramtool/hexdump.c index 4d13963..e6d9faf 100644 --- a/util/nvramtool/hexdump.c +++ b/util/nvramtool/hexdump.c @@ -83,10 +83,10 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, bytes_left >= format->bytes_per_line; bytes_left -= format->bytes_per_line) { /* print start address for current line */ - fprintf(outfile, format->indent); + fprintf(outfile, "%s", format->indent); addrprint(outfile, addrprint_start + index, format->addrprint_width); - fprintf(outfile, format->sep1); + fprintf(outfile, "%s", format->sep1); /* display the bytes in hex */ for (i = 0;;) { @@ -95,11 +95,11 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, if (++i >= format->bytes_per_line) break; - fprintf(outfile, format->sep2); + fprintf(outfile, "%s", format->sep2); } index -= format->bytes_per_line; - fprintf(outfile, format->sep3); + fprintf(outfile, "%s", format->sep3); /* display the bytes as characters */ for (i = 0; i < format->bytes_per_line; i++, index++) @@ -112,14 +112,14 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, return; /* print start address for last line */ - fprintf(outfile, format->indent); + fprintf(outfile, "%s", format->indent); addrprint(outfile, addrprint_start + index, format->addrprint_width); - fprintf(outfile, format->sep1); + fprintf(outfile, "%s", format->sep1); /* display bytes for last line in hex */ for (i = 0; i < bytes_left; i++) { fprintf(outfile, "%02x", p[index++]); - fprintf(outfile, format->sep2); + fprintf(outfile, "%s", format->sep2); } index -= bytes_left; @@ -131,10 +131,10 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, if (++i >= format->bytes_per_line) break; - fprintf(outfile, format->sep2); + fprintf(outfile, "%s", format->sep2); } - fprintf(outfile, format->sep3); + fprintf(outfile, "%s", format->sep3); /* display bytes for last line as characters */ for (i = 0; i < bytes_left; i++)

1 0

Patch set updated for coreboot: 1c810f1 Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer 07 Apr '12

07 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871 -gerrit commit 1c810f17a1a3e9c5433e9eee4a18175d64698be2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - drop AMD CPU model 14XXX config variable use. Those do not exist. - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 15 +++++++++++---- src/include/cpu/intel/speedstep.h | 3 +++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..2ac9093 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -14,6 +14,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX mdelay(10); #endif @@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX num_starts = 2; #else num_starts = 1; @@ -269,7 +270,7 @@ int start_cpu(device_t cpu) break; } udelay(10); - } + } } secondary_stack = 0; spin_unlock(&start_cpu_lock); @@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) { device_t cpu; int old_active_count, active_count; + long loopcount = 0; + /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); @@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } udelay(10); active_count = atomic_read(&active_cpus); + loopcount++; } for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } if (!cpu->initialized) { printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", cpu->path.apic.apic_id); } } - printk(BIOS_DEBUG, "All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } #else /* CONFIG_SMP */ diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 0fa5244..00a5b9b 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -19,6 +19,9 @@ * MA 02110-1301 USA */ +/* Magic value used to locate speedstep configuration in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + /* MWAIT coordination I/O base address. This must match * the \_PR_.CPU0 PM base address. */

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Patch merged into coreboot/master: e35b393 Remove Dell s1850
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit e35b393caad3c74efc8c06c1d13a9608cd316618 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying to work with Dell we have not had much interest. It's misleading to have it there. Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b Build-Tested: build bot (Jenkins) at Fri Apr 6 23:16:03 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 6 23:21:51 2012, giving +2 See http://review.coreboot.org/876 for details. -gerrit

1 0

Patch set updated for coreboot: e35b393 Remove Dell s1850
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/876 -gerrit commit e35b393caad3c74efc8c06c1d13a9608cd316618 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying to work with Dell we have not had much interest. It's misleading to have it there. Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b --- src/mainboard/Kconfig | 3 - src/mainboard/dell/Kconfig | 17 -- src/mainboard/dell/s1850/Kconfig | 44 ---- src/mainboard/dell/s1850/Makefile.inc | 1 - src/mainboard/dell/s1850/chip.h | 3 - src/mainboard/dell/s1850/cmos.layout | 80 -------- src/mainboard/dell/s1850/debug.c | 289 --------------------------- src/mainboard/dell/s1850/devicetree.cb | 72 ------- src/mainboard/dell/s1850/irq_tables.c | 53 ----- src/mainboard/dell/s1850/mainboard.c | 7 - src/mainboard/dell/s1850/mptable.c | 160 --------------- src/mainboard/dell/s1850/reset.c | 16 -- src/mainboard/dell/s1850/romstage.c | 324 ------------------------------- src/mainboard/dell/s1850/s1850_fixups.c | 60 ------ src/mainboard/dell/s1850/watchdog.c | 57 ------ 15 files changed, 0 insertions(+), 1186 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 051ae45..64ae1d6 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -44,8 +44,6 @@ config VENDOR_BROADCOM bool "Broadcom" config VENDOR_COMPAQ bool "Compaq" -config VENDOR_DELL - bool "Dell" config VENDOR_DIGITALLOGIC bool "DIGITAL-LOGIC" config VENDOR_EAGLELION @@ -149,7 +147,6 @@ source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" -source "src/mainboard/dell/Kconfig" source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/ecs/Kconfig" diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig deleted file mode 100644 index fb665c4..0000000 --- a/src/mainboard/dell/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if VENDOR_DELL - -choice - prompt "Mainboard model" - -config BOARD_DELL_S1850 - bool "PowerEdge 1850" - -endchoice - -source "src/mainboard/dell/s1850/Kconfig" - -config MAINBOARD_VENDOR - string - default "Dell" - -endif # VENDOR_DELL diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig deleted file mode 100644 index cd4a6a9..0000000 --- a/src/mainboard/dell/s1850/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if BOARD_DELL_S1850 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_INTEL_SOCKET_MPGA604 - select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801EX - select SOUTHBRIDGE_INTEL_PXHD - select SUPERIO_NSC_PC8374 - select ROMCC - select HAVE_OPTION_TABLE - select BOARD_HAS_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_1024 - select UDELAY_TSC - -config MAINBOARD_DIR - string - default dell/s1850 - -config MAINBOARD_PART_NUMBER - string - default "PowerEdge 1850" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config IRQ_SLOT_COUNT - int - default 9 - -config DIMM_MAP_LOGICAL - hex - default 0x2841 - -endif # BOARD_DELL_S1850 diff --git a/src/mainboard/dell/s1850/Makefile.inc b/src/mainboard/dell/s1850/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/dell/s1850/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/dell/s1850/chip.h b/src/mainboard/dell/s1850/chip.h deleted file mode 100644 index d138e51..0000000 --- a/src/mainboard/dell/s1850/chip.h +++ /dev/null @@ -1,3 +0,0 @@ -extern struct chip_operations mainboard_ops; - -struct mainboard_config {}; diff --git a/src/mainboard/dell/s1850/cmos.layout b/src/mainboard/dell/s1850/cmos.layout deleted file mode 100644 index 81f1a69..0000000 --- a/src/mainboard/dell/s1850/cmos.layout +++ /dev/null @@ -1,80 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c deleted file mode 100644 index 7904c06..0000000 --- a/src/mainboard/dell/s1850/debug.c +++ /dev/null @@ -1,289 +0,0 @@ -#include <spd.h> - -static void print_reg(unsigned char index) -{ - unsigned char data; - - outb(index, 0x2e); - data = inb(0x2f); - print_debug("0x"); - print_debug_hex8(index); - print_debug(": 0x"); - print_debug_hex8(data); - print_debug("\n"); - return; -} - -static void xbus_en(void) -{ - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); - return; -} - -static void setup_func(unsigned char func) -{ - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; -} - -static void siodump(void) -{ - int i; - unsigned char data; - - print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } -#if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } - - print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); - - print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); - -#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); - print_debug("\nGPDO 4: 0x"); - print_debug_hex8(data); - data = inb(0x68b); - print_debug("\nGPDI 4: 0x"); - print_debug_hex8(data); - print_debug("\n"); - -#if 0 - - print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); - - print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); - - print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); - - print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); -#endif - return; -} - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - } -} - -static void dump_bar14(unsigned dev) -{ - int i; - unsigned long bar; - - print_debug("BAR 14 Dump\n"); - - bar = pci_read_config32(dev, 0x14); - for(i = 0; i <= 0x300; i+=4) { -#if 0 - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); -#endif - if((i%4)==0) { - print_debug("\n"); - print_debug_hex16(i); - print_debug_char(' '); - } - print_debug_hex32(read32(bar + i)); - print_debug_char(' '); - } - print_debug("\n"); -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_spd_registers(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} - -void show_dram_slots(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - status = smbus_read_byte(device, 0); - if (status < 0) { - print_debug("bad device: "); - } else { - print_debug("present: "); - } - print_debug_hex8(status); - print_debug("\n"); - device++; - print_debug("\n"); - } -} - -void dump_ipmi_registers(void) -{ - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); - print_debug_hex8(device); - - for(i = 0; (i < 8) ; i++) { - unsigned char byte; - status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb deleted file mode 100644 index c56fd37..0000000 --- a/src/mainboard/dell/s1850/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/nsc/pc8374 - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 off end - device pnp 2e.3 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.8 off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x8a07030b" - register "pirq_e_h" = "0x85808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device lapic 6 on end - end - end - register "intrline" = "0x00070100" -end - diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c deleted file mode 100644 index e6073c7..0000000 --- a/src/mainboard/dell/s1850/irq_tables.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x66, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/dell/s1850/mainboard.c b/src/mainboard/dell/s1850/mainboard.c deleted file mode 100644 index 3d22f2d..0000000 --- a/src/mainboard/dell/s1850/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_ops = { - CHIP_NAME("Dell S1850 Mainboard") -}; - diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c deleted file mode 100644 index 0c7562c..0000000 --- a/src/mainboard/dell/s1850/mptable.c +++ /dev/null @@ -1,160 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_pxhd_1; - unsigned char bus_pxhd_2; - unsigned char bus_pxhd_3; - unsigned char bus_pxhd_4; - unsigned char bus_ich5r_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* ich5r */ - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - if (dev) { - bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_ich5r_1 = 7; - } - /* pxhd-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); - if (dev) { - bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n"); - bus_pxhd_1 = 2; - } - /* pxhd-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); - if (dev) { - bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n"); - bus_pxhd_2 = 3; - } - - /* pxhd-3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); - if (dev) { - bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n"); - bus_pxhd_3 = 5; - } - /* pxhd-4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); - if (dev) { - bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n"); - bus_pxhd_4 = 6; - } - - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - struct resource *res; - device_t dev; - /* pxhd apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); - } - /* pxhd apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); - } - } - - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x76, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x77, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7c, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x08, 0x03, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0c, 0x03, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0d, 0x03, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_2, 0x08, 0x04, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_ich5r_1, 0x04, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_4, 0x00, 0x02, 0x10); -#if 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - (bus_isa - 1), 0x04, 0x02, 0x10); -#endif - /* Standard local interrupt assignments */ -#if 0 - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x00); -#endif - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} - diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c deleted file mode 100644 index 745f187..0000000 --- a/src/mainboard/dell/s1850/reset.c +++ /dev/null @@ -1,16 +0,0 @@ -#include <arch/io.h> -#include <reset.h> -#if defined (__PRE_RAM__) -#include <arch/romcc_io.h> -#endif - -void soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c deleted file mode 100644 index e636986..0000000 --- a/src/mainboard/dell/s1850/romstage.c +++ /dev/null @@ -1,324 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include <console/console.h> -#include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7520/raminit.h" -#include "superio/nsc/pc8374/early_init.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "debug.c" -#include "watchdog.c" -// Remove comment if resets in this file are actually used. -// #include "reset.c" -#include "s1850_fixups.c" -#include "northbridge/intel/e7520/memory_initialized.c" -#include "cpu/x86/bist.h" -#include <spd.h> - -#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) - -#define DEVPRES_CONFIG ( \ - DEVPRES_D0F0 | \ - DEVPRES_D1F0 | \ - DEVPRES_D2F0 | \ - DEVPRES_D3F0 | \ - DEVPRES_D4F0 | \ - DEVPRES_D6F0 | \ - 0 ) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7520/raminit.c" -#include "lib/generic_sdram.c" - -/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere - */ - -#define nftransport 0xc - -#define OBF 0 -#define IBF 1 - -#define ipmidata 0xca0 -#define ipmicsr 0xca4 - -static inline void ibfzero(void) -{ - while(inb(ipmicsr) & (1<<IBF)) - ; -} -static inline void clearobf(void) -{ - (void) inb(ipmidata); -} - -static inline void waitobf(void) -{ - while((inb(ipmicsr) & (1<<OBF)) == 0) - ; -} - -/* quite possibly the stupidest interface ever designed. */ -static inline void first_cmd_byte(unsigned char byte) -{ - ibfzero(); - clearobf(); - outb(0x61, ipmicsr); - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void next_cmd_byte(unsigned char byte) -{ - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void last_cmd_byte(unsigned char byte) -{ - outb(0x62, ipmicsr); - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void read_response_byte(void) -{ - int val = -1; - if ((inb(ipmicsr)>>6) != 1) - return; - - ibfzero(); - waitobf(); - val = inb(ipmidata); - outb(0x68, ipmidata); - - /* see if it is done */ - if ((inb(ipmicsr)>>6) != 1){ - /* wait for the dummy read. Which describes this protocol */ - waitobf(); - (void)inb(ipmidata); - } -} - -static inline void ipmidelay(void) -{ - int i; - for(i = 0; i < 1000; i++) { - inb(0x80); - } -} - -static inline void bmc_foad(void) -{ - unsigned char c; - /* be safe; make sure it is really ready */ - while ((inb(ipmicsr)>>6)) { - outb(0x60, ipmicsr); - inb(ipmidata); - } - first_cmd_byte(nftransport << 2); - ipmidelay(); - next_cmd_byte(0x12); - ipmidelay(); - next_cmd_byte(2); - ipmidelay(); - last_cmd_byte(3); - ipmidelay(); -} - -/* end IPMI garbage */ - -#include "arch/x86/lib/stages.c" - -static void main(unsigned long bist) -{ - u8 b; - u16 w; - u32 l; - int do_reset; - - static const struct mem_controller mch[] = { - { - .node_id = 0, - /* the wiring on this part is really messed up */ - /* this is my best guess so far */ - .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, - .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, - } - }; - - /* superio setup */ - /* observed from serialice */ - static const u8 earlyinit[] = { - 0x21, 0x11, 0x11, - 0x22, 1, 1, - 0x23, 05, 05, - 0x24, 0x81, 0x81, - 0x26, 0, 0, - 0, - }; - - /* using SerialICE, we've seen this basic reset sequence on the dell. - * we don't understand it as it uses undocumented registers, but - * we're going to clone it. - */ - /* enable a hidden device. */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* read-write lock in CMOS on LPC bridge on ICH5 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4); - - /* operate on undocumented device */ - l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4); - l |= 0x1000; - pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l); - - l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c); - l |= 0x8000; - pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l); - - /* disable undocumented device */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b &= ~0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* set up LPC bridge bits, some of which reply on undocumented - * registers - */ - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); - b |= 4; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b); - - /* ACPI base address */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800); - - /* Enable specific ACPI features */ - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44); - b |= 0x10; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b); - - /* ACPI control */ - w = inw(0x868); - outw(w|0x800, 0x868); - w = inw(0x866); - outw(w|2, 0x866); - -#if 0 - /*seriaice shows - dell does this so leave it here so I don't forget - */ - /* SMBUS */ - pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); - - /* unknown */ - b = inb(0x8c2); - outb(0xdf, 0x8c2); -#endif - - /* another device enable? */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* ?? */ - l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0); - do_reset = l & 0x8000000; - l |= 0x8000000; - pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l); - - if (! do_reset) { - outb(2, 0xcf9); - outb(6, 0xcf9); - } - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - early_mtrr_init(); - if (memory_initialized()) - skip_romstage(); - } - /* Setup the console */ - mainboard_set_ich5(); - //bmc_foad(); - pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* stuff we seem to need */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0); - - /* GPIOs */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20); - - /* keep this in mind. - SerialICE-hlp: outb 002e <= 23 - SerialICE-hlp: inb 002f => 05 - SerialICE-hlp: outb 002f <= 05 - SerialICE-hlp: outb 002e <= 24 - SerialICE-hlp: inb 002f => c1 - SerialICE-hlp: outb 002f <= c1 - */ - - /* Halt if there was a built in self test failure */ -// report_bist_failure(bist); - - /* MOVE ME TO A BETTER LOCATION !!! */ - /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); - -#if 0 - display_cpuid_update_microcode(); -#endif -#if 1 - print_pci_devices(); -#endif -#if 1 - enable_smbus(); -#endif -#if 0 -// dump_spd_registers(&cpu[0]); - int i; - for(i = 0; i < 1; i++) - dump_spd_registers(); -#endif -#if 1 - show_dram_slots(); -#endif - disable_watchdogs(); -// dump_ipmi_registers(); - mainboard_set_e7520_leds(); - - sdram_initialize(ARRAY_SIZE(mch), mch); -#if 0 - dump_pci_devices(); -#endif -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); -// dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} diff --git a/src/mainboard/dell/s1850/s1850_fixups.c b/src/mainboard/dell/s1850/s1850_fixups.c deleted file mode 100644 index 7ef9ce1..0000000 --- a/src/mainboard/dell/s1850/s1850_fixups.c +++ /dev/null @@ -1,60 +0,0 @@ -#include <arch/romcc_io.h> - -static void mch_reset(void) -{ - return; -} - - - -static void mainboard_set_e7520_pll(unsigned bits) -{ - return; -} - - -static void mainboard_set_e7520_leds(void) -{ - return; -} - -static void mainboard_set_ich5(void) -{ - /* coma is 0x3f8 , comb is 0x2f8*/ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe0, 0x10); - /* enable decoding of various devices */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xe6, 0x140f); - /* 1M flash */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0); - /* disable certain devices -- see data sheet -- this is from - * dell settings via lspci - * Note that they leave SMBUS disabled -- 8f6f. - * we leave it enabled and visible in config space -- 8f66 - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); - /* GPIOs -- needed, possibly, for SPD */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x58, 0x881); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); - - /* now the fun begins ... enable the GPIOs as done on factory */ - /* factory config from IO ports - * It has a few more things enabled than default! - */ - outl(0x1ae0f183, 0x880); - outl(0x1b00ffff, 0x884); - outl(0x131f0000, 0x88c); - outl(0x00000000, 0x894); - outl(0x00040000, 0x898); - outl(0x00000000, 0x8a4); - outl(0x00000000, 0x8a8); - outl(0x000031c0, 0x8ac); - outl(0x00000007, 0x8b0); - outl(0x00000304, 0x8b4); - outl(0x00030303, 0x8b8); - -} - - - - diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c deleted file mode 100644 index 43f4029..0000000 --- a/src/mainboard/dell/s1850/watchdog.c +++ /dev/null @@ -1,57 +0,0 @@ -#include <device/pnp_def.h> - -#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) -#define NSC_WDBASE 0x600 -#define ICH5_WDBASE 0x400 -#define ICH5_GPIOBASE 0x500 - -static void disable_sio_watchdog(device_t dev) -{ -#if 0 - /* FIXME move me somewhere more appropriate */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); - /* disable the sio watchdog */ - outb(0, NSC_WDBASE + 0); - pnp_set_enable(dev, 0); -#endif -} - -static void disable_ich5_watchdog(void) -{ - /* FIXME move me somewhere more appropriate */ - device_t dev; - unsigned long value, base; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Set and enable acpibase */ - pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); - pci_write_config8(dev, 0x44, 0x10); - base = ICH5_WDBASE + 0x60; - - /* Set bit 11 in TCO1_CNT */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); -} - - -static void disable_watchdogs(void) -{ -// disable_sio_watchdog(NSC_WD_DEV); - disable_ich5_watchdog(); - print_debug("Watchdogs disabled\n"); -} -

1 0

Re: [coreboot] [RFC] Re-thinking the stages
by ron minnich 06 Apr '12

06 Apr '12

On Fri, Apr 6, 2012 at 11:12 AM, Marc Jones <marcj303(a)gmail.com> wrote: >> 3. Microcode updates >> >> The "tiny" bootblock doesn't seem like the correct place for microcode >> updates. >> > > Does microcode have to be this early? Before CAR? Yes. Some history. We started out doing microcode updates in linux. Then it moved to the end of the ram stage. Then the start. Then it turned out it had to happen before CAR. So be careful! Sure, it may not make sense, but hardware often does not. This is an example of a seemingly sensible change, that would work on many platforms, and destroy others. This is a really tricky area. >> One such a nice app would be zmodem download of raminit. >> > > This is an interesting thought, but really a debug/development > feature. We even talked about this in v3. But it never got done, seems there is no interest. > I am not convinced of the value of earlier serial console. It adds > complexity where things should be simple. I hesitate to continue > moving more code before CAR. We have had a long standing goal to > reduce code before CAR. CAR is fragile! I agree. It should be reduced as much as possible. You may want to look at what we did in v3, it has some similarities to your ideas. And, we dropped it :-) ron

1 0

Patch set updated for coreboot: 4159696 Remove Dell s1850
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/876 -gerrit commit 4159696eabb8bb7aae741e19962fe00aed03329e Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying to work with Dell we have not had much interest. It's misleading to have it there. Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b --- src/mainboard/dell/Kconfig | 17 -- src/mainboard/dell/s1850/Kconfig | 44 ---- src/mainboard/dell/s1850/Makefile.inc | 1 - src/mainboard/dell/s1850/chip.h | 3 - src/mainboard/dell/s1850/cmos.layout | 80 -------- src/mainboard/dell/s1850/debug.c | 289 --------------------------- src/mainboard/dell/s1850/devicetree.cb | 72 ------- src/mainboard/dell/s1850/irq_tables.c | 53 ----- src/mainboard/dell/s1850/mainboard.c | 7 - src/mainboard/dell/s1850/mptable.c | 160 --------------- src/mainboard/dell/s1850/reset.c | 16 -- src/mainboard/dell/s1850/romstage.c | 324 ------------------------------- src/mainboard/dell/s1850/s1850_fixups.c | 60 ------ src/mainboard/dell/s1850/watchdog.c | 57 ------ 14 files changed, 0 insertions(+), 1183 deletions(-) diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig deleted file mode 100644 index fb665c4..0000000 --- a/src/mainboard/dell/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if VENDOR_DELL - -choice - prompt "Mainboard model" - -config BOARD_DELL_S1850 - bool "PowerEdge 1850" - -endchoice - -source "src/mainboard/dell/s1850/Kconfig" - -config MAINBOARD_VENDOR - string - default "Dell" - -endif # VENDOR_DELL diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig deleted file mode 100644 index cd4a6a9..0000000 --- a/src/mainboard/dell/s1850/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if BOARD_DELL_S1850 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_INTEL_SOCKET_MPGA604 - select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801EX - select SOUTHBRIDGE_INTEL_PXHD - select SUPERIO_NSC_PC8374 - select ROMCC - select HAVE_OPTION_TABLE - select BOARD_HAS_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_1024 - select UDELAY_TSC - -config MAINBOARD_DIR - string - default dell/s1850 - -config MAINBOARD_PART_NUMBER - string - default "PowerEdge 1850" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config IRQ_SLOT_COUNT - int - default 9 - -config DIMM_MAP_LOGICAL - hex - default 0x2841 - -endif # BOARD_DELL_S1850 diff --git a/src/mainboard/dell/s1850/Makefile.inc b/src/mainboard/dell/s1850/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/dell/s1850/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/dell/s1850/chip.h b/src/mainboard/dell/s1850/chip.h deleted file mode 100644 index d138e51..0000000 --- a/src/mainboard/dell/s1850/chip.h +++ /dev/null @@ -1,3 +0,0 @@ -extern struct chip_operations mainboard_ops; - -struct mainboard_config {}; diff --git a/src/mainboard/dell/s1850/cmos.layout b/src/mainboard/dell/s1850/cmos.layout deleted file mode 100644 index 81f1a69..0000000 --- a/src/mainboard/dell/s1850/cmos.layout +++ /dev/null @@ -1,80 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c deleted file mode 100644 index 7904c06..0000000 --- a/src/mainboard/dell/s1850/debug.c +++ /dev/null @@ -1,289 +0,0 @@ -#include <spd.h> - -static void print_reg(unsigned char index) -{ - unsigned char data; - - outb(index, 0x2e); - data = inb(0x2f); - print_debug("0x"); - print_debug_hex8(index); - print_debug(": 0x"); - print_debug_hex8(data); - print_debug("\n"); - return; -} - -static void xbus_en(void) -{ - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); - return; -} - -static void setup_func(unsigned char func) -{ - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; -} - -static void siodump(void) -{ - int i; - unsigned char data; - - print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } -#if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } - - print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); - - print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); - -#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); - print_debug("\nGPDO 4: 0x"); - print_debug_hex8(data); - data = inb(0x68b); - print_debug("\nGPDI 4: 0x"); - print_debug_hex8(data); - print_debug("\n"); - -#if 0 - - print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); - - print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); - - print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); - - print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); -#endif - return; -} - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - } -} - -static void dump_bar14(unsigned dev) -{ - int i; - unsigned long bar; - - print_debug("BAR 14 Dump\n"); - - bar = pci_read_config32(dev, 0x14); - for(i = 0; i <= 0x300; i+=4) { -#if 0 - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); -#endif - if((i%4)==0) { - print_debug("\n"); - print_debug_hex16(i); - print_debug_char(' '); - } - print_debug_hex32(read32(bar + i)); - print_debug_char(' '); - } - print_debug("\n"); -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_spd_registers(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} - -void show_dram_slots(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - status = smbus_read_byte(device, 0); - if (status < 0) { - print_debug("bad device: "); - } else { - print_debug("present: "); - } - print_debug_hex8(status); - print_debug("\n"); - device++; - print_debug("\n"); - } -} - -void dump_ipmi_registers(void) -{ - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); - print_debug_hex8(device); - - for(i = 0; (i < 8) ; i++) { - unsigned char byte; - status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb deleted file mode 100644 index c56fd37..0000000 --- a/src/mainboard/dell/s1850/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/nsc/pc8374 - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 off end - device pnp 2e.3 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.8 off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x8a07030b" - register "pirq_e_h" = "0x85808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device lapic 6 on end - end - end - register "intrline" = "0x00070100" -end - diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c deleted file mode 100644 index e6073c7..0000000 --- a/src/mainboard/dell/s1850/irq_tables.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x66, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/dell/s1850/mainboard.c b/src/mainboard/dell/s1850/mainboard.c deleted file mode 100644 index 3d22f2d..0000000 --- a/src/mainboard/dell/s1850/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_ops = { - CHIP_NAME("Dell S1850 Mainboard") -}; - diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c deleted file mode 100644 index 0c7562c..0000000 --- a/src/mainboard/dell/s1850/mptable.c +++ /dev/null @@ -1,160 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_pxhd_1; - unsigned char bus_pxhd_2; - unsigned char bus_pxhd_3; - unsigned char bus_pxhd_4; - unsigned char bus_ich5r_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* ich5r */ - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - if (dev) { - bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_ich5r_1 = 7; - } - /* pxhd-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); - if (dev) { - bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n"); - bus_pxhd_1 = 2; - } - /* pxhd-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); - if (dev) { - bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n"); - bus_pxhd_2 = 3; - } - - /* pxhd-3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); - if (dev) { - bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n"); - bus_pxhd_3 = 5; - } - /* pxhd-4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); - if (dev) { - bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n"); - bus_pxhd_4 = 6; - } - - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - struct resource *res; - device_t dev; - /* pxhd apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); - } - /* pxhd apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); - } - } - - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x76, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x77, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7c, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x08, 0x03, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0c, 0x03, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0d, 0x03, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_2, 0x08, 0x04, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_ich5r_1, 0x04, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_4, 0x00, 0x02, 0x10); -#if 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - (bus_isa - 1), 0x04, 0x02, 0x10); -#endif - /* Standard local interrupt assignments */ -#if 0 - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x00); -#endif - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} - diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c deleted file mode 100644 index 745f187..0000000 --- a/src/mainboard/dell/s1850/reset.c +++ /dev/null @@ -1,16 +0,0 @@ -#include <arch/io.h> -#include <reset.h> -#if defined (__PRE_RAM__) -#include <arch/romcc_io.h> -#endif - -void soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c deleted file mode 100644 index e636986..0000000 --- a/src/mainboard/dell/s1850/romstage.c +++ /dev/null @@ -1,324 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include <console/console.h> -#include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7520/raminit.h" -#include "superio/nsc/pc8374/early_init.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "debug.c" -#include "watchdog.c" -// Remove comment if resets in this file are actually used. -// #include "reset.c" -#include "s1850_fixups.c" -#include "northbridge/intel/e7520/memory_initialized.c" -#include "cpu/x86/bist.h" -#include <spd.h> - -#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) - -#define DEVPRES_CONFIG ( \ - DEVPRES_D0F0 | \ - DEVPRES_D1F0 | \ - DEVPRES_D2F0 | \ - DEVPRES_D3F0 | \ - DEVPRES_D4F0 | \ - DEVPRES_D6F0 | \ - 0 ) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7520/raminit.c" -#include "lib/generic_sdram.c" - -/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere - */ - -#define nftransport 0xc - -#define OBF 0 -#define IBF 1 - -#define ipmidata 0xca0 -#define ipmicsr 0xca4 - -static inline void ibfzero(void) -{ - while(inb(ipmicsr) & (1<<IBF)) - ; -} -static inline void clearobf(void) -{ - (void) inb(ipmidata); -} - -static inline void waitobf(void) -{ - while((inb(ipmicsr) & (1<<OBF)) == 0) - ; -} - -/* quite possibly the stupidest interface ever designed. */ -static inline void first_cmd_byte(unsigned char byte) -{ - ibfzero(); - clearobf(); - outb(0x61, ipmicsr); - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void next_cmd_byte(unsigned char byte) -{ - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void last_cmd_byte(unsigned char byte) -{ - outb(0x62, ipmicsr); - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void read_response_byte(void) -{ - int val = -1; - if ((inb(ipmicsr)>>6) != 1) - return; - - ibfzero(); - waitobf(); - val = inb(ipmidata); - outb(0x68, ipmidata); - - /* see if it is done */ - if ((inb(ipmicsr)>>6) != 1){ - /* wait for the dummy read. Which describes this protocol */ - waitobf(); - (void)inb(ipmidata); - } -} - -static inline void ipmidelay(void) -{ - int i; - for(i = 0; i < 1000; i++) { - inb(0x80); - } -} - -static inline void bmc_foad(void) -{ - unsigned char c; - /* be safe; make sure it is really ready */ - while ((inb(ipmicsr)>>6)) { - outb(0x60, ipmicsr); - inb(ipmidata); - } - first_cmd_byte(nftransport << 2); - ipmidelay(); - next_cmd_byte(0x12); - ipmidelay(); - next_cmd_byte(2); - ipmidelay(); - last_cmd_byte(3); - ipmidelay(); -} - -/* end IPMI garbage */ - -#include "arch/x86/lib/stages.c" - -static void main(unsigned long bist) -{ - u8 b; - u16 w; - u32 l; - int do_reset; - - static const struct mem_controller mch[] = { - { - .node_id = 0, - /* the wiring on this part is really messed up */ - /* this is my best guess so far */ - .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, - .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, - } - }; - - /* superio setup */ - /* observed from serialice */ - static const u8 earlyinit[] = { - 0x21, 0x11, 0x11, - 0x22, 1, 1, - 0x23, 05, 05, - 0x24, 0x81, 0x81, - 0x26, 0, 0, - 0, - }; - - /* using SerialICE, we've seen this basic reset sequence on the dell. - * we don't understand it as it uses undocumented registers, but - * we're going to clone it. - */ - /* enable a hidden device. */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* read-write lock in CMOS on LPC bridge on ICH5 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4); - - /* operate on undocumented device */ - l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4); - l |= 0x1000; - pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l); - - l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c); - l |= 0x8000; - pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l); - - /* disable undocumented device */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b &= ~0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* set up LPC bridge bits, some of which reply on undocumented - * registers - */ - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); - b |= 4; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b); - - /* ACPI base address */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800); - - /* Enable specific ACPI features */ - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44); - b |= 0x10; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b); - - /* ACPI control */ - w = inw(0x868); - outw(w|0x800, 0x868); - w = inw(0x866); - outw(w|2, 0x866); - -#if 0 - /*seriaice shows - dell does this so leave it here so I don't forget - */ - /* SMBUS */ - pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); - - /* unknown */ - b = inb(0x8c2); - outb(0xdf, 0x8c2); -#endif - - /* another device enable? */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* ?? */ - l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0); - do_reset = l & 0x8000000; - l |= 0x8000000; - pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l); - - if (! do_reset) { - outb(2, 0xcf9); - outb(6, 0xcf9); - } - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - early_mtrr_init(); - if (memory_initialized()) - skip_romstage(); - } - /* Setup the console */ - mainboard_set_ich5(); - //bmc_foad(); - pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* stuff we seem to need */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0); - - /* GPIOs */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20); - - /* keep this in mind. - SerialICE-hlp: outb 002e <= 23 - SerialICE-hlp: inb 002f => 05 - SerialICE-hlp: outb 002f <= 05 - SerialICE-hlp: outb 002e <= 24 - SerialICE-hlp: inb 002f => c1 - SerialICE-hlp: outb 002f <= c1 - */ - - /* Halt if there was a built in self test failure */ -// report_bist_failure(bist); - - /* MOVE ME TO A BETTER LOCATION !!! */ - /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); - -#if 0 - display_cpuid_update_microcode(); -#endif -#if 1 - print_pci_devices(); -#endif -#if 1 - enable_smbus(); -#endif -#if 0 -// dump_spd_registers(&cpu[0]); - int i; - for(i = 0; i < 1; i++) - dump_spd_registers(); -#endif -#if 1 - show_dram_slots(); -#endif - disable_watchdogs(); -// dump_ipmi_registers(); - mainboard_set_e7520_leds(); - - sdram_initialize(ARRAY_SIZE(mch), mch); -#if 0 - dump_pci_devices(); -#endif -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); -// dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} diff --git a/src/mainboard/dell/s1850/s1850_fixups.c b/src/mainboard/dell/s1850/s1850_fixups.c deleted file mode 100644 index 7ef9ce1..0000000 --- a/src/mainboard/dell/s1850/s1850_fixups.c +++ /dev/null @@ -1,60 +0,0 @@ -#include <arch/romcc_io.h> - -static void mch_reset(void) -{ - return; -} - - - -static void mainboard_set_e7520_pll(unsigned bits) -{ - return; -} - - -static void mainboard_set_e7520_leds(void) -{ - return; -} - -static void mainboard_set_ich5(void) -{ - /* coma is 0x3f8 , comb is 0x2f8*/ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe0, 0x10); - /* enable decoding of various devices */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xe6, 0x140f); - /* 1M flash */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0); - /* disable certain devices -- see data sheet -- this is from - * dell settings via lspci - * Note that they leave SMBUS disabled -- 8f6f. - * we leave it enabled and visible in config space -- 8f66 - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); - /* GPIOs -- needed, possibly, for SPD */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x58, 0x881); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); - - /* now the fun begins ... enable the GPIOs as done on factory */ - /* factory config from IO ports - * It has a few more things enabled than default! - */ - outl(0x1ae0f183, 0x880); - outl(0x1b00ffff, 0x884); - outl(0x131f0000, 0x88c); - outl(0x00000000, 0x894); - outl(0x00040000, 0x898); - outl(0x00000000, 0x8a4); - outl(0x00000000, 0x8a8); - outl(0x000031c0, 0x8ac); - outl(0x00000007, 0x8b0); - outl(0x00000304, 0x8b4); - outl(0x00030303, 0x8b8); - -} - - - - diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c deleted file mode 100644 index 43f4029..0000000 --- a/src/mainboard/dell/s1850/watchdog.c +++ /dev/null @@ -1,57 +0,0 @@ -#include <device/pnp_def.h> - -#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) -#define NSC_WDBASE 0x600 -#define ICH5_WDBASE 0x400 -#define ICH5_GPIOBASE 0x500 - -static void disable_sio_watchdog(device_t dev) -{ -#if 0 - /* FIXME move me somewhere more appropriate */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); - /* disable the sio watchdog */ - outb(0, NSC_WDBASE + 0); - pnp_set_enable(dev, 0); -#endif -} - -static void disable_ich5_watchdog(void) -{ - /* FIXME move me somewhere more appropriate */ - device_t dev; - unsigned long value, base; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Set and enable acpibase */ - pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); - pci_write_config8(dev, 0x44, 0x10); - base = ICH5_WDBASE + 0x60; - - /* Set bit 11 in TCO1_CNT */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); -} - - -static void disable_watchdogs(void) -{ -// disable_sio_watchdog(NSC_WD_DEV); - disable_ich5_watchdog(); - print_debug("Watchdogs disabled\n"); -} -

1 0

New patch to review for coreboot: d8f2b2f Add multicore support to coreboot.
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit d8f2b2f51ab249977430685dec0093b8e0256106 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot. This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs easier, we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 --- src/arch/x86/include/arch/cpu.h | 5 ++ src/arch/x86/lib/cpu.c | 30 ++++++++-- src/cpu/x86/lapic/lapic_cpu_init.c | 117 +++++++++++++++++++++++++++++++++--- src/include/cpu/cpu.h | 10 +++- 4 files changed, 146 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..5e2683e 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld, info %p\n", info->index, info); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,26 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); + + return; +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..02924e2 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -16,6 +16,21 @@ #include <cpu/cpu.h> #if CONFIG_SMP == 1 + +/* we do not want this struct visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[1024 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) +typedef struct apcore apcore_t; + +apcore_t apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -224,9 +239,11 @@ static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; static unsigned last_cpu_index = 0; volatile unsigned long secondary_stack; +static void testfunc(u32 a, u32 b, u32 c){ + printk(a, "testfunc: %s %d\n", (char *)b, (int)c); +} int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; @@ -243,16 +260,17 @@ int start_cpu(device_t cpu) index = ++last_cpu_index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + printk(BIOS_SPEW, "start_cpu CPU %ld secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -273,6 +291,12 @@ int start_cpu(device_t cpu) } secondary_stack = 0; spin_unlock(&start_cpu_lock); + if (result) { /* test work */ + printk(BIOS_SPEW, "BSP tests work\n"); + run_work(index, (workfunc)testfunc, BIOS_SPEW, + (u32)"Hello; run_work works", 555, NULL, 5000000); + printk(BIOS_SPEW, "Done core %ld\n", index); + } return result; } @@ -380,8 +404,11 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) -{ +void secondary_cpu_init(u32 x) + { + /* note: we tried (((u32 *)&x)[1]) but that failed. Compiler? */ + struct cpu_info *info = (struct cpu_info *)(((u8*)&x)+4); + atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); @@ -397,11 +424,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -498,6 +525,7 @@ void initialize_cpus(struct bus *cpu_bus) info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 + memset(apcores, 0, sizeof(*apcores)); copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -515,7 +543,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -527,3 +555,74 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + *ptr = f; + return 0; +} + +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait) +{ + int i = 0; + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *result; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + while (i++ < maxwait && *ptr) + if (i%100000 == 0) printk(BIOS_SPEW, "still waiting on %p at %d\n", + ptr, i); + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d iterations\n", + core, i); + return -1; + } + result = &info->result; + printk(BIOS_INFO, "info->work after result is %#lx\n", (unsigned long)*result); + if (retval) + *retval = *result; + return 0; +} + +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..39f2fa2 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,15 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(u32 unused); +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c); +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0)

1 0

Re: [coreboot] [RFC] Re-thinking the stages
by Patrick Georgi 06 Apr '12

06 Apr '12

Am 06.04.2012 20:12, schrieb Marc Jones: > There is a lot of assumed configuration ownership in the vendor code, > and coreboot may need to adjust to that. Something else to consider as > you design these stages. Reminds me: can we get rid of platform_cfg.h on AGESA boards, please? Patrick

1 0

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coreboot April 2012