coreboot April 2012

coreboot@coreboot.org

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459 discussions

Patch set updated for coreboot: 19807ed cmos.layout: Remove invalid warning
by Vikram Narayanan 15 Apr '12

15 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/899 -gerrit commit 19807eda20ce738b5419cb003f1aeae6d0e2fbcd Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:51:53 2012 +0530 cmos.layout: Remove invalid warning "This file must be in UNIX format" is not valid anymore. Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/mainboard/intel/xe7501devkit/cmos.layout | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout index baae5eb..322f1c9 100644 --- a/src/mainboard/intel/xe7501devkit/cmos.layout +++ b/src/mainboard/intel/xe7501devkit/cmos.layout @@ -1,6 +1,3 @@ -# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: -# "Error - Name is an invalid identifier in line" - entries #start-bit length config config-ID name

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New patch to review for coreboot: e4fc528 Add the memory reference code binary for sandybridge chipsets
by Ronald G. Minnich 15 Apr '12

15 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/897 -gerrit commit e4fc5283d5c2e5fe8f75875a8229319696f8990b Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 12 04:26:22 2012 -0700 Add the memory reference code binary for sandybridge chipsets This binary is required for anyone who wishes to build a sandybridge mainboard. Change-Id: I779ef5e2b77166b81cb05eada37291368e74fbb6 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- 3rdparty/northbridge/intel/sandybridge/mrc.bin | Bin 0 -> 102932 bytes 1 files changed, 0 insertions(+), 0 deletions(-) diff --git a/3rdparty/northbridge/intel/sandybridge/mrc.bin b/3rdparty/northbridge/intel/sandybridge/mrc.bin new file mode 100644 index 0000000..eec64ed Binary files /dev/null and b/3rdparty/northbridge/intel/sandybridge/mrc.bin differ

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New patch to review for coreboot: c036828 ASUS M4A785T-M mainboard: fix screen flickering issues
by Denis Carikli 15 Apr '12

15 Apr '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/900 -gerrit commit c03682861a1d8716900b74ec3f197faa9a68cecd Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Apr 14 14:30:49 2012 +0200 ASUS M4A785T-M mainboard: fix screen flickering issues Without that fix the screen flickered with resolutions superior to 832x624 because the cpu_ht_freq was 0 (so it ran at 200Mhz). Change-Id: I1056d76b1d77f6177594ed9d03ecc5ae7b3c2c13 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785-m/romstage.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index a96592d..870af70 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -246,6 +246,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { +#ifndef CONFIG_BOARD_ASUS_M4A785TM static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { @@ -255,6 +256,14 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) return 1; } } +#else + static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } +#endif return 0; }

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Re: [coreboot] coreboot Digest, Vol 86, Issue 47
by Ken Phillis Jr 14 Apr '12

14 Apr '12

On Sat, Apr 14, 2012 at 1:55 PM, Paul Menzel wrote: > Dear Ken, > > > first off topic. > > 0. The spelling is coreboot, i. e. all lowercase. > 1. Please do not send HTML message to mailing lists [1]. > 2. Using Gmail Web interface the down side is it wraps line > automatically which is bad if you paste stuff. Since they will not fix > that, you should think about using a mail program. > > I normally have "rich formatting" disabled ( html messages ), however i forgot this. > Am Freitag, den 13.04.2012, 23:31 -0500 schrieb Ken Phillis Jr: > > Just another board support request... If there's any other information that > > is required, please ask me... > > > > General Board information: > > =============================================================================== > > Vendor: GIGABYTE > > Model: GA-MA790XT-UD4P (rev. 1.0) > > Product Page: http://www.gigabyte.us/products/product-page.aspx?pid=3010 > > North Bridge: AMD 790X > > South Bridge: AMD SB750 > > [?] > > As Peter wrote, you need to do the port yourself. Two good things > though, coreboot folks will help you if you have problems and your > components seem to be supported. So if you are willing to spend some > time, you should be able to complete that port. > I do expect some hassles with actual board to get fully configured. This is one of the Gigabyte boards that features dual-Bios on the board directly. > Please read the coreboot Wiki. You need to make sure to recover. Is the > flash chip socketed on your board? If yes, just get some back up chips, > find an already supported board similar to yours, build an image, > connect a second system over serial line to capture debugging output and > work your way through it. If something fails, just boot the system with > your back up flash chip, switch the flash chip and write another > (hopefully improved) image to it. > There is no flash chip socket on this board, and I do not have another computer that features a serial port. Actually, on a side note, what's the past trial and error that happened when dealing with other gigabyte boards that feature a dual-bios setup? On this board, there is two flash chips: I don't know what the ITE IT8720F super i/o chip clearly states that i cannot write to the bios on this chip, and when you look at the board, The chip is physically located over near the PCI Slots near the edge of the board. The other flash chip is the south bridge for the board. This is located over near the SATA ports under the heatsink. And finally, I do know that the bios chips are located near the southbridge. They have labels of M_BIOS, and B_BIOS. I know that there is a similar board already supported in CoreBoot... That board is the Gigabyte MA785GMT-UD2H. http://www.gigabyte.us/products/product-page.aspx?pid=3395#ov The only differences on this is that the dual-bios is located near the Super I/O that near the main power connector. > We are looking forward to your port! > > > Thanks, > > Paul > > > [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette

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Re: [coreboot] Add Support for Gigabyte GA-MA790XT-UD4P
by Paul Menzel 14 Apr '12

14 Apr '12

Dear Ken, first off topic. 0. The spelling is coreboot, i. e. all lowercase. 1. Please do not send HTML message to mailing lists [1]. 2. Using Gmail Web interface the down side is it wraps line automatically which is bad if you paste stuff. Since they will not fix that, you should think about using a mail program. Am Freitag, den 13.04.2012, 23:31 -0500 schrieb Ken Phillis Jr: > Just another board support request... If there's any other information that > is required, please ask me... > > General Board information: > =============================================================================== > Vendor: GIGABYTE > Model: GA-MA790XT-UD4P (rev. 1.0) > Product Page: http://www.gigabyte.us/products/product-page.aspx?pid=3010 > North Bridge: AMD 790X > South Bridge: AMD SB750 […] As Peter wrote, you need to do the port yourself. Two good things though, coreboot folks will help you if you have problems and your components seem to be supported. So if you are willing to spend some time, you should be able to complete that port. Please read the coreboot Wiki. You need to make sure to recover. Is the flash chip socketed on your board? If yes, just get some back up chips, find an already supported board similar to yours, build an image, connect a second system over serial line to capture debugging output and work your way through it. If something fails, just boot the system with your back up flash chip, switch the flash chip and write another (hopefully improved) image to it. We are looking forward to your port! Thanks, Paul [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette

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MB A8N5X // nforce4 chipsets // wake on lan capability
by F M 14 Apr '12

14 Apr '12

Dear Sirs, I am writing to you regarding the above mentionned MB (and most probably on all nForce4 mb's) Wake on lan capabilities. At page : http://www.coreboot.org/ASUS_A8N5X you mention "The on-board ethernet device doesn't seem to support WOL (also not mentioned in the manual)" Please not that i am using this capability with this MB es follows (This is a known 'bug' from Nvidia nforce4 chipsets): If your ethernet's MAC address is *00:AB:34:FE:67:CD for exemple, you will need to type the address the other way round to wake your computer using wol. You will have to type "wakeonlan CD:67:FE:34:AB:00″ in a terminal. It of course also works through the internet. Brgds Franck *

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Re: [coreboot] CoreBoot: Add Support for Gigabyte GA-MA790XT-UD4P
by Peter Stuge 14 Apr '12

14 Apr '12

Ken Phillis Jr wrote: > Just another board support request... This is not really something compatible with the coreboot community development model. If you need the board supported you have to do it yourself. //Peter

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New patch to review for coreboot: f3befe2 nvramtool: Allow spaces in enumeration names
by Patrick Georgi 14 Apr '12

14 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/901 -gerrit commit f3befe21fc8542342f3c08ba7b2061cfcc661065 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Apr 14 16:21:39 2012 +0200 nvramtool: Allow spaces in enumeration names Change-Id: Id526e74f06fb15d4692d7b6edc8b5863f2d42c50 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/nvramtool/accessors/layout-text.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index 5f7cade..cbe698c 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -149,7 +149,7 @@ static const char enums_line_regex[] = /* followed by one or more whitespace characters */ "[[:space:]]+" /* followed by a chunk of nonwhitespace for text field */ - "([^[:space:]]+)" + "([[:print:]]*[^[:space:]])" /* followed by optional whitespace */ "[[:space:]]*$";

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New patch to review for coreboot: 9a258e6 cmos.layout: Remove invalid warning
by Vikram Narayanan 14 Apr '12

14 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/899 -gerrit commit 9a258e6907d235411c5069778923535467f76d1f Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:51:53 2012 +0530 cmos.layout: Remove invalid warning "This file must be in UNIX format" is not valid anymore. Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/mainboard/intel/xe7501devkit/cmos.layout | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout index baae5eb..b8fbebe 100644 --- a/src/mainboard/intel/xe7501devkit/cmos.layout +++ b/src/mainboard/intel/xe7501devkit/cmos.layout @@ -1,4 +1,3 @@ -# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: # "Error - Name is an invalid identifier in line" entries

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New patch to review for coreboot: c65489f nvramtool: Unify nvramtool and build_opt_tbl
by Vikram Narayanan 14 Apr '12

14 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/898 -gerrit commit c65489f0b556a1e57adade6da8fdbcc06e5deeab Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:25:13 2012 +0530 nvramtool: Unify nvramtool and build_opt_tbl As cmos.layout parsing capabilities are already there in nvramtool, use those than using build_opt_tbl.c. Add binary and header file generation in nvramtool. Make appropriate changes to Makefile.inc. Change-Id: Iaf3f5d4f51451aeb33c92800a0c895045f2388cf Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/arch/x86/Makefile.inc | 16 +- util/nvramtool/accessors/layout-text.c | 242 ++++++++++++++++++++++++++++++++ util/nvramtool/accessors/layout-text.h | 2 + util/nvramtool/cli/nvramtool.c | 18 +++- util/nvramtool/cli/opts.c | 9 +- util/nvramtool/cli/opts.h | 4 +- util/nvramtool/common.c | 2 + util/nvramtool/layout.h | 8 +- 8 files changed, 286 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8783d4b..6d9bdaf 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -128,18 +128,18 @@ bootsplash.jpg-type := bootsplash ####################################################################### # i386 specific tools +NVRAMTOOL:=$(obj)/nvramtool -$(OPTION_TABLE_H): $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $@ +$(NVRAMTOOL): $(objutil)/nvramtool/nvramtool + cp $< $@ -$(obj)/cmos_layout.bin: $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout +$(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --binary $@ + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@ -$(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) $< -o $@ +$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout + @printf " OPTION $(subst $(obj)/,,$(@))\n" + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ ####################################################################### # Build the coreboot_ram (stage 2) diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index 5f7cade..f656b22 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -1,6 +1,12 @@ /*****************************************************************************\ * layout-text.c ***************************************************************************** + * Copyright (C) 2012, Vikram Narayanan + * Unified build_opt_tbl and nvramtool + * build_opt_tbl.c + * Copyright (C) 2003 Eric Biederman (ebiederm(a)xmission.com) + * Copyright (C) 2007-2010 coresystems GmbH + * * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. * Written by Dave Peterson <dsp(a)llnl.gov> <dave_peterson(a)pobox.com>. @@ -186,6 +192,7 @@ static int line_num; static const char *layout_filename = NULL; +#define ALIGN(x) (x += (4 - (x % 4))) /**************************************************************************** * set_layout_filename * @@ -218,6 +225,241 @@ void get_layout_from_file(void) fclose(f); } +static int is_ident_digit(int c) +{ + int result; + switch(c) { + case '0': case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + case '8': case '9': + result = 1; + break; + default: + result = 0; + break; + } + return result; +} + +static int is_ident_nondigit(int c) +{ + int result; + switch(c) { + case 'A': case 'B': case 'C': case 'D': + case 'E': case 'F': case 'G': case 'H': + case 'I': case 'J': case 'K': case 'L': + case 'M': case 'N': case 'O': case 'P': + case 'Q': case 'R': case 'S': case 'T': + case 'U': case 'V': case 'W': case 'X': + case 'Y': case 'Z': + case 'a': case 'b': case 'c': case 'd': + case 'e': case 'f': case 'g': case 'h': + case 'i': case 'j': case 'k': case 'l': + case 'm': case 'n': case 'o': case 'p': + case 'q': case 'r': case 's': case 't': + case 'u': case 'v': case 'w': case 'x': + case 'y': case 'z': + case '_': + result = 1; + break; + default: + result = 0; + break; + } + return result; +} + +static int is_ident(char *str) +{ + int result; + int ch; + ch = *str; + result = 0; + if (is_ident_nondigit(ch)) { + do { + str++; + ch = *str; + } while(ch && (is_ident_nondigit(ch) || (is_ident_digit(ch)))); + result = (ch == '\0'); + } + return result; +} + +int write_cmos_layout_bin(FILE *f) +{ + const cmos_entry_t *cmos_entry; + const cmos_enum_t *cmos_enum; + cmos_checksum_layout_t layout; + struct cmos_option_table table; + struct cmos_entries entry; + struct cmos_enums cenum; + struct cmos_checksum csum; + size_t sum = 0; + int len; + + for (cmos_entry = first_cmos_entry(); cmos_entry != NULL; + cmos_entry = next_cmos_entry(cmos_entry)) { + + if (cmos_entry == first_cmos_entry()) { + sum += sizeof(table); + table.header_length = sizeof(table); + table.tag = LB_TAG_CMOS_OPTION_TABLE; + + if (fwrite((char *)&table, sizeof(table), 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + memset(&entry, 0, sizeof(entry)); + entry.tag = LB_TAG_OPTION; + entry.config = cmos_entry->config; + entry.config_id = (uint32_t)cmos_entry->config_id; + entry.bit = cmos_entry->bit; + entry.length = cmos_entry->length; + + if (!is_ident((char *)cmos_entry->name)) { + fprintf(stderr, + "Error - Name %s is an invalid identifier\n", + cmos_entry->name); + goto err; + } + + memcpy(entry.name, cmos_entry->name, strlen(cmos_entry->name)); + entry.name[strlen(cmos_entry->name)] = '\0'; + len = strlen(cmos_entry->name) + 1; + + if (len % 4) + ALIGN(len); + + entry.size = sizeof(entry) - CMOS_MAX_NAME_LENGTH + len; + sum += entry.size; + if (fwrite((char *)&entry, entry.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + for (cmos_enum = first_cmos_enum(); + cmos_enum != NULL; cmos_enum = next_cmos_enum(cmos_enum)) { + memset(&cenum, 0, sizeof(cenum)); + cenum.tag = LB_TAG_OPTION_ENUM; + memcpy(cenum.text, cmos_enum->text, strlen(cmos_enum->text)); + cenum.text[strlen(cmos_enum->text)] = '\0'; + len = strlen((char *)cenum.text) + 1; + + if (len % 4) + ALIGN(len); + + cenum.config_id = cmos_enum->config_id; + cenum.value = cmos_enum->value; + cenum.size = sizeof(cenum) - CMOS_MAX_TEXT_LENGTH + len; + sum += cenum.size; + if (fwrite((char *)&cenum, cenum.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + layout.summed_area_start = cmos_checksum_start; + layout.summed_area_end = cmos_checksum_end; + layout.checksum_at = cmos_checksum_index; + checksum_layout_to_bits(&layout); + + csum.tag = LB_TAG_OPTION_CHECKSUM; + csum.size = sizeof(csum); + csum.range_start = layout.summed_area_start; + csum.range_end = layout.summed_area_end; + csum.location = layout.checksum_at; + csum.type = CHECKSUM_PCBIOS; + sum += csum.size; + + if (fwrite((char *)&csum, csum.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + + if (fseek(f, sizeof(table.tag), SEEK_SET) != 0) { + perror("Error while seeking"); + goto err; + } + + if (fwrite((char *)&sum, sizeof(table.tag), 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + return sum; + +err: + fclose(f); + exit(1); +} + +void write_cmos_output_bin(const char *binary_filename) +{ + FILE *fp; + + if ((fp = fopen(binary_filename, "wb")) == NULL) { + fprintf(stderr, + "%s: Can not open file %s for writing: " + "%s\n", prog_name, binary_filename, strerror(errno)); + exit(1); + } + write_cmos_layout_bin(fp); + fclose(fp); +} + +void write_cmos_layout_header(const char *header_filename) +{ + FILE *fp; + const cmos_entry_t *cmos_entry; + cmos_checksum_layout_t layout; + + if ((fp = fopen(header_filename, "w+")) == NULL) { + fprintf(stderr, + "%s: Can't open file %s for writing: %s\n", + prog_name, header_filename, strerror(errno)); + exit(1); + } + + fprintf(fp, "/**\n * This is an autogenerated file. Do not EDIT.\n" + " * All changes made to this file will be lost.\n" + " * See mainboard's cmos.layout file.\n */\n" + "\n#ifndef __OPTION_TABLE_H\n" + "#define __OPTION_TABLE_H\n\n"); + + for (cmos_entry = first_cmos_entry(); cmos_entry != NULL; + cmos_entry = next_cmos_entry(cmos_entry)) { + + if (!is_ident((char *)cmos_entry->name)) { + fprintf(stderr, + "Error - Name %s is an invalid identifier\n", + cmos_entry->name); + fclose(fp); + exit(1); + } + + fprintf(fp, "#define CMOS_VSTART_%s\t%d\n", + cmos_entry->name, cmos_entry->bit); + fprintf(fp, "#define CMOS_VLEN_%s\t%d\n", + cmos_entry->name, cmos_entry->length); + } + + layout.summed_area_start = cmos_checksum_start; + layout.summed_area_end = cmos_checksum_end; + layout.checksum_at = cmos_checksum_index; + checksum_layout_to_bits(&layout); + + fprintf(fp, "\n#define LB_CKS_RANGE_START %d\n", + layout.summed_area_start / 8); + fprintf(fp, "#define LB_CKS_RANGE_END %d\n", + layout.summed_area_end / 8); + fprintf(fp, "#define LB_CKS_LOC %d\n", + layout.checksum_at / 8); + fprintf(fp, "\n#endif /* __OPTION_TABLE_H */\n"); + + fclose(fp); +} /**************************************************************************** * write_cmos_layout * diff --git a/util/nvramtool/accessors/layout-text.h b/util/nvramtool/accessors/layout-text.h index 21997e9..e6b4397 100644 --- a/util/nvramtool/accessors/layout-text.h +++ b/util/nvramtool/accessors/layout-text.h @@ -37,5 +37,7 @@ void set_layout_filename(const char filename[]); void get_layout_from_file(void); void write_cmos_layout(FILE * f); +void write_cmos_output_bin(const char *binary_filename); +void write_cmos_layout_header(const char *header_filename); #endif /* LAYOUT_FILE_H */ diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index bcb10bb..f3fb16d 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -62,6 +62,8 @@ static void op_write_cmos_dump(void); static void op_read_cmos_dump(void); static void op_show_cmos_hex_dump(void); static void op_show_cmos_dumpfile(void); +static void op_write_cmos_layout_bin(void); +static void op_write_cmos_layout_header(void); static int list_one_param(const char name[], int show_name); static int list_all_params(void); static void list_param_enums(const char name[]); @@ -86,9 +88,23 @@ static const op_fn_t op_fns[] = { op_show_version, op_write_cmos_dump, op_read_cmos_dump, op_show_cmos_hex_dump, - op_show_cmos_dumpfile + op_show_cmos_dumpfile, + op_write_cmos_layout_bin, + op_write_cmos_layout_header }; +static void op_write_cmos_layout_bin(void) +{ + get_layout_from_file(); + write_cmos_output_bin(nvramtool_op.param); +} + +static void op_write_cmos_layout_header(void) +{ + get_layout_from_file(); + write_cmos_layout_header(nvramtool_op.param); +} + static const hexdump_format_t cmos_dump_format = { 16, 2, "", " | ", " ", " | ", '.' }; diff --git a/util/nvramtool/cli/opts.c b/util/nvramtool/cli/opts.c index 4949649..8e920e8 100644 --- a/util/nvramtool/cli/opts.c +++ b/util/nvramtool/cli/opts.c @@ -41,7 +41,7 @@ static void register_op_modifier(nvramtool_op_modifier_t mod, char mod_param[]); static void resolve_op_modifiers(void); static void sanity_check_args(void); -static const char getopt_string[] = "-ab:B:c::C:dD:e:hil::np:r:tvw:xX:y:Y"; +static const char getopt_string[] = "-ab:B:c::C:dD:e:hH:iL:l::np:r:tvw:xX:y:Y"; /**************************************************************************** * parse_nvramtool_args @@ -100,6 +100,9 @@ void parse_nvramtool_args(int argc, char *argv[]) case 'h': register_op(&op_found, NVRAMTOOL_OP_SHOW_USAGE, NULL); break; + case 'H': + register_op(&op_found, NVRAMTOOL_OP_WRITE_HEADER_FILE, optarg); + break; case 'i': register_op(&op_found, NVRAMTOOL_OP_CMOS_SET_PARAMS_STDIN, NULL); @@ -108,6 +111,10 @@ void parse_nvramtool_args(int argc, char *argv[]) register_op(&op_found, NVRAMTOOL_OP_LBTABLE_SHOW_INFO, handle_optional_arg(argc, argv)); break; + case 'L': + register_op(&op_found, NVRAMTOOL_OP_WRITE_BINARY_FILE, + optarg); + break; case 'n': register_op_modifier(NVRAMTOOL_MOD_SHOW_VALUE_ONLY, NULL); diff --git a/util/nvramtool/cli/opts.h b/util/nvramtool/cli/opts.h index f46f254..a011ef1 100644 --- a/util/nvramtool/cli/opts.h +++ b/util/nvramtool/cli/opts.h @@ -48,7 +48,9 @@ typedef enum { NVRAMTOOL_OP_SHOW_VERSION = 0, NVRAMTOOL_OP_WRITE_CMOS_DUMP, NVRAMTOOL_OP_READ_CMOS_DUMP, NVRAMTOOL_OP_SHOW_CMOS_HEX_DUMP, - NVRAMTOOL_OP_SHOW_CMOS_DUMPFILE + NVRAMTOOL_OP_SHOW_CMOS_DUMPFILE, + NVRAMTOOL_OP_WRITE_BINARY_FILE, + NVRAMTOOL_OP_WRITE_HEADER_FILE } nvramtool_op_t; typedef struct { diff --git a/util/nvramtool/common.c b/util/nvramtool/common.c index 91fcccc..15f8b0d 100644 --- a/util/nvramtool/common.c +++ b/util/nvramtool/common.c @@ -98,6 +98,8 @@ void usage(FILE * outfile) "VALUE.\n" " -l [ARG]: Show coreboot table info for ARG, or " "all ARG choices.\n" + " -L OUTPUT_BIN Write CMOS layout file in binary format\n" + " -H OUTPUT_HDR Write CMOS layout file in header format\n" " -d: Show low-level dump of coreboot table.\n" " -Y: Show CMOS layout info.\n" " -b OUTPUT_FILE: Dump CMOS memory contents to file.\n" diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h index d99275c..39a4159 100644 --- a/util/nvramtool/layout.h +++ b/util/nvramtool/layout.h @@ -46,10 +46,10 @@ #define LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE (LAYOUT_RESULT_START + 9) typedef enum { - CMOS_ENTRY_ENUM, - CMOS_ENTRY_HEX, - CMOS_ENTRY_STRING, - CMOS_ENTRY_RESERVED + CMOS_ENTRY_ENUM = 0x65, + CMOS_ENTRY_HEX = 0x68, + CMOS_ENTRY_STRING = 0x96, + CMOS_ENTRY_RESERVED = 0x72, } cmos_entry_config_t; /* This represents a CMOS parameter. */

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coreboot April 2012