coreboot April 2012

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Patch merged into coreboot/master: d0cf472 Fix the blank in acpi_tables.c
by gerrit＠coreboot.org 18 Apr '12

18 Apr '12

the following patch was just integrated into master: commit d0cf472c8f7aaebda3706d5e7ff03440437b749d Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 11:28:07 2012 +0800 Fix the blank in acpi_tables.c Change-Id: I65d50616e49802b7bb13f02369c4898fa4a238a4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Apr 18 13:05:28 2012, giving +2 See http://review.coreboot.org/903 for details. -gerrit

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Patch set updated for coreboot: 060fba7 S3: Use old heap during normal boot
by Zheng Bao 18 Apr '12

18 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/904 -gerrit commit 060fba770b8e067defb91ed7ba266fced87e438a Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 16:59:53 2012 +0800 S3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem. Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index 071c73c..cd23110 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" +#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ #define BIOS_HEAP_SIZE 0x20000 #define BSP_STACK_BASE_ADDR 0x30000 diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6bba7ca..e60673e 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -40,6 +40,7 @@ #include <arch/io.h> #include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> +#include <arch/acpi.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -250,11 +251,15 @@ UINT32 GetHeapBase( AMD_CONFIG_PARAMS *StdHeader ) { - UINT32 high_heap; + UINT32 heap; - high_heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ + else + heap = BIOS_HEAP_START_ADDRESS; /* low mem */ - return high_heap; + return heap; } UINT32

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Patch set updated for coreboot: c076afd s3: Use old heap during normal boot
by Zheng Bao 18 Apr '12

18 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/904 -gerrit commit c076afd137fda12ace65ada0b3dd95c14ea88a1e Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 12:56:09 2012 +0800 s3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem. Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index 071c73c..cd23110 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" +#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ #define BIOS_HEAP_SIZE 0x20000 #define BSP_STACK_BASE_ADDR 0x30000 diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6bba7ca..4a53d6c 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -40,6 +40,7 @@ #include <arch/io.h> #include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> +#include <arch/acpi.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -252,7 +253,11 @@ UINT32 GetHeapBase( { UINT32 high_heap; - high_heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + high_heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + else + high_heap = BIOS_HEAP_START_ADDRESS; return high_heap; }

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New patch to review for coreboot: 0e51575 s3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem.
by Zheng Bao 18 Apr '12

18 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/904 -gerrit commit 0e51575316977452449f4353d94b5244770990f0 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 12:54:20 2012 +0800 s3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem. Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index 071c73c..cd23110 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" +#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ #define BIOS_HEAP_SIZE 0x20000 #define BSP_STACK_BASE_ADDR 0x30000 diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6bba7ca..4a53d6c 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -40,6 +40,7 @@ #include <arch/io.h> #include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> +#include <arch/acpi.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -252,7 +253,11 @@ UINT32 GetHeapBase( { UINT32 high_heap; - high_heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + high_heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + else + high_heap = BIOS_HEAP_START_ADDRESS; return high_heap; }

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Patch set updated for coreboot: a99159b Leverage the Pstate table created by AGESA.
by Zheng Bao 18 Apr '12

18 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/884 -gerrit commit a99159bd88b984957714dc8f123a8126b5e9404a Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 12 11:27:26 2012 +0800 Leverage the Pstate table created by AGESA. The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts from 0. The dsdt should be aligned with that. This feature has only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi/cpstate.asl | 74 -------------- src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/dsdt.asl | 48 +++++++--- src/mainboard/amd/inagua/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/inagua/acpi_tables.c | 8 +- src/mainboard/amd/inagua/dsdt.asl | 24 ++++- src/mainboard/amd/persimmon/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/persimmon/acpi_tables.c | 8 +- src/mainboard/amd/persimmon/dsdt.asl | 24 ++++- src/mainboard/amd/south_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/south_station/acpi_tables.c | 12 +- src/mainboard/amd/south_station/dsdt.asl | 24 ++++- src/mainboard/amd/torpedo/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/torpedo/dsdt.asl | 18 ++-- src/mainboard/amd/union_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/union_station/acpi_tables.c | 12 +- src/mainboard/amd/union_station/dsdt.asl | 24 ++++- src/mainboard/asrock/e350m1/acpi/cpstate.asl | 75 -------------- src/mainboard/asrock/e350m1/acpi_tables.c | 12 +- src/mainboard/asrock/e350m1/dsdt.asl | 24 ++++- src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 75 -------------- src/mainboard/supermicro/h8qgi/acpi_tables.c | 8 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 115 +++++++++++----------- 23 files changed, 222 insertions(+), 746 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl deleted file mode 100644 index 64b3f16..0000000 --- a/src/mainboard/amd/dinar/acpi/cpstate.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 1b80b18..a6382fe 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -297,7 +297,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -305,11 +306,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 1cbb05e..501ec78 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -51,37 +51,61 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x0 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } + Processor( + C004, /* name space name */ + 4, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C005, /* name space name */ + 5, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C006, /* name space name */ + 6, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C007, /* name space name */ + 7, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h. */ diff --git a/src/mainboard/amd/inagua/acpi/cpstate.asl b/src/mainboard/amd/inagua/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/inagua/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 6c1acc8..923d0bf 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -264,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -273,12 +274,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 361adbb..7708676 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/acpi/cpstate.asl b/src/mainboard/amd/persimmon/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/persimmon/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 043ba3c..4a44a5a 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -264,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -273,12 +274,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index b480c33..bd9ce74 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/acpi/cpstate.asl b/src/mainboard/amd/south_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/south_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 8d32614..f430087 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -263,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -271,12 +273,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 7f03a43..b18bcb2 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/acpi/cpstate.asl b/src/mainboard/amd/torpedo/acpi/cpstate.asl deleted file mode 100755 index 5eca9cc..0000000 --- a/src/mainboard/amd/torpedo/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index a8a731d..758fba5 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -51,36 +51,32 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/acpi/cpstate.asl b/src/mainboard/amd/union_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/union_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index fc26df2..e32a42b 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -263,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -271,12 +273,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index fb2cfe8..7e49fd4 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/acpi/cpstate.asl b/src/mainboard/asrock/e350m1/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/asrock/e350m1/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index fc26df2..e32a42b 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -263,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -271,12 +273,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 97533c1..c2ea1fb 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index ac9acd6..77c0772 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -297,7 +297,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -305,11 +306,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 137a90d..2955eea 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -65,69 +65,68 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - P000, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0x00, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - //#include "acpi/cpstate.asl" } - Processor(P001, 0x01, 0x00000000, 0x00) {} - Processor(P002, 0x02, 0x00000000, 0x00) {} - Processor(P003, 0x03, 0x00000000, 0x00) {} - Processor(P004, 0x04, 0x00000000, 0x00) {} - Processor(P005, 0x05, 0x00000000, 0x00) {} - Processor(P006, 0x06, 0x00000000, 0x00) {} - Processor(P007, 0x07, 0x00000000, 0x00) {} - Processor(P008, 0x08, 0x00000000, 0x00) {} - Processor(P009, 0x09, 0x00000000, 0x00) {} - Processor(P00A, 0x0A, 0x00000000, 0x00) {} - Processor(P00B, 0x0B, 0x00000000, 0x00) {} - Processor(P00C, 0x0C, 0x00000000, 0x00) {} - Processor(P00D, 0x0D, 0x00000000, 0x00) {} - Processor(P00E, 0x0E, 0x00000000, 0x00) {} - Processor(P00F, 0x0F, 0x00000000, 0x00) {} - Processor(P010, 0x10, 0x00000000, 0x00) {} - Processor(P011, 0x11, 0x00000000, 0x00) {} - Processor(P012, 0x12, 0x00000000, 0x00) {} - Processor(P013, 0x13, 0x00000000, 0x00) {} - Processor(P014, 0x14, 0x00000000, 0x00) {} - Processor(P015, 0x15, 0x00000000, 0x00) {} - Processor(P016, 0x16, 0x00000000, 0x00) {} - Processor(P017, 0x17, 0x00000000, 0x00) {} - Processor(P018, 0x18, 0x00000000, 0x00) {} - Processor(P019, 0x19, 0x00000000, 0x00) {} - Processor(P01A, 0x1A, 0x00000000, 0x00) {} - Processor(P01B, 0x1B, 0x00000000, 0x00) {} - Processor(P01C, 0x1C, 0x00000000, 0x00) {} - Processor(P01D, 0x1D, 0x00000000, 0x00) {} - Processor(P01E, 0x1E, 0x00000000, 0x00) {} - Processor(P01F, 0x1F, 0x00000000, 0x00) {} - Processor(P020, 0x20, 0x00000000, 0x00) {} - Processor(P021, 0x21, 0x00000000, 0x00) {} - Processor(P022, 0x22, 0x00000000, 0x00) {} - Processor(P023, 0x23, 0x00000000, 0x00) {} - Processor(P024, 0x24, 0x00000000, 0x00) {} - Processor(P025, 0x25, 0x00000000, 0x00) {} - Processor(P026, 0x26, 0x00000000, 0x00) {} - Processor(P027, 0x27, 0x00000000, 0x00) {} - Processor(P028, 0x28, 0x00000000, 0x00) {} - Processor(P029, 0x29, 0x00000000, 0x00) {} - Processor(P02A, 0x2A, 0x00000000, 0x00) {} - Processor(P02B, 0x2B, 0x00000000, 0x00) {} - Processor(P02C, 0x2C, 0x00000000, 0x00) {} - Processor(P02D, 0x2D, 0x00000000, 0x00) {} - Processor(P02E, 0x2E, 0x00000000, 0x00) {} - Processor(P02F, 0x2F, 0x00000000, 0x00) {} - Alias (P000, CPU0) - Alias (P001, CPU1) - Alias (P002, CPU2) - Alias (P003, CPU3) - Alias (P004, CPU4) - Alias (P005, CPU5) - Alias (P006, CPU6) - Alias (P007, CPU7) - Alias (P008, CPU8) + Processor(C001, 0x01, 0x00000000, 0x00) {} + Processor(C002, 0x02, 0x00000000, 0x00) {} + Processor(C003, 0x03, 0x00000000, 0x00) {} + Processor(C004, 0x04, 0x00000000, 0x00) {} + Processor(C005, 0x05, 0x00000000, 0x00) {} + Processor(C006, 0x06, 0x00000000, 0x00) {} + Processor(C007, 0x07, 0x00000000, 0x00) {} + Processor(C008, 0x08, 0x00000000, 0x00) {} + Processor(C009, 0x09, 0x00000000, 0x00) {} + Processor(C00A, 0x0A, 0x00000000, 0x00) {} + Processor(C00B, 0x0B, 0x00000000, 0x00) {} + Processor(C00C, 0x0C, 0x00000000, 0x00) {} + Processor(C00D, 0x0D, 0x00000000, 0x00) {} + Processor(C00E, 0x0E, 0x00000000, 0x00) {} + Processor(C00F, 0x0F, 0x00000000, 0x00) {} + Processor(C010, 0x10, 0x00000000, 0x00) {} + Processor(C011, 0x11, 0x00000000, 0x00) {} + Processor(C012, 0x12, 0x00000000, 0x00) {} + Processor(C013, 0x13, 0x00000000, 0x00) {} + Processor(C014, 0x14, 0x00000000, 0x00) {} + Processor(C015, 0x15, 0x00000000, 0x00) {} + Processor(C016, 0x16, 0x00000000, 0x00) {} + Processor(C017, 0x17, 0x00000000, 0x00) {} + Processor(C018, 0x18, 0x00000000, 0x00) {} + Processor(C019, 0x19, 0x00000000, 0x00) {} + Processor(C01A, 0x1A, 0x00000000, 0x00) {} + Processor(C01B, 0x1B, 0x00000000, 0x00) {} + Processor(C01C, 0x1C, 0x00000000, 0x00) {} + Processor(C01D, 0x1D, 0x00000000, 0x00) {} + Processor(C01E, 0x1E, 0x00000000, 0x00) {} + Processor(C01F, 0x1F, 0x00000000, 0x00) {} + Processor(C020, 0x20, 0x00000000, 0x00) {} + Processor(C021, 0x21, 0x00000000, 0x00) {} + Processor(C022, 0x22, 0x00000000, 0x00) {} + Processor(C023, 0x23, 0x00000000, 0x00) {} + Processor(C024, 0x24, 0x00000000, 0x00) {} + Processor(C025, 0x25, 0x00000000, 0x00) {} + Processor(C026, 0x26, 0x00000000, 0x00) {} + Processor(C027, 0x27, 0x00000000, 0x00) {} + Processor(C028, 0x28, 0x00000000, 0x00) {} + Processor(C029, 0x29, 0x00000000, 0x00) {} + Processor(C02A, 0x2A, 0x00000000, 0x00) {} + Processor(C02B, 0x2B, 0x00000000, 0x00) {} + Processor(C02C, 0x2C, 0x00000000, 0x00) {} + Processor(C02D, 0x2D, 0x00000000, 0x00) {} + Processor(C02E, 0x2E, 0x00000000, 0x00) {} + Processor(C02F, 0x2F, 0x00000000, 0x00) {} + Alias (C000, CPU0) + Alias (C001, CPU1) + Alias (C002, CPU2) + Alias (C003, CPU3) + Alias (C004, CPU4) + Alias (C005, CPU5) + Alias (C006, CPU6) + Alias (C007, CPU7) + Alias (C008, CPU8) } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h */

1 0

Patch set updated for coreboot: 6a28f1e Fix messy code in ALIB
by Zheng Bao 18 Apr '12

18 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885 -gerrit commit 6a28f1e5cf0a7bb94e57545533aa08dccd08bffe Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:48:50 2012 +0800 Fix messy code in ALIB Fix the copy-paste typo in ALIB talbe creation. ssdt is useless here. Change-Id: I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 4 ++-- src/mainboard/amd/inagua/acpi_tables.c | 7 +++---- src/mainboard/amd/persimmon/acpi_tables.c | 7 +++---- src/mainboard/amd/south_station/acpi_tables.c | 7 +++---- src/mainboard/amd/union_station/acpi_tables.c | 7 +++---- src/mainboard/asrock/e350m1/acpi_tables.c | 7 +++---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 4 ++-- 7 files changed, 19 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index a6382fe..e2a8a44 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -290,9 +290,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); + acpi_add_table(rsdp, (void *)alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 923d0bf..29a8423 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 4a44a5a..cb415fd 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index f430087..b6c9b9f 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index e32a42b..5c958a0 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index e32a42b..5c958a0 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 77c0772..f6db214 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -290,9 +290,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); + acpi_add_table(rsdp, (void *)alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); }

1 0

New patch to review for coreboot: d0cf472 Fix the blank in acpi_tables.c
by Zheng Bao 18 Apr '12

18 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/903 -gerrit commit d0cf472c8f7aaebda3706d5e7ff03440437b749d Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 11:28:07 2012 +0800 Fix the blank in acpi_tables.c Change-Id: I65d50616e49802b7bb13f02369c4898fa4a238a4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bimini_fam10/acpi_tables.c | 18 +++++++++--------- src/mainboard/amd/dinar/acpi_tables.c | 12 ++++++------ src/mainboard/amd/inagua/acpi_tables.c | 2 +- src/mainboard/amd/mahogany_fam10/acpi_tables.c | 16 ++++++++-------- .../amd/serengeti_cheetah_fam10/acpi_tables.c | 18 +++++++++--------- src/mainboard/amd/south_station/acpi_tables.c | 2 +- src/mainboard/amd/tilapia_fam10/acpi_tables.c | 18 +++++++++--------- src/mainboard/amd/torpedo/acpi_tables.c | 16 ++++++++-------- 8 files changed, 51 insertions(+), 51 deletions(-) diff --git a/src/mainboard/amd/bimini_fam10/acpi_tables.c b/src/mainboard/amd/bimini_fam10/acpi_tables.c index 7be5aaa..d7a1f24 100644 --- a/src/mainboard/amd/bimini_fam10/acpi_tables.c +++ b/src/mainboard/amd/bimini_fam10/acpi_tables.c @@ -128,7 +128,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -137,14 +137,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -155,7 +155,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -163,7 +163,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -171,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -179,7 +179,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -187,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)current; memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) } else { c = (u8) ('A' + i - 1 - 6); } - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt ssdtx = (acpi_header_t *)current; switch (sysconf.hcid[i]) { diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index e2a8a44..db01d79 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -237,7 +237,7 @@ unsigned long write_acpi_tables(unsigned long start) * We explicitly add these tables later on: */ #ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -246,7 +246,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -254,14 +254,14 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -273,7 +273,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -285,7 +285,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = (current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 29a8423..a4504d4 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c index 1f7c2f7..7e89881 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -144,7 +144,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -153,14 +153,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -171,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -179,7 +179,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -187,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -195,7 +195,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -203,7 +203,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); ssdt = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 87cadc0..2c112f9 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -198,7 +198,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -207,14 +207,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -225,7 +225,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -233,7 +233,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n", current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -241,7 +241,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -249,7 +249,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -257,7 +257,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)current; memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); @@ -287,7 +287,7 @@ unsigned long write_acpi_tables(unsigned long start) else { c = (u8) ('A' + i - 1 - 6); } - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index b6c9b9f..5c958a0 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index 4e10d5b..c44fe33 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -128,7 +128,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -137,14 +137,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -155,7 +155,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -163,7 +163,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -171,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -179,7 +179,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -187,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)current; memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) } else { c = (u8) ('A' + i - 1 - 6); } - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt ssdtx = (acpi_header_t *)current; switch (sysconf.hcid[i]) { diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 9cad9fa..2e04c57 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -164,7 +164,7 @@ unsigned long write_acpi_tables(unsigned long start) * We explicitly add these tables later on: */ #if 0 // Don't need HPET table. - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -173,7 +173,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -188,7 +188,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ((acpi_header_t *)current)->length; /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -200,7 +200,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -212,7 +212,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -234,7 +234,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -243,14 +243,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t);

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Re: [coreboot] [geda-user] Re: Dual SPI Flash adapter
by Oliver Schinagl 18 Apr '12

18 Apr '12

Hi, I've threw out half the schema and incorporated the dual FET switch. So far only the schema, any input appreciated! I think worked in Peter's suggestions. I added two resistors, S1 and S2 who's purpouse is to bypass the FET switch if one would choose not to use one, I figured using a really small SMD footprint should work allright as a solder bridge? Only downside is you'd have two 10k resistors when using a resistor network. When using a 100k resistor network that's less of an issue, but I only have some salvaged 103 ones :p One could always only solder two SMD resistors where the resistor network lives of course. I'll work on the PCB the next few days, if people don't want me to throw everything around again :) Oliver On 04/05/12 13:40, Oliver Schinagl wrote: > On 04/05/12 06:16, Peter Stuge wrote: >> Peter Stuge wrote: >>> It's a mux on the CS/ line of two SPI flash chips. >> >> Oliver, I really think you should add a real mux to the PCB, and have >> that be "remote controlled" by the jumper or mechanical switch. > Why is that recommended? If using a jumper cap, it shouldn't be able to > go wrong? Chip1 active, none active, chip2 active? To which I can't > understand why that extra component would help. > > Not that I don't believe you :p I know nothing of this stuff, but the > goal was to make this board as simple as possible. >> >> It's a small board but I think it can be done. The design I used on > I think it would make the board a little bigger again, or actually the > SOIC8 3306 could fit on top between the connector, so I think it may be > possible using the same size :) Dunno if routing will be still possible :p > >> the M57SLI (see http://stuge.se/m57sli/ if curious) is shown in the > > Now the left schematic is what your motherboard does? The top right is > what's the smallest component count and the ride side is with an easier > switch, but higher component count? > > >> attachment, but I suggest to make some improvements: >> >> 1. change things around so that the switch common is GND >> 2. look for little logic to reduce component count >> >> The attachment has two suggested circuits using little logic, one >> with only two components (3306+resistorpack) but which then requires >> a SPDT switch, and one with three components (3306+1g14+resistorpack) >> but which only requires shorting a jumper to ground to switch between >> flash chips. > Even though I am sure that the 3306 method would be better, I don't > understand quite how and why it's needed. Also I haven't found a 3306 on > any of my pcb's to scavenge one off :) I'd reccon the simpler design > would allow for easier adaption? > > Finally, I notice you use 100k resistorpacks, but in a previous message > I recall you mentioning anything between 1k and 10k should be good? (I > happen to have a 103 resistor pack on a pcb here is my wondering :) >> >> >> //Peter >

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Binary blobs in the source tree (was: Re: New patch to review for coreboot: e4fc528 Add the memory reference code binary for sandybridge chipsets)
by Carl-Daniel Hailfinger 17 Apr '12

17 Apr '12

Am 15.04.2012 04:57 schrieb ron minnich: > On Sat, Apr 14, 2012 at 3:12 AM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >> I hope this is not going into the main repository, but into some >> separate repository instead. >> Right now we can tell people that all code in our official git >> repository is GPL-compatible, and I'd like to keep it that way. > We maintain GPL V2 compatibility as this is a blob that is placed into > cbfs. There is no linking. It's a slippery slope, though. We call the blob from coreboot and expect it to return to coreboot (whether the return is a JMP/RET/... doesn't matter). Unless I'm mistaken, we've never done that before, and if we do this now in the official tree, it will be very hard to refuse merging chipset init blobs (well, pretty much any init blob), and for some chipset/CPU combinations coreboot may turn into a simple blob aggregator with PCI init. That's a scenario I'm very afraid of. Side note: AFAICS the blob in your patch came without any licensing document. Does Intel allow distributing the blob on/for non-Intel systems? > I don't see it as different from what we do today with microcode, > which has been in the coreboot tree for many years now. While that > code is in "source" form in some sense, it really is a binary blob. We > would not have wanted to force people to maintain all that as as > separate repo. Microcode is conceptually different. It's a stream of bytes you bang into some register, you don't execute it as normal code on your CPU. CPU microcode is like a network card's internal firmware: outside the scope of coreboot. > Hope that helps. I'd like to make sandybridge support as convenient as possible. I heard rumors that the MRC blob is only a stopgap solution because there wasn't sufficient time to write+QA RAM init code for the sandybridge platform, and such code might materialize later. If that rumor is indeed true, the added convenience is only a short-term benefit and I hope we can keep the blob out. However, if there will never be an open source RAM init for sandybridge, we should decide now which types of blobs (if any) are acceptable in the main source tree, and make sure all active developers are aware of the policy. Regards, Carl-Daniel

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Patch merged into coreboot/master: cf2748d lint: tighten whitespace check some more
by gerrit＠coreboot.org 17 Apr '12

17 Apr '12

the following patch was just integrated into master: commit cf2748dfffc75ca94e5397e59e549c1e451b9dcd Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 12 15:23:58 2012 +0200 lint: tighten whitespace check some more Don't test executable files nor object files, even if the former might render the test useless on win32 (executable bit isn't well defined there). Change-Id: Ifb6fc83243289d266f439316c14b6b009f8da5fc Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/890 for details. -gerrit

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coreboot April 2012