coreboot December 2012

coreboot@coreboot.org

30 participants
341 discussions

New patch to review for coreboot: 6fe234f AMD S3: Rename generated s3.rom for make clean
by Zheng Bao 14 Dec '12

14 Dec '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2029 -gerrit commit 6fe234f2851533d2a8ce5fa198143acbaccfd228 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Dec 14 15:43:12 2012 +0800 AMD S3: Rename generated s3.rom for make clean Add prefix coreboot_ to let make clean find it and delete it. Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 1e3309a..1b2cb1f 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -19,14 +19,14 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) -$(obj)/s3.rom: $(obj)/config.h +$(obj)/coreboot_s3nv.rom: $(obj)/config.h echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ cbfs-files-y += s3nv -s3nv-file := $(obj)/s3.rom +s3nv-file := $(obj)/coreboot_s3nv.rom s3nv-position := $(CONFIG_S3_VOLATILE_POS) s3nv-type := raw

1 0

ASRock E350M1: Only costs 66,10 € in Germany
by Paul Menzel 13 Dec '12

13 Dec '12

Dear coreboot folks, just a notice, that the ASRock E350M1 had a price drop in September and currently costs only 66,10 € [1] in Germany. So if you want to get a Christmas present, that might be it. You just need RAM as the CPU is included. Thanks to AMD, Scott and <http://www.se-eng.com/>, coreboot works with the board pretty good [2]. The only problems seem to be resume from suspend not working and the Ethernet device sometimes not enabling during start. Thanks, Paul [1] http://www.guenstiger.de/Preisvergleich/ASRock/E350M1.html?versand=1 [2] http://www.coreboot.org/ASRock_E350M1

4 3

Patch merged into coreboot/master: 9915b37 coreinfo: Build libpayload from coreinfo makefile
by gerrit＠coreboot.org 13 Dec '12

13 Dec '12

the following patch was just integrated into master: commit 9915b37f10828874dcc699bfb0298303fbc356c8 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Nov 30 17:15:36 2012 -0700 coreinfo: Build libpayload from coreinfo makefile Build libpayload and install it in the coreinfo directory. Allows coreinfo to be built with a single make command. Change-Id: I56982265555aae16e482b0a0040989c1f5317423 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/1995 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Dec 10 19:04:28 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Thu Dec 13 10:37:28 2012, giving +2 See http://review.coreboot.org/1995 for details. -gerrit

1 0

Patch merged into coreboot/master: 0b97f29 libpayload: increase the default heap size
by gerrit＠coreboot.org 13 Dec '12

13 Dec '12

the following patch was just integrated into master: commit 0b97f2978f389a51953da11224a525b470ae82b4 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Nov 29 10:18:53 2012 -0700 libpayload: increase the default heap size Coreinfo uses the default heap size and will blow up if the USB keyboard is used. Change-Id: I2ffae330ec34167b2ccfbd4c428e3e8306230f44 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/1980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Marc Jones <marcj303(a)gmail.com> See http://review.coreboot.org/1980 for details. -gerrit

1 0

Patch merged into coreboot/master: 15a2c8f coreinfo: changes to get the USB keyboard working
by gerrit＠coreboot.org 12 Dec '12

12 Dec '12

the following patch was just integrated into master: commit 15a2c8f82769c67684d0a6eac05be48487599dfc Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Dec 5 17:22:47 2012 -0700 coreinfo: changes to get the USB keyboard working A call to usb_initialize() was needed. Also needed to set several curses flags. One to prevent keystrokes echoing to the display, and one to allow extended keystrokes (like the KEY_F(n)) to be seen when calling getch(); Change-Id: I495b42055a54603e4efb92b2845051434d88432d Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/1983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Dec 11 00:31:55 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Wed Dec 12 17:44:05 2012, giving +2 See http://review.coreboot.org/1983 for details. -gerrit

1 0

Patch merged into coreboot/master: e899e51 SB800: Add IMC ROM and fan control.
by gerrit＠coreboot.org 12 Dec '12

12 Dec '12

the following patch was just integrated into master: commit e899e518d88f2f48927fba9006d02ea9e1e5a797 Author: Martin Roth <martin(a)se-eng.com> Date: Wed Dec 5 16:07:11 2012 -0700 SB800: Add IMC ROM and fan control. Add configuration for AMD's IMC ROM and fan registers for cimx/sb800 platforms. - Allows user to add the IMC rom to the build and to configure the location of the "signature" between the allowed positions. - Allows for no fan control, manual setup of SB800 Fan registers, or setup of the IMC fan configuration registers. - Register configuration is done through devicetree.cb. No files need to be added for new platform configuration. - Initial setup is for Persimmon, but may be extended to any cimx/sb800 platform. Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae Signed-off-by: Martin Roth <martin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/1977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Dec 11 14:17:23 2012, giving +1 Build-Tested: build bot (Jenkins) at Tue Dec 11 03:11:26 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Wed Dec 12 17:43:22 2012, giving +2 See http://review.coreboot.org/1977 for details. -gerrit

1 0

Patch merged into coreboot/master: a17fd05 Rename generated hudson_romsig.bin for make clean
by gerrit＠coreboot.org 12 Dec '12

12 Dec '12

the following patch was just integrated into master: commit a17fd056d4b4fb373f7821ccca74a80de14fc618 Author: Martin Roth <martin(a)se-eng.com> Date: Wed Dec 5 16:09:35 2012 -0700 Rename generated hudson_romsig.bin for make clean The file generated when the IMC or XHCI binaries are included in the rom was named $(obj)/hudson_romsig.bin. The problem with this is that it doesn't get deleted when the user does a make clean. changing the name to coreboot_hudson_romsig.bin makes this happen. Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b Signed-off-by: Martin Roth <martin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/1978 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao(a)amd.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Dec 7 01:56:59 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Wed Dec 12 17:42:48 2012, giving +2 See http://review.coreboot.org/1978 for details. -gerrit

1 0

Patch merged into coreboot/master: 3aef7b4 Fix SPI BAR special case in lpc_set_resources
by gerrit＠coreboot.org 12 Dec '12

12 Dec '12

the following patch was just integrated into master: commit 3aef7b4f63b3870e3699d5408d0fb8917c5eb135 Author: Martin Roth <martin(a)se-eng.com> Date: Wed Dec 5 15:50:32 2012 -0700 Fix SPI BAR special case in lpc_set_resources There was already a special case for the SPI base address in lpc_set_resources for southbridge/amd/cimx/sb800 and southbridge/amd/agesa/hudson, but it needed to be modified to keep from killing the IMC rom during initialization. As soon as the BAR is disabled by setting the new base address, the IMC dies. The fix is to make sure it's still enabled when setting the new base address instead of setting the new address then re-enabling it. Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER to more accurately describe what we're using. Change-Id: I216d75b722c4332c239d487111a9880eabf59e91 Signed-off-by: Martin Roth <martin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/1975 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Dec 7 00:55:20 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Dec 7 00:30:25 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Wed Dec 12 17:42:07 2012, giving +2 See http://review.coreboot.org/1975 for details. -gerrit

1 0

Patch merged into coreboot/master: 3316cf2 Claim the SPI bus before writes if the IMC ROM is present
by gerrit＠coreboot.org 12 Dec '12

12 Dec '12

the following patch was just integrated into master: commit 3316cf2ff80f379b609115f375f73ef4b9e7d8f4 Author: Martin Roth <martin(a)se-eng.com> Date: Wed Dec 5 16:22:54 2012 -0700 Claim the SPI bus before writes if the IMC ROM is present The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/1976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Dec 11 14:14:15 2012, giving +2 Build-Tested: build bot (Jenkins) at Tue Dec 11 03:19:33 2012, giving +1 See http://review.coreboot.org/1976 for details. -gerrit

1 0

Re: [coreboot] ASRock E350M1: Only costs 66,10 € in Germany
by Peter Stuge 12 Dec '12

12 Dec '12

Marc Jones wrote: > You may need some of the fixes that have gone into Persimmon. We > have not been maintaining the E350 mainboard. Are those fixes mainboard-specific changes? //Peter

1 0

← Newer
1
...
14
15
16
17
18
19
20
...
35
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2012