coreboot December 2012

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New patch to review for coreboot: a6398fd Add support for Google Parrot Chromebook
by Stefan Reinauer 12 Dec '12

12 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2026 -gerrit commit a6398fd7cb661ab8e66f8c38dad5e1b604efb30c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 16:00:47 2012 -0800 Add support for Google Parrot Chromebook AKA Acer C7 Chromebook See http://www.google.com/intl/en/chrome/devices/acer-c7-chromebook.html for more information. Thank you to Sage Electronic Engineering, LLC for making this possible! http://www.se-eng.com/ Change-Id: Ic4e4d50045a82cbb82e1dea3cd5a04525a648612 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/google/Kconfig | 3 + src/mainboard/google/parrot/Kconfig | 57 ++++ src/mainboard/google/parrot/Makefile.inc | 27 ++ src/mainboard/google/parrot/acpi/chromeos.asl | 25 ++ src/mainboard/google/parrot/acpi/ec.asl | 25 ++ .../google/parrot/acpi/ivybridge_pci_irqs.asl | 69 +++++ src/mainboard/google/parrot/acpi/mainboard.asl | 71 +++++ src/mainboard/google/parrot/acpi/platform.asl | 88 ++++++ .../google/parrot/acpi/sandybridge_pci_irqs.asl | 69 +++++ src/mainboard/google/parrot/acpi/superio.asl | 27 ++ src/mainboard/google/parrot/acpi/thermal.asl | 98 ++++++ src/mainboard/google/parrot/acpi/video.asl | 43 +++ src/mainboard/google/parrot/acpi_tables.c | 268 +++++++++++++++++ src/mainboard/google/parrot/chromeos.c | 167 +++++++++++ src/mainboard/google/parrot/cmos.layout | 139 +++++++++ src/mainboard/google/parrot/devicetree.cb | 105 +++++++ src/mainboard/google/parrot/dsdt.asl | 57 ++++ src/mainboard/google/parrot/ec.c | 82 ++++++ src/mainboard/google/parrot/ec.h | 66 +++++ src/mainboard/google/parrot/fadt.c | 166 +++++++++++ src/mainboard/google/parrot/gpio.h | 279 ++++++++++++++++++ src/mainboard/google/parrot/hda_verb.h | 169 +++++++++++ src/mainboard/google/parrot/mainboard.c | 328 +++++++++++++++++++++ src/mainboard/google/parrot/mainboard_smi.c | 217 ++++++++++++++ src/mainboard/google/parrot/onboard.h | 29 ++ src/mainboard/google/parrot/romstage.c | 307 +++++++++++++++++++ src/mainboard/google/parrot/thermal.h | 31 ++ 27 files changed, 3012 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index cf2fad3..0603566 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -21,11 +21,14 @@ if VENDOR_GOOGLE choice prompt "Mainboard model" +config BOARD_GOOGLE_PARROT + bool "Parrot" config BOARD_GOOGLE_SNOW bool "Snow" endchoice +source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/snow/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig new file mode 100644 index 0000000..e141033 --- /dev/null +++ b/src/mainboard/google/parrot/Kconfig @@ -0,0 +1,57 @@ +if BOARD_GOOGLE_PARROT + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select EC_COMPAL_ENE932 + select BOARD_HAS_FADT + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select HAVE_MAINBOARD_RESOURCES + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select GFXUMA + select CHROMEOS + select EXTERNAL_MRC_BLOB + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default google/parrot + +config MAINBOARD_PART_NUMBER + string + default "Parrot" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0106.rom" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1ae0 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0xc000 + +endif # BOARD_GOOGLE_PARROT diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc new file mode 100644 index 0000000..c4fb74d --- /dev/null +++ b/src/mainboard/google/parrot/Makefile.inc @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-y += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c + +SRC_ROOT = $(src)/mainboard/google/parrot diff --git a/src/mainboard/google/parrot/acpi/chromeos.asl b/src/mainboard/google/parrot/acpi/chromeos.asl new file mode 100644 index 0000000..622b5d9 --- /dev/null +++ b/src/mainboard/google/parrot/acpi/chromeos.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button + Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button + Package() { 0x003, 0, 70, "PantherPoint" }, // firmware write protect +}) + diff --git a/src/mainboard/google/parrot/acpi/ec.asl b/src/mainboard/google/parrot/acpi/ec.asl new file mode 100644 index 0000000..522a0b9 --- /dev/null +++ b/src/mainboard/google/parrot/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include "../ec.h" +#define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI + +/* ACPI code for EC functions */ +#include "../../../../ec/compal/ene932/acpi/ec.asl" diff --git a/src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl new file mode 100644 index 0000000..dd32379 --- /dev/null +++ b/src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 20 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} + diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl new file mode 100644 index 0000000..7b9aef0 --- /dev/null +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_GPE) { + Method(_L1F, 0x0, NotSerialized) + { + Notify(\_SB.LID0,0x80) + } +} + +Scope (\_SB) { + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (GP15, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } + + Device (TPAD) + { + Name (_ADR, 0x0) + Name (_UID, 1) + + // Report as a Sleep Button device so Linux will + // automatically enable it as a wake source + Name(_HID, EisaId("PNP0C0E")) + + // Trackpad Wake is GPIO12, wake from S3 + Name(_PRW, Package(){0x1c, 0x03}) + + Name(_CRS, ResourceTemplate() + { + + // PIRQA -> GSI16 + Interrupt (ResourceConsumer, Level, ActiveLow) {16} + + // PIRQE -> GSI20 + Interrupt (ResourceConsumer, Edge, ActiveLow) {20} + + // SMBUS Address 0x67 + VendorShort (ADDR) {0x67} + }) + } + +} diff --git a/src/mainboard/google/parrot/acpi/platform.asl b/src/mainboard/google/parrot/acpi/platform.asl new file mode 100644 index 0000000..2d59ebe --- /dev/null +++ b/src/mainboard/google/parrot/acpi/platform.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Update in case state changed while asleep */ + /* Update AC status */ + Store (\_SB.PCI0.LPCB.EC0.ADPT, Local0) + if (LNotEqual (Local0, \PWRS)) { + Store (Local0, \PWRS) + Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) + } + + /* Update LID status */ + Store (GP15, Local0) + if (LNotEqual (Local0, \LIDS)) { + Store (Local0, \LIDS) + Notify (\_SB.LID0, 0x80) + } + + Return(Package(){0,0}) +} + diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..ee4221a --- /dev/null +++ b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} + diff --git a/src/mainboard/google/parrot/acpi/superio.asl b/src/mainboard/google/parrot/acpi/superio.asl new file mode 100644 index 0000000..e4856fc --- /dev/null +++ b/src/mainboard/google/parrot/acpi/superio.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include "../ec.h" + + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include "../../../../ec/compal/ene932/acpi/superio.asl" diff --git a/src/mainboard/google/parrot/acpi/thermal.asl b/src/mainboard/google/parrot/acpi/thermal.asl new file mode 100644 index 0000000..440612c --- /dev/null +++ b/src/mainboard/google/parrot/acpi/thermal.asl @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Ignore critical temps for the first few reads + // at boot to prevent unexpected shutdown + Name (IRDC, 4) + Name (CRDC, 0) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + // Get CPU Temperature from the Embedded Controller + Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0) + + // Re-read from EC if the temperature is very high to + // avoid OS shutdown if we got a bad reading. + If (LGreaterEqual (Local0, \TCRT)) { + Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0) + If (LGreaterEqual (Local0, \TCRT)) { + // Check if this is an early read + If (LLess (CRDC, IRDC)) { + Store (0, Local0) + } + } + } + + // Keep track of first few reads by the OS + If (LLess (CRDC, IRDC)) { + Increment (CRDC) + } + + Return (CTOK (Local0)) + } + +// The EC does all fan control. The is no Active Cooling Fan control (_ACx). + + } +} + diff --git a/src/mainboard/google/parrot/acpi/video.asl b/src/mainboard/google/parrot/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/google/parrot/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c new file mode 100644 index 0000000..8308c01 --- /dev/null +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <ec/compal/ene932/ec.h> +#include "ec.h" + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + /* EC handles all active thermal and fan control on Parrot. */ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = (u32)get_cbmem_toc(); + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + +#if CONFIG_CHROMEOS + // TODO(reinauer) this could move elsewhere? + chromeos_init_vboot(&(gnvs->chromeos)); + + gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + + acpi_update_thermal_table(gnvs); + + // the lid is open by default. + gnvs->lids = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + acpi_save_gnvs(current); + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c new file mode 100644 index 0000000..d4054ef --- /dev/null +++ b/src/mainboard/google/parrot/chromeos.c @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> + +#ifdef __PRE_RAM__ +#include <arch/romcc_io.h> +#else +#include <device/device.h> +#include <device/pci.h> +#endif + +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/compal/ene932/ec.h> +#include "ec.h" + +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> + +#define GPIO_COUNT 6 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + + if (!gpio_base) + return; + + u32 gp_lvl = inl(gpio_base + GP_LVL); + u32 gp_lvl3 = inl(gpio_base + GP_LVL3); + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + /* Write Protect: GPIO70 active high */ + gpios->gpios[0].port = 70; + gpios->gpios[0].polarity = ACTIVE_LOW; + gpios->gpios[0].value = (gp_lvl3 >> (70 - 64)) & 1; + strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); + + /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ + gpios->gpios[1].port = -1; + gpios->gpios[1].polarity = ACTIVE_HIGH; + gpios->gpios[1].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + + /* Developer: Virtual GPIO in the EC ( Servo GPIO17 active low) */ + gpios->gpios[2].port = -1; + gpios->gpios[2].polarity = ACTIVE_HIGH; + gpios->gpios[2].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); + + /* Lid switch GPIO active high (open). */ + gpios->gpios[3].port = 15; + gpios->gpios[3].polarity = ACTIVE_HIGH; + gpios->gpios[3].value = ((gp_lvl >> 15) & 1);; + strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + + /* Power Button */ + gpios->gpios[4].port = 101; + gpios->gpios[4].polarity = ACTIVE_LOW; + gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1; + strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); + + /* Did we load the VGA Option ROM? */ + gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ + gpios->gpios[5].polarity = ACTIVE_HIGH; + gpios->gpios[5].value = oprom_is_loaded; + strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + +} +#endif + + +int get_developer_mode_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + + if (!gpio_base) + return(0); + +/* + * Dev mode is controled by EC and uboot stores a flag in TPM. This GPIO is only + * for the debug header. It is AND'd to the EC request. + */ + + u32 gp_lvl = inl(gpio_base + GP_LVL); + printk(BIOS_DEBUG,"DEV MODE GPIO 17: %x\n", !((gp_lvl >> 17) & 1)); + + /* GPIO17, active low -- return active high reading and let + * it be inverted by the caller if needed. */ + return !((gp_lvl >> 17) & 1); +} + +int get_recovery_mode_switch(void) +{ + u8 rec_mode; + + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + + if (!gpio_base) + return(0); + + /* GPIO68, active low. For Servo support + * Treat as active high and let the caller invert if needed. */ + u32 gp_lvl3 = inl(gpio_base + GP_LVL3); + rec_mode = !((gp_lvl3 >> (68 - 64)) & 1); + printk(BIOS_DEBUG,"REC MODE GPIO 68: %x\n", rec_mode); + + return (rec_mode); +} + +int parrot_ec_running_ro(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + + if (!gpio_base) + return(0); + + /* GPIO68 EC_RW is active low. + * Treat as active high and let the caller invert if needed. */ + u32 gp_lvl3 = inl(gpio_base + GP_LVL3); + return !((gp_lvl3 >> (68 - 64)) & 1); +} diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout new file mode 100644 index 0000000..afdd3c6 --- /dev/null +++ b/src/mainboard/google/parrot/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb new file mode 100644 index 0000000..d93c021 --- /dev/null +++ b/src/mainboard/google/parrot/devicetree.cb @@ -0,0 +1,105 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort B Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Enable Panel as eDP and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "500" # 50ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # Set backlight PWM values + register "gpu_cpu_backlight" = "0x000001d4" + register "gpu_pch_backlight" = "0x03aa0000" + + device lapic_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Coordinate with HW_ALL + register "pstate_coord_type" = "0xfe" + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + # Set Lid Switch to SMI to capture in recovery mode. It gets reset to + # SCI mode when we go to ACPI mode. + register "alt_gp_smi_en" = "0x8100" + register "gpi7_routing" = "2" + register "gpi8_routing" = "1" + register "gpi15_routing" = "1" #lid switch gpe + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + + # EC range is 0xFD60 (EC_IO) and 0x68/0x6C + register "gen1_dec" = "0x0004fd61" + register "gen2_dec" = "0x00040069" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (WLAN) + device pci 1c.2 on end # PCIe Port #3 (ETH0) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on # dummy address + end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl new file mode 100644 index 0000000..608827a --- /dev/null +++ b/src/mainboard/google/parrot/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c new file mode 100644 index 0000000..e6d2d38 --- /dev/null +++ b/src/mainboard/google/parrot/ec.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <ec/compal/ene932/ec.h> +#include "ec.h" + + +void parrot_ec_init(void) +{ + printk(BIOS_DEBUG, "Parrot EC Init\n"); + + /* Clean up the buffers. We don't know the initial condition. */ + kbc_cleanup_buffers(); + + /* Report EC info */ + /* EC version: cmd 0x51 - returns three bytes */ + ec_kbc_write_cmd(0x51); + printk(BIOS_DEBUG," EC version %x.%x.%x\n", + ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob()); + + /* EC Project name: cmd 0x52, 0xA0 - returns five bytes */ + ec_kbc_write_cmd(0x52); + ec_kbc_write_ib(0xA0); + printk(BIOS_DEBUG," EC Project: %c%c%c%c%c\n", + ec_kbc_read_ob(),ec_kbc_read_ob(),ec_kbc_read_ob(), + ec_kbc_read_ob(), ec_kbc_read_ob()); + + /* Print the hardware revision */ + printk(BIOS_DEBUG," Parrot Revision %x\n", parrot_rev()); + + /* US Keyboard */ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE5); + + /* Enable IRQ1 */ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xD1); + + /* TODO - Do device detection and device maintain state (nvs) */ + /* Enable Wireless and Bluetooth */ + ec_kbc_write_cmd(0x45); + ec_kbc_write_ib(0xAD); + + /* Set Wireless and Bluetooth Available */ + ec_kbc_write_cmd(0x45); + ec_kbc_write_ib(0xA8); + + /* Set Wireless and Bluetooth Enable */ + ec_kbc_write_cmd(0x45); + ec_kbc_write_ib(0xA2); +} + + +/* Parrot Hardware Revision */ +u8 parrot_rev(void) +{ + ec_kbc_write_cmd(0x45); + ec_kbc_write_ib(0x40); + return ec_kbc_read_ob(); +} diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h new file mode 100644 index 0000000..5245920 --- /dev/null +++ b/src/mainboard/google/parrot/ec.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef PARROT_EC_H +#define PARROT_EC_H + +#define EC_SCI_GPI 7 /* GPIO7 is EC_SCI# */ +#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ +#define EC_LID_GPI 15 /* GPIO15 is EC_LID_OUT# */ + +/* EC SMI sources TODO - make defines + * No event 80h +*/ +#define EC_NO_EVENT 0x80 +/* + * DTS temperature update A0h + * Decrease brightness event A1h + * Increase brightness event A2h + * Lid open A5h + * Lid closed A6h + */ +#define EC_LID_CLOSE 0xA6 + /* Bluetooth wake up event A9h + * Display change (LCD , CRT) ACh + * Cpu fast event ADh + * Cpu slow event ADh + * Battery life in critical low state (LLB) B2h + */ +#define EC_BATTERY_CRITICAL 0xB2 +/* + * Battery life in low power state (LB) B3h + * Battery Plug-In B5h + * Docked in request BAh + * Undock request BBh + * Power button pressed C2h + * AC power plug-in C7h + * AC power plug-out C8h + * Modem Ring In CAh + * PME signal active CEh + * Acer Hotkey Function – Make event D5h + * Acer Hotkey Function – Break event D6h + */ + +#ifndef __ACPI__ +extern void parrot_ec_init(void); +u8 parrot_rev(void); +int parrot_ec_running_ro(void); +#endif + +#endif // PARROT_EC_H diff --git a/src/mainboard/google/parrot/fadt.c b/src/mainboard/google/parrot/fadt.c new file mode 100644 index 0000000..5ce9ab1 --- /dev/null +++ b/src/mainboard/google/parrot/fadt.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0xb2 +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_DESKTOP; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h new file mode 100644 index 0000000..a9eb99b --- /dev/null +++ b/src/mainboard/google/parrot/gpio.h @@ -0,0 +1,279 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef PARROT_GPIO_H +#define PARROT_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NONE, /* NOT USED */ + .gpio1 = GPIO_MODE_NONE, /* NOT USED */ + .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */ + .gpio3 = GPIO_MODE_NONE, /* NOT USED / PIRQ#F */ + .gpio4 = GPIO_MODE_NONE, /* NOT USED / PIRQG# */ + .gpio5 = GPIO_MODE_NONE, /* NOT USED / PIRQH# */ + .gpio6 = GPIO_MODE_NONE, /* NOT USED / FAN TACH2 */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC SMI# */ + .gpio9 = GPIO_MODE_NATIVE, /* NOT USED / OC5# USB */ + .gpio10 = GPIO_MODE_NATIVE, /* NOT USED / OC6# USB */ + .gpio11 = GPIO_MODE_NONE, /* NOT USED / SMB_ALERT*/ + .gpio12 = GPIO_MODE_GPIO, /* Track Pad IRQ / LAN_PHY_PWR_CTRL / SMB_ALERT */ + .gpio13 = GPIO_MODE_NONE, /* NOT USED / HDA_DOCK_RST */ + .gpio14 = GPIO_MODE_NATIVE, /* NOT USED / OC7# USB */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT (INPUT to PantherPoint) */ + .gpio16 = GPIO_MODE_NONE, /* NOT USED / SATA4GP */ + .gpio17 = GPIO_MODE_GPIO, /* DEV MODE */ + .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */ + .gpio19 = GPIO_MODE_NONE, /* BIOS BOOT STRAP (NOT USED)/ SATA1GP */ + .gpio20 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ2# */ + .gpio21 = GPIO_MODE_NONE, /* NOT USED / SATA0GP */ + .gpio22 = GPIO_MODE_NONE, /* NOT USED */ + .gpio23 = GPIO_MODE_NONE, /* NOT USED */ + .gpio24 = GPIO_MODE_NONE, /* NOT USED / MEM_LED */ + .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */ + .gpio26 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ4# */ + .gpio27 = GPIO_MODE_NONE, /* S4,S5 WAKE? */ + .gpio28 = GPIO_MODE_NONE, /* On-Die PLL Voltage Regulator */ + .gpio29 = GPIO_MODE_NONE, /* NOT USED / SLP_LAN# */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */ + .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */ + .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */ + .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */ + .gpio67 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX3 */ + .gpio68 = GPIO_MODE_NONE, /* NOT USED / FAN TACK4 */ + .gpio69 = GPIO_MODE_GPIO, /* REC_MODE_L / FAN TACK5 */ + .gpio70 = GPIO_MODE_GPIO, /* SPI_WP1#_RPCH / FAN TACK7 */ + .gpio71 = GPIO_MODE_GPIO, /* LVDS/eDP / FAN TACK8 */ + .gpio72 = GPIO_MODE_NONE, /* NOT USED / BATLOW# */ + .gpio73 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ0#*/ + .gpio74 = GPIO_MODE_NONE, /* NOT USED / SML1ALERT# /PCHHOT# */ + .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_LOW, + .gpio75 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map parrot_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/parrot/hda_verb.h b/src/mainboard/google/parrot/hda_verb.h new file mode 100644 index 0000000..18d42c2 --- /dev/null +++ b/src/mainboard/google/parrot/hda_verb.h @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Parrot audio ports: + * ALC269: + * out: + * Internal Speaker: PORT D (0x14) + * Headphone: PORT A - (0x21) (SenseA) + * + * in: + * Mic2: PORT F (0x19) (SenseB) + * Line2 (internal Mic): PORT E (0x1B) + * PCBeep + * + * HDMI PatherPoint + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 + 0x10250742, // Subsystem ID + 0x0000000E, // Number of jacks (NID entries) + + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10250742 */ + 0x00172042, + 0x00172107, + 0x00172225, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + 0x01471c10, // group 1, front left/right + 0x01471d01, // no connector, no jack detect + 0x01471e17, // speaker out, analog + 0x01471f90, // fixed function, internal + + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, + + /* Pin Complex (NID 0x18) MIC1 PORTB */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + + /* Pin Complex (NID 0x19) MIC2 PORTF */ + 0x01971c21, // group 2, cap 1 + 0x01971d10, // black, jack detect + 0x01971ea7, // mic in, analog + 0x01971f04, // connector, right panel + + /* Pin Complex (NID 0x1A) LINE1 PORTC */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1B) LINE2 PORTE */ + 0x01b71c20, // group 2, cap 0 + 0x01b71d01, // no connector, no jack detect + 0x01b71ea7, // mic in, analog + 0x01b71f90, // fixed function, internal + + /* Pin Complex (NID 0x1d) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, internal + + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + + /* Pin Complex (NID 0x21) HPOUT PORTA? */ + 0x02171c1f, // group1, + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 1/8 stereo + 0x02171f04, // connector, right panel + + /* Undocumented speaker output volume settings from Compal and Realtek */ + /* Widget node 0x20 */ + 0x02050011, + 0x02040710, + 0x02050012, + 0x02041901, + + 0x02050002, + 0x0204AAB8, + 0x0205000D, + 0x02044440, + + 0x02050008, + 0x02040300, + 0x02050017, + 0x020400AF, + + /* --- Next Codec --- */ + + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x00172001, + 0x00172101, + 0x00172286, + 0x00172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +static const u32 mainboard_pc_beep_verbs_size = + sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c new file mode 100644 index 0000000..32a79d9 --- /dev/null +++ b/src/mainboard/google/parrot/mainboard.c @@ -0,0 +1,328 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <arch/coreboot_tables.h> +#include "hda_verb.h" +#include "onboard.h" +#include "ec.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <ec/compal/ene932/ec.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); + + /* Enable ACPI mode before OS resume */ + outb(0xe1, 0xb2); +} + +#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(struct eregs *regs) +{ + int res=-1; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, regs->eax & 0xffff); + + switch(regs->eax & 0xffff) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffffff00; + regs->ecx |= 0x00; /* Use video bios default */ + res = 0; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; /* Use video bios default */ + res = 0; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0003; /* eDP */ + res = 0; + break; + case 0x5f70: + switch ((regs->ecx >> 8) & 0xff) { + case 0: + /* Get Mux */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 1: + /* Set Mux */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 2: + /* Get SG/Non-SG mode */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + ((regs->ecx >> 8) & 0xff)); + return 0; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} +#endif + +#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) +{ + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + + switch (M.x86.R_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x00; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; /* Use video bios default */ + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 3; /* eDP */ + break; + case 0x5f70: + switch (M.x86.R_CH) { + case 0: + /* Get Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CL = 0; + break; + case 1: + /* Set Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0; + break; + case 2: + /* Get SG/Non-SG mode */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + M.x86.R_CH); + return 0; + } + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", + M.x86.R_AX); + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static void int15_install(void) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +#endif +#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} +#endif + +/* Audio Setup */ + +extern const u32 * cim_verb_data; +extern u32 cim_verb_data_size; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; + +} + +static void mainboard_init(device_t dev) +{ + /* Initialize the Embedded Controller */ + parrot_ec_init(); +} + +static int parrot_smbios_type41(int *handle, unsigned long *current, + const char *name, u8 irq, u8 addr) +{ + struct smbios_type41 *t = (struct smbios_type41 *)*current; + int len = sizeof(struct smbios_type41); + + memset(t, 0, sizeof(struct smbios_type41)); + t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION; + t->handle = *handle; + t->length = len - 2; + t->reference_designation = smbios_add_string(t->eos, name); + t->device_type = SMBIOS_DEVICE_TYPE_OTHER; + t->device_status = 1; + t->device_type_instance = irq; + t->segment_group_number = 0; + t->bus_number = addr; + t->function_number = 0; + t->device_number = 0; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} + +static int parrot_onboard_smbios_data(device_t dev, int *handle, + unsigned long *current) +{ + int len = 0; + u8 hardware_version = parrot_rev(); + if (hardware_version < 0x2) { /* DVT vs PVT */ + len += parrot_smbios_type41(handle, current, + PARROT_TRACKPAD_NAME, + PARROT_TRACKPAD_IRQ_DVT, + PARROT_TRACKPAD_I2C_ADDR); + } else { + len += parrot_smbios_type41(handle, current, + PARROT_TRACKPAD_NAME, + PARROT_TRACKPAD_IRQ_PVT, + PARROT_TRACKPAD_I2C_ADDR); + } + + + return len; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = parrot_onboard_smbios_data; +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif + verb_setup(); +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("Google Parrot ChromeBook") + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/parrot/mainboard_smi.c b/src/mainboard/google/parrot/mainboard_smi.c new file mode 100644 index 0000000..6f83fd8 --- /dev/null +++ b/src/mainboard/google/parrot/mainboard_smi.c @@ -0,0 +1,217 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> +#include <elog.h> +#include <ec/compal/ene932/ec.h> +#include "ec.h" + +/* Power Management PCI Configuration Registers + * Bus 0, Device 31, Function 0, Offset 0xB8 + * 00 = No Effect + * 01 = SMI# + * 10 = SCI + * 11 = NMI + */ +#define GPI_ROUT 0x8000F8B8 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 + +static void set_lid_gpi_mode(u32 mode) +{ + u32 reg32 = 0; + u16 reg16 = 0; + + /* read the GPI register, clear the lid GPI's mode, write the new mode + * and write out the register. + */ + outl(GPI_ROUT, 0xcf8); + reg32 = inl(0xcfc); + reg32 &= ~(0x03 << (EC_LID_GPI * 2)); + reg32 |= (mode << (EC_LID_GPI * 2)); + outl(GPI_ROUT, 0xcf8); + outl(reg32, 0xcfc); + + /* Set or Disable Lid GPE as SMI source in the ALT_GPI_SMI_EN register. */ + reg16 = inw(smm_get_pmbase() + ALT_GP_SMI_EN); + if (mode == GPI_IS_SCI) { + reg16 &= ~(1 << EC_LID_GPI); + } else { + reg16 |= (1 << EC_LID_GPI); + } + outw(reg16, smm_get_pmbase() + ALT_GP_SMI_EN); + + return; +} + +int mainboard_io_trap_handler(int smif) +{ + printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif); + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + + +static u8 mainboard_smi_ec(void) +{ + u8 src; + u32 pm1_cnt; + static int battery_critical_logged; + + ec_kbc_write_cmd(0x56); + src = ec_kbc_read_ob(); + printk(BIOS_DEBUG, "mainboard_smi_ec src: %x\n", src); + + switch (src) { + case EC_BATTERY_CRITICAL: +#if CONFIG_ELOG_GSMI + if (!battery_critical_logged) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, + EC_EVENT_BATTERY_CRITICAL); +#endif + battery_critical_logged = 1; + break; + case EC_LID_CLOSE: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + +#if CONFIG_ELOG_GSMI + elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); +#endif + /* Go to S5 */ + pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + break; + } + + return src; +} + +void mainboard_smi_gpi(u16 gpi_sts) +{ + u32 pm1_cnt; + + printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); + if (gpi_sts & (1 << EC_SMI_GPI)) { + /* Process all pending events from EC */ + while (mainboard_smi_ec() != EC_NO_EVENT); + } + else if (gpi_sts & (1 << EC_LID_GPI)) { + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + +#if CONFIG_ELOG_GSMI + elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); +#endif + /* Go to S5 */ + pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + } +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); + /* Disable SCI and SMI events */ + + + /* Clear pending events that may trigger immediate wake */ + + + /* Enable wake events */ + + + /* Tell the EC to Disable USB power */ + if (smm_get_gnvs()->s3u0 == 0 && smm_get_gnvs()->s3u1 == 0) { + ec_kbc_write_cmd(0x45); + ec_kbc_write_ib(0xF2); + } +} + +#define APMC_FINALIZE 0xcb +#define APMC_ACPI_EN 0xe1 +#define APMC_ACPI_DIS 0x1e + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); + switch (apmc) { + case APMC_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + case APMC_ACPI_EN: + printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); + /* Clear all pending events */ + /* EC cmd:59 data:E8 */ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE8); + + /* Set LID GPI to generate SCIs */ + set_lid_gpi_mode(GPI_IS_SCI); + + break; + case APMC_ACPI_DIS: + printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); + /* Clear all pending events */ + /* EC cmd:59 data:e9 */ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); + + /* Set LID GPI to generate SMIs */ + set_lid_gpi_mode(GPI_IS_SMI); + break; + } + return 0; +} diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h new file mode 100644 index 0000000..f3d200d --- /dev/null +++ b/src/mainboard/google/parrot/onboard.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef PARROT_ONBOARD_H +#define PARROT_ONBOARD_H + +#include <arch/smp/mpspec.h> + +#define PARROT_TRACKPAD_NAME "trackpad" +#define PARROT_TRACKPAD_I2C_ADDR 0x67 +#define PARROT_TRACKPAD_IRQ_DVT 16 +#define PARROT_TRACKPAD_IRQ_PVT 20 +#endif diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c new file mode 100644 index 0000000..58c3881 --- /dev/null +++ b/src/mainboard/google/parrot/romstage.c @@ -0,0 +1,307 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <cbmem.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include "gpio.h" +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif +#include <cbfs.h> +#include "ec/compal/ene932/ec.h" + +static void pch_enable_lpc(void) +{ + /* Parrot EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); + + /* Map EC_IO decode to the LPC bus */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001); + + /* Map EC registers 68/6C decode to the LPC bus */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001); +} + +static void rcba_config(void) +{ + u32 reg32; + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQB + * D28IP_P3IP ETH0 INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQE + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * + * Trackpad DVT PIRQA (16) + * Trackpad DVT PIRQE (20) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | + (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | + (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + reg32 = RCBA32(FD); + reg32 |= PCH_DISABLE_ALWAYS; + /* Disable PCI bridge so MRC does not probe this bus */ + reg32 |= PCH_DISABLE_P2P; + RCBA32(FD) = reg32; +} + +void main(unsigned long bist) +{ + int boot_mode = 0; + int cbmem_was_initted; + u32 pm1_cnt; + u16 pm1_sts; + +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + struct pei_data pei_data = { + pei_version: PEI_VERSION, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + smbusbar: SMBUS_IO_BASE, + wdbbar: 0x4000000, + wdbsize: 0x1000, + hpet_address: CONFIG_HPET_ADDRESS, + rcba: DEFAULT_RCBABASE, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, + thermalbase: 0xfed08000, + system_type: 0, // 0 Mobile, 1 Desktop/Server + tseg_size: CONFIG_SMM_TSEG_SIZE, + spd_addresses: { 0xA0, 0x00,0xA4,0x00 }, + ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, + ec_present: 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + dimm_channel0_disabled: 2, + dimm_channel1_disabled: 2, + max_ddr3_freq: 1600, + usb_port_config: { + /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ + { 0, 3, 0x0000 }, /* P0: Empty */ + { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ + { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ + { 0, 3, 0x0000 }, /* P4: Empty */ + { 0, 3, 0x0000 }, /* P5: Empty */ + { 0, 3, 0x0000 }, /* P6: Empty */ + { 0, 3, 0x0000 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ + { 0, 4, 0x0000 }, /* P9: Empty */ + { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ + }, + }; + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + + if (bist == 0) + enable_lapic(); + + pch_enable_lpc(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + setup_pch_gpios(&parrot_gpio_map); + + /* Initialize console device(s) */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected\n"); + boot_mode = 1; + + /* System is not happy after keyboard reset... */ + printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); + outb(0x6, 0xcf9); + hlt(); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + sandybridge_early_initialization(SANDYBRIDGE_MOBILE); + printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + post_code(0x38); + /* Enable SPD ROMs and DDR-III DRAM */ + enable_smbus(); + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == 2) + enable_usb_bar(); + + post_code(0x39); + + post_code(0x3a); + pei_data.boot_mode = boot_mode; +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif + sdram_initialize(&pei_data); + +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif + post_code(0x3c); + + rcba_config(); + post_code(0x3d); + + quick_ram_check(); + post_code(0x3e); + + MCHBAR16(SSKPD) = 0xCAFE; +#if CONFIG_EARLY_CBMEM_INIT + cbmem_was_initted = !cbmem_initialize(); +#else + cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() + - HIGH_MEMORY_SIZE)); +#endif + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else if (boot_mode == 2) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + hlt(); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); +#if CONFIG_CHROMEOS + init_chromeos(boot_mode); +#endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); + timestamp_add(TS_AFTER_INITRAM, after_dram_time ); + timestamp_add_now(TS_END_ROMSTAGE); +#endif +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif +} diff --git a/src/mainboard/google/parrot/thermal.h b/src/mainboard/google/parrot/thermal.h new file mode 100644 index 0000000..9154d0a --- /dev/null +++ b/src/mainboard/google/parrot/thermal.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef PARROT_THERMAL_H +#define PARROT_THERMAL_H + +/* Active Thermal and fans are controlled by the EC. */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif

1 0

New patch to review for coreboot: b08602e Update 3rdparty to it's HEAD
by Stefan Reinauer 12 Dec '12

12 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2025 -gerrit commit b08602e7b16ccafe437139a407742e589aea7f75 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 15:59:08 2012 -0800 Update 3rdparty to it's HEAD Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- 3rdparty | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index b617b81..7eb78b1 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit b617b812e3cf1d2c4e60efc90bf8b60232124192 +Subproject commit 7eb78b1109242653c60cccd741951dcb58f51cec

1 0

New patch to review for coreboot: cc1911a Add support for ENE932 EC w/ Compal firmware
by Stefan Reinauer 12 Dec '12

12 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2024 -gerrit commit cc1911ac17ed1ee684ec6559a7bf9e02502c4f9b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 15:51:47 2012 -0800 Add support for ENE932 EC w/ Compal firmware Change-Id: I19b03139e7edfee6ff3e0bcef735bb36bfadc354 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/ec/Kconfig | 1 + src/ec/Makefile.inc | 2 +- src/ec/compal/Kconfig | 1 + src/ec/compal/Makefile.inc | 1 + src/ec/compal/ene932/Kconfig | 4 + src/ec/compal/ene932/Makefile.inc | 3 + src/ec/compal/ene932/acpi/ac.asl | 39 ++++ src/ec/compal/ene932/acpi/battery.asl | 158 +++++++++++++++ src/ec/compal/ene932/acpi/ec.asl | 355 ++++++++++++++++++++++++++++++++++ src/ec/compal/ene932/acpi/superio.asl | 57 ++++++ src/ec/compal/ene932/chip.h | 35 ++++ src/ec/compal/ene932/ec.c | 180 +++++++++++++++++ src/ec/compal/ene932/ec.h | 56 ++++++ 13 files changed, 891 insertions(+), 1 deletion(-) diff --git a/src/ec/Kconfig b/src/ec/Kconfig index 935b40b..0233bd9 100644 --- a/src/ec/Kconfig +++ b/src/ec/Kconfig @@ -1,3 +1,4 @@ source src/ec/acpi/Kconfig +source src/ec/compal/Kconfig source src/ec/lenovo/Kconfig source src/ec/smsc/Kconfig diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc index b334c1f..0ddba79 100644 --- a/src/ec/Makefile.inc +++ b/src/ec/Makefile.inc @@ -1,2 +1,2 @@ subdirs-$(CONFIG_EC_ACPI) += acpi -subdirs-y += lenovo smsc +subdirs-y += compal lenovo smsc diff --git a/src/ec/compal/Kconfig b/src/ec/compal/Kconfig new file mode 100644 index 0000000..5b7899a --- /dev/null +++ b/src/ec/compal/Kconfig @@ -0,0 +1 @@ +source src/ec/compal/ene932/Kconfig diff --git a/src/ec/compal/Makefile.inc b/src/ec/compal/Makefile.inc new file mode 100644 index 0000000..ce75ca6 --- /dev/null +++ b/src/ec/compal/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_EC_COMPAL_ENE932) += ene932 diff --git a/src/ec/compal/ene932/Kconfig b/src/ec/compal/ene932/Kconfig new file mode 100644 index 0000000..47e4b7b --- /dev/null +++ b/src/ec/compal/ene932/Kconfig @@ -0,0 +1,4 @@ +config EC_COMPAL_ENE932 + bool + help + Interface to COMPAL ENE932 Embedded Controller. diff --git a/src/ec/compal/ene932/Makefile.inc b/src/ec/compal/ene932/Makefile.inc new file mode 100644 index 0000000..fb898be --- /dev/null +++ b/src/ec/compal/ene932/Makefile.inc @@ -0,0 +1,3 @@ +ramstage-y += ec.c +smm-y += ec.c +smm-y += ../../../lib/delay.c diff --git a/src/ec/compal/ene932/acpi/ac.asl b/src/ec/compal/ene932/acpi/ac.asl new file mode 100644 index 0000000..8c85fc3 --- /dev/null +++ b/src/ec/compal/ene932/acpi/ac.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_PSR) + { + Store(ADPT, Local0) + Return(Local0) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl new file mode 100644 index 0000000..90d8adb --- /dev/null +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Scope (EC0) + +Device (BATX) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Name (PBIF, Package () { + 0x00000001, // Power Unit: mAh + 0xFFFFFFFF, // Design Capacity + 0xFFFFFFFF, // Last Full Charge Capacity + 0x00000001, // Battery Technology: Rechargeable + 0xFFFFFFFF, // Design Voltage + 0x00000003, // Design Capacity of Warning + 0xFFFFFFFF, // Design Capacity of Low + 0x00000001, // Capacity Granularity 1 + 0x00000001, // Capacity Granularity 2 + "", // Model Number + "", // Serial Number + "LION", // Battery Type + "" // OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // Battery State + 0xFFFFFFFF, // Battery Present Rate + 0xFFFFFFFF, // Battery Remaining Capacity + 0xFFFFFFFF, // Battery Present Voltage + }) + Name (BTNM, Zero) // Battery number + + // Workaround for full battery status, enabled by default + Name (BFWK, One) + + // Method to enable full battery workaround + Method (BFWE) + { + Store (One, BFWK) + } + + // Method to disable full battery workaround + Method (BFWD) + { + Store (Zero, BFWK) + } + + Method (_STA, 0, Serialized) + { + If (BOL0) { + Return (0x1F) + } Else { + Return (0x0F) + } + } + + Method (_BIF, 0, Serialized) + { + // Update fields from EC + Store (BAM0, Index (PBIF, 0)) + Store (BDC0, Index (PBIF, 1)) + Store (BFC0, Index (PBIF, 2)) + Store (BDV0, Index (PBIF, 4)) + Divide(BFC0, 0x64, Local0, Local1) + Multiply(Local1, 0x0A, Local1) + Store(Local1, Index(PBIF, 5)) + Divide(BFC0, 0x64, Local0, Local1) + Multiply(Local1, 0x03, Local1) + Store (Local1, Index (PBIF, 6)) + + Store (ToString(BATD), Index (PBIF, 9)) // model + Store (ToHexString(BSN0), Index (PBIF, 10)) // serial + Store (ToString(BMFN), Index (PBIF, 12)) // venor + + Store(BDN0, BTNM) // Save the battery number + + Return (PBIF) + } + + Method (_BST, 0, Serialized) + { + // + // 0: BATTERY STATE + // + // bit 0 = discharging + // bit 1 = charging + // bit 2 = critical level + // + + // Get battery state from EC and save it for the charging workaround + Store (BST0, Local0) + Store (Local0, Index (PBST, 0)) + + // + // 1: BATTERY PRESENT RATE/CURRENT + // + + Store (BAC0, Local1) + Subtract(0xFFFF, Local1, Local1) + Store (Local1, Index (PBST, 1)) + + // + // 2: BATTERY REMAINING CAPACITY + // + Multiply(BFC0, GAU0, Local1) + Divide(Local1, 0x64, Local2, Local1) + + If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) { + // On AC power and battery is neither charging + // nor discharging. Linux expects a full battery + // to report same capacity as last full charge. + // https://bugzilla.kernel.org/show_bug.cgi?id=12632 + Store (GAU0, Local2) + + // See if within ~3% of full + ShiftRight (Local2, 5, Local3) + If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), + LLess (Local1, Add (Local2, Local3)))) + { + Store (Local2, Local1) + } + } + Store (Local1, Index (PBST, 2)) + + // + // 3: BATTERY PRESENT VOLTAGE + // + Store (BPV0, Index (PBST, 3)) + + // Check the Battery Number + If(LNotEqual(BDN0, BTNM)) { + Notify(BATX, 0x81) + } + + Return (PBST) + } +} diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl new file mode 100644 index 0000000..cb50a21 --- /dev/null +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -0,0 +1,355 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, EC_SCI) // GPE for Runtime SCI + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + // EC Name Space Configuration + Offset(0x00), + , 1, // Reserved ; 00h.0 + LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 + , 6, // Reserved ; 00h.2 ~ 00h.6 + HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function + HTBT, 8, // HOTKEY_BUTTON_TYPE ; 02h For ABO Hot Key Function + LMEN, 1, // Launch Manager enable .(1=Enable ) ; 03h.0, Lauanch manage + , 7, // Reserved ; 03h.1 ~ 03h.7 + ADAP, 2, // Adaptor Type ; 04h.0 ~ 1 + // 0x00 = default(65w) + // 0x01 = 65w + // 0x02 = 90w + // 0x03 = 120w + , 6, // Reserved ; 04h.2 ~ 04h.7 + Offset(0x08), // Project Common Name space definition ; 08h - 2Ch + Offset(0x2D), + DSPM, 1, // Display Mode.(0=dGPU, 1=iGPU ) ; 2Dh.0 + Offset(0x2E), + EFP1, 4, // Turbo Off P-State ; 2Eh.3-0 + Offset(0x40), // ABO Common Name space definition ; 2F - 5Ch + Offset(0x5D), + ENIB, 16, // Ext_NameSpace_Index ; 5Dh + // Ext_NameSpace_Bank ; 5Eh + ENDD, 8, // Ext_NameSpace_Data ; 5Fh + Offset(0x60), + SMPR, 8, // SMBus protocol register ; 60h + SMST, 8, // SMBus status register ; 61h + SMAD, 8, // SMBus address register ; 62h + SMCM, 8, // SMBus command register ; 63h + SMD0, 0x100, // SMBus data regs (32) ; 64h - 83h + BCNT, 8, // SMBus Block Count ; 84h + SMAA, 24, // SMBus Alarm Address ; 85h - 87h + Offset(0x90), + BMFN, 72, // Battery Manufacture name ; 90h - 98h + BATD, 56, // Battery Device name ; 99h - 9fh + Offset(0xA1), + , 1, // Reserve ; A1h.0 + VIDO, 1, // Video Out Button (1=Pressed) ; A1h.1 + TOUP, 1, // Touch Pad Button (0=On, 1=Off) ; A1h.2 + Offset(0xA2), + ODTS, 8, // OS Shutdown Temp2 (DTS) ; A2h + Offset(0xA3), + OSTY, 3, // OSTYPE : 000- XP ; A3h.0-2 + // 001- Vista + // 010- Linux + // 011- Win7 + , 4, // Reserve ; A3h.3-6 + ADPT, 1, // AC Adapter (0=OffLine, 1=OnLine) ; A3h.7 + Offset(0xA4), + PWAK, 1, // PME Wake Enable(0=Disable, 1=Enable) ; A4h.0 + MWAK, 1, // Modem Wake Enable(0/1=Disable/Enable); A4h.1 + LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); A4h.2 + RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; A4h.3 + WWAK, 1, // WLAN wake Enable (0=Disable,1=Enable); A4h.4 + UWAK, 1, // USB WAKE(0=Disable, 1=Enable) ; A4h.5 + KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; A4h.6 + TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; A4h.7 + Offset(0xA5), + CCAC, 1, // Charge Current (1=AC OFF) ; A5h.0 + AOAC, 1, // Adapter OVP (1=AC OFF) ; A5h.1 + BLAC, 1, // Batt learning (1=AC OFF) ; A5h.2 + PSRC, 1, // Command (1=AC OFF) ; A5h.3 + BOAC, 1, // Batt OVP (1=AC OFF) ; A5h.4 + LCAC, 1, // Leak Current (1=AC OFF) ; A5h.5 + AAAC, 1, // Air Adapter (1=AC OFF) ; A5h.6 + ACAC, 1, // AC Off (1=AC OFF) ; A5h.7 + Offset(0xA6), + S3ST, 1, // System entry S3 State : A6.0 + S3RM, 1, // System resume from S3 State : A6.1 + S4ST, 1, // System entry S4 State : A6.2 + S4RM, 1, // System resume from S4 State : A6.3 + S5ST, 1, // System entry S4 State : A6.4 + S5RM, 1, // System resume from S4 State : A6.5 + , 2, // Reserve ; A6h.6-7 + Offset(0xA7), + OSTT, 8, // OS Throttling Temp ; A7h + OSST, 8, // OS Shutdown Temp ; A8h + THLT, 8, // Throttling Temp ; A9h + TCNL, 8, // Tcontrol Temp ; AAh + MODE, 1, // Mode(0=Local, 1=Remote) ; ABh.0 + , 2, // Reserve ; ABh.1-2 + INIT, 1, // INITOK(0/1=Controlled by OS/EC) ; ABh.3 + FAN1, 1, // FAN1 Active ; ABh.4 + FAN2, 1, // FAN2 Active ; ABh.5 + FANT, 1, // FAN Speed Time OK ; ABh.6 + SKNM, 1, // Skin Mode (0/1=Skin Address 90/92) ; ABh.7 + SDTM, 8, // Shutdown Thermal Temperature ; ACh + FSSN, 4, // Fan Speed Step Number ; ADh.0-3 + // 00 : Fan Off + // 01 : Fan On Speed 1 + // 10 : Fan On Speed 2 + // 11 : Fan On Speed 3 + FANU, 4, // Machine Fan's number ; ADh.4-7 + PCVL, 4, // Throttling Level ; AEh.0-3 + // 0000 : Nothing + // 0001 : Clock throttling 12.5% + // 0010 : Clock throttling 25% + // 0011 : Clock throttling 37.5% + // 0100 : Clock throttling 50% + , 2, // Reserved ; AEh.4-5 + SWTO, 1, // SW Throttling (1=Active) ; AEh.6 + TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7 + TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0 + THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1 + , 2, // Reserved ; AFh.2-3 + NPST, 4, // Number of P-State level ; AFh.4-7 + CTMP, 8, // Current CPU Temperature ; B0h + CTML, 8, // CPU local temperature ; B1h + SKTA, 8, // Skin Temperature A ; B2h + SKTB, 8, // GPU Temperature ; B3h + SKTC, 8, // Skin Temperature C ; B4h + , 8, // Reserved ; B5h + NTMP, 8, // North Bridge Diode Temp ; B6h + Offset(0xB7), + , 1, // Reserved ; B7h.0 + SKEY, 1, // Security key event ; B7h.1 + DIGM, 1, // Digital Mode (1=Selected) ; B7h.2 + CDLE, 1, // CD lock mode enable ; B7h.3 + , 4, // Reserved ; B7h.4-7 + , 1, // Reserved ; B8h.0 + LIDF, 1, // LID flag (1=Closed, 0=Opened) ; B8h.1 + PMEE, 1, // PME event (0=off, 1=On) ; B8h.2 + PWBE, 1, // Power button event (0=off, 1=On) ; B8h.3 + RNGE, 1, // Ring in event (0=off, 1=On) ; B8h.4 + BTWE, 1, // Bluetooth wake event (0=off, 1=On) ; B8h.5 + , 2, // Reserved ; B8h.6-7 + Offset(0xB9), + BRTS, 8, // Brightness Value ; B9h + S35M, 1, // S3.5 HotKey test mode ; BAh.0 + S35S, 1, // S3.5 function status ; BAh.1 + , 2, // Reserved ; BAh.2-3 + FFEN, 1, // IRST support bit (1= Support) ; BAh.4 + FFST, 1, // IRST status flag ; BAh.5 + , 2, // Reserved ; BAh.6-7 + WLAT, 1, // Wireless LAN (0=Inactive, 1=Active) ; BBh.0 + BTAT, 1, // BlueTooth (0=Inactive, 1=Active) ; BBh.1 + WLEX, 1, // Wireless LAN (0=Not Exist, 1=Exist) ; BBh.2 + BTEX, 1, // BlueTooth (0=Not Exist, 1=Exist) ; BBh.3 + KLSW, 1, // Kill Switch (0=Off, 1=On) ; BBh.4 + WLOK, 1, // Wireless LAN Initialize OK ; BBh.5 + AT3G, 1, // 3G (0=non-active, 1=active) ; BBh.6 + EX3G, 1, // 3G (0=Not Exist, 1=Exist) ; BBh.7 + PJID, 8, // Project ID ; BCh + CPUJ, 3, // CPU Type ; BDh.0-2 + // 00, Tj85, + // 01, Tj90, + // 02, Tj100, + // 03, Tj105, + // 04 - 07, Reserved + CPNM, 3, // CPU Core number ; BDh.3-5 + // 00, Single Core + // 01, Dual Core + // 02, Quad Core + // 03 - 07, Reserved + GATY, 2, // VGA Type ; BDh.6-7 + // 00, UMA + // 01. Discrete + // 02 - 03, Reserved + Offset(0xBE), + BOL0, 1, // Batt0 (0=OffLine, 1=OnLine) ; BEh.0 + BOL1, 1, // Batt1 (0=OffLine, 1=OnLine) ; BEh.1 + , 2, // Reserved ; BEh.2-3 + BCC0, 1, // Batt0 be charging (1=Charging) ; BEh.4 + BCC1, 1, // Batt1 be charging (1=Charging) ; BEh.5 + , 2, // Reserved ; BEh.6-7 + BPU0, 1, // Batt0 (1=PowerUp) ; BFh.0 + BPU1, 1, // Batt1 (1=PowerUp) ; BFh.1 + , 2, // Reserved ; BFh.2-3 + BOS0, 1, // Batt0 (1=OnSMBUS) ; BFh.4 + BOS1, 1, // Batt1 (1=OnSMBUS) ; BFh.5 + , 2, // Reserved ; BFh.6-7 + Offset(0xC0), + BTY0, 1, // Batt Type (0=NiMh, 1=LiIon) ; C0h.0 + BAM0, 1, // Battery mode (0=mA, 1=mW) ; C0h.1 + BAL0, 1, // Low Battery ; C0h.2 + , 1, // Reserved ; C0h.3 + BMF0, 3, // Battery Manufacturer ; C0h.4-6 + // 001 : Sanyo + // 010 : Sony + // 100 : Pansonic + // 101 : CPT + , 1, // Reserved ; C0h.7 + BST0, 8, // Battery Status ; C1h + // Bit0 : Discharging + // Bit1 : Charging + // Bit2 : Discharg and Critical Low + // Bit3-7 : Reserved + BRC0, 16, // Batt Remaining Capacity ; C2h, C3h + BSN0, 16, // Batt Serial Number ; C4h, C5h + BPV0, 16, // Batt Present Voltage ; C6h, C7h + BDV0, 16, // Batt Design Voltage ; C8h, C9h + BDC0, 16, // Batt Design Capacity ; CAh, CBh + BFC0, 16, // Batt Last Full Charge Capacity ; CCh, CDh + GAU0, 8, // Batt Gasgauge ; CEh + CYC0, 8, // Batt Cycle Counter ; CFh + BPC0, 16, // Batt Current ; D0h, D1h + BAC0, 16, // Batt Average Current ; D2h, D3h + BTW0, 8, // Batt Comsuption ; D4h + BVL0, 8, // Batt Battery Volt ; D5h + BTM0, 8, // Batt Battery Temp ; D6h + BAT0, 8, // Batt Average Temp (Degree C) ; D7h + BCG0, 16, // Batt charge current ; D8h, D9h + BCT0, 8, // Batt Current Temp Semple counter ; DAh + BCI0, 8, // BATT CMD Index for read BATT(SMB) ; DBh + BCM0, 8, // Count up to Communicate BATT ; DCh + BOT0, 8, // Count up if BATT over Temp ; DDh + BSSB, 16, // BATT Battery Status SMB ; DEh, DFh + BOV0, 8, // BATT Over Voltage Count ; E0h + BCF0, 8, // BATT Communication Fail Counter ; E1h + BAD0, 8, // Battery Voltage of ADC ; E2h + BCV1, 16, // Cell Voltage 1 (mV) ; E3h, E4h + BCV2, 16, // Cell Voltage 2 (mV) ; E5h, E6h + BCV3, 16, // Cell Voltage 3 (mV) ; E7h, E8h + BCV4, 16, // Cell Voltage 4 (mV) ; E9h, EAh + Offset(0xF4), + BMD0, 16, // Manufacture Date ; F4h, F5h + // Batt Day ; BIT[4:0] (Day) + // Batt Month ; BIT[9:5] (Month) + // Batt Year ; BIT[15:10] (Year) + BACV, 16, // Charging Voltage ; F6h, F7h + BDN0, 8, // Battery Cell Number ; F8h + , 8 // Last byte for Reserved. + } + + Method (_CRS, 0, NotSerialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + Return (ECMD) + } + + Method (_REG, 2, NotSerialized) + { + // Initialize AC power state + Store (ADPT, \PWRS) + + // Initialize LID switch state + Store (GP15, \LIDS) + + // Force a read of CPU temperature + Store (CTML, Local0) + } + + +/* + * EC Query Responses + * + * DTS temperature update 10h + * Decrease brightness event 11h + * Increase brightness event 12h + * Cover lid open 15h + * Cover lid close 16h + * External device plugged 17h + * External device removed 18h + * Bluetooth wake up event 19h + * Scr expand event 1Bh + * Display toggle 1Ch + * CPU fast/slow event 1Dh + * Battery in critical low 22h + * Battery in low state 23h + * Battery pack plug in 25h + * Docking in 2Ah + * Undock 2Bh + * Power button pressed 32h + * AC plug in 37h + * AC removed 38h + * Modem ring in 3Ah + * PME signal active 3Eh + * Hotkey make Function 45h + * Hotkey break Function 46h + */ + + // AC Power Connected + Method (_Q37, 0, NotSerialized) + { + Store (One, \PWRS) + Notify (AC, 0x80) + Notify (BATX, 0x80) + // TODO ADD CPU power profile + \PNOT () + } + + // AC Power Removed + Method (_Q38, 0, NotSerialized) + { + Store (Zero, \PWRS) + Notify (AC, 0x80) + Notify (BATX, 0x80) + // TODO ADD CPU power profile + \PNOT () + } + + // Battery at critical low state + Method (_Q22, 0, NotSerialized) + { + Notify (BATX, 0x80) + } + + // Battery insert + Method(_Q25, 0, NotSerialized) + { + Notify(BATX, 0x81) + Notify(BATX, 0x80) + } + + // Commuation Device Disable/Enable Event + Method(_Q60, 0, NotSerialized) + { + IF(WLEX) //if Wlan exist + { + //TODO Store(WLAT, LANE) + } + } + + #include "ac.asl" + #include "battery.asl" +} diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl new file mode 100644 index 0000000..db4b412 --- /dev/null +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_UID, 0) + Name (_ADR, 0) + + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif +} diff --git a/src/ec/compal/ene932/chip.h b/src/ec/compal/ene932/chip.h new file mode 100644 index 0000000..5d209ff --- /dev/null +++ b/src/ec/compal/ene932/chip.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _EC_COMPAL_ENE932_CHIP_H +#define _EC_COMPAL_ENE932_CHIP_H + +#include <device/device.h> +#include <pc80/keyboard.h> + +struct chip_operations; +extern struct chip_operations ec_compal_ene932_ops; + +struct ec_compal_ene932_config { + struct pc_keyboard keyboard; +}; + +#endif /* _EC_COMPAL_ENE932_CHIP_H */ diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c new file mode 100644 index 0000000..c3087e9 --- /dev/null +++ b/src/ec/compal/ene932/ec.c @@ -0,0 +1,180 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> +#include <arch/io.h> +#include <delay.h> +#include "ec.h" +#include "chip.h" + +/* kbc helper functions from drivers/pc80/keyboard.c. TODO: share functions. */ +static int kbc_input_buffer_empty(void) +{ + u32 timeout; + for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & KBD_IBF); + timeout--) { + mdelay(1); + } + + if (!timeout) { + printk(BIOS_WARNING, + "Unexpected Keyboard controller input buffer full\n"); + } + return !!timeout; +} + + +static int kbc_output_buffer_full(void) +{ + u32 timeout; + for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(KBD_STATUS) + & KBD_OBF) == 0); timeout--) { + mdelay(1); + } + + if (!timeout) { + printk(BIOS_INFO, "Keyboard controller output buffer result timeout\n"); + } + return !!timeout; +} + +int kbc_cleanup_buffers(void) +{ + u32 timeout; + for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) + & (KBD_OBF | KBD_IBF)); timeout--) { + mdelay(1); + inb(KBD_DATA); + } + + if (!timeout) { + printk(BIOS_ERR, "Couldn't cleanup the keyboard controller buffers\n"); + printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n", + KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); + } + + return !!timeout; +} + + +/* The ENE 60/64 EC registers are the same comand/status IB/OB KBC pair. + * Check status from 64 port before each command. + * + * Ex. Get panel ID command C43/D77 + * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port + * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port + * Check OBF set. Then Get Data(0x03:panel ID) from 0x60 + * Different commands return may or maynot respond and may have multiple + * bytes. Keep it simple for nor + */ + +u8 ec_kbc_read_ob(void) +{ + if (!kbc_output_buffer_full()) return 0; + return inb(KBD_DATA); +} + +void ec_kbc_write_cmd(u8 cmd) +{ + if (!kbc_input_buffer_empty()) return; + outb(cmd, KBD_COMMAND); +} + +void ec_kbc_write_ib(u8 data) +{ + if (!kbc_input_buffer_empty()) return; + outb(data, KBD_DATA); +} + + +/* + * These functions are for accessing the ENE932 device space, but are not + * currently used. + */ +/* +static u8 ec_io_read(u16 addr) +{ + outb(addr >> 8, EC_IO_HIGH); + outb(addr & 0xff, EC_IO_LOW); + return inb(EC_IO_DATA); +} +*/ +/*static void ec_write(u16 addr, u8 data) +{ + outb(addr >> 8, EC_IO_HIGH); + outb(addr & 0xff, EC_IO_LOW; + outb(data, EC_IO_DATA); +} +*/ + +#ifndef __SMM__ +static void ene932_init(device_t dev) +{ + struct ec_compal_ene932_config *conf = dev->chip_info; + + + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); + pc_keyboard_init(&conf->keyboard); + +} + + +static void ene932_read_resources(device_t dev) +{ + /* This function avoids an error on serial console. */ +} + + +static void ene932_enable_resources(device_t dev) +{ + /* This function avoids an error on serial console. */ +} + +static struct device_operations ops = { + .init = ene932_init, + .read_resources = ene932_read_resources, + .enable_resources = ene932_enable_resources +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, 0, 0, { 0, 0 }, } +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); +} + +struct chip_operations ec_compal_ene932_ops = { + CHIP_NAME("COMPAL ENE932 EC") + .enable_dev = enable_dev +}; +#endif /* ! __SMM__ */ +#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h new file mode 100644 index 0000000..879925f --- /dev/null +++ b/src/ec/compal/ene932/ec.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * EC communication interface for COMPAL ENE932 Embedded Controller. + */ + +#ifndef _EC_COMPAL_ENE932_EC_H +#define _EC_COMPAL_ENE932_EC_H + +#define EC_IO 0xfd60 /* Mainboard specific. Could be Kconfig option */ +#define EC_IO_HIGH EC_IO + 1 +#define EC_IO_LOW EC_IO + 2 +#define EC_IO_DATA EC_IO + 3 + +/* ENE EC internal address space */ +#define REG_SPI_DATA 0xfeab +#define REG_SPI_COMMAND 0xfeac +#define REG_SPI_CONFIG 0xfead +#define CFG_CSn_FORCE_LOW (1 << 4) +#define CFG_COMMAND_WRITE_ENABLE (1 << 3) +#define CFG_STATUS (1 << 1) + + +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) + + +/* Wait 400ms for keyboard controller answers */ +#define KBC_TIMEOUT_IN_MS 400 + +u8 ec_kbc_read_ob(void); +void ec_kbc_write_cmd(u8 cmd); +void ec_kbc_write_ib(u8 data); +int kbc_cleanup_buffers(void); + +#endif /* _EC_COMPAL_ENE932_EC_H */

1 0

Patch merged into coreboot/master: 3600e96 Fix UART8250 console prototypes
by gerrit＠coreboot.org 12 Dec '12

12 Dec '12

the following patch was just integrated into master: commit 3600e960b603a610064c6024c275e149944df1ca Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 12:49:32 2012 -0800 Fix UART8250 console prototypes and disable IO mapped UARTs on ARMV7 per default Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2021 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Dec 11 22:33:44 2012, giving +1 See http://review.coreboot.org/2021 for details. -gerrit

1 0

Patch merged into coreboot/master: de48f0f Fix up Maxim MAX77686 driver
by gerrit＠coreboot.org 12 Dec '12

12 Dec '12

the following patch was just integrated into master: commit de48f0fd4213f8d0e2c71cbd3929e629fd76eb96 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 11:20:35 2012 -0800 Fix up Maxim MAX77686 driver ... to fit into the naming convention Change-Id: I4a7d81c4d6674d001fc831df863bd2343f6c636f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2020 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Dec 11 22:19:38 2012, giving +1 See http://review.coreboot.org/2020 for details. -gerrit

1 0

New patch to review for coreboot: 111a621 Fix ARMv7 payload handling
by Stefan Reinauer 12 Dec '12

12 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2022 -gerrit commit 111a621f6876780707c1b82b4550a755195e0ed8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 15:23:45 2012 -0800 Fix ARMv7 payload handling cbfstool was called with the wrong parameters Change-Id: I405d0fd7c84b46da3c98a36fd19ef0034dc175cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/armv7/Makefile.inc | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 076a93f..11b99a0 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -33,9 +33,6 @@ COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) endif -#ifeq ($(CONFIG_AP_CODE_IN_CAR),y) -#COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf -#endif extract_nth=$(word $(1), $(subst |, ,$(2))) @@ -44,9 +41,9 @@ prebuild-files = \ $(foreach file,$(cbfs-files), \ $(CBFSTOOL) $@.tmp \ add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload) \ - $(call extract_nth,1,$(file)) \ - $(call extract_nth,2,$(file)) $(if $(filter-out stage payload,$(call extract_nth,3,$(file))),$(call extract_nth,3,$(file))) \ - $(call extract_nth,4,$(file)) &&) + -f $(call extract_nth,1,$(file)) \ + -n $(call extract_nth,2,$(file)) $(if $(filter-out stage,$(call extract_nth,3,$(file))),-t $(call extract_nth,3,$(file))) \ + $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) @@ -74,7 +71,7 @@ ifeq ($(CONFIG_PAYLOAD_NONE),y) endif ifeq ($(CONFIG_PAYLOAD_ELF),y) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" - $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n"

1 0

Patch set updated for coreboot: 34c5a26 Add minimal mainboard support for snow
by Stefan Reinauer 12 Dec '12

12 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2018 -gerrit commit 34c5a26c769dfecb761fcc21ac31e0de08cca74a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 16:13:43 2012 -0800 Add minimal mainboard support for snow This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/google/Kconfig | 35 ++++++ src/mainboard/google/snow/Kconfig | 180 +++++++++++++++++++++++++++++++ src/mainboard/google/snow/Makefile.inc | 36 +++++++ src/mainboard/google/snow/devicetree.cb | 26 +++++ src/mainboard/google/snow/mainboard.c | 34 ++++++ src/mainboard/google/snow/romstage.c | 32 ++++++ src/mainboard/google/snow/smdk5250_spl.c | 78 ++++++++++++++ 8 files changed, 424 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index da76327..66168ea 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -58,6 +58,8 @@ config VENDOR_GETAC bool "Getac" config VENDOR_GIGABYTE bool "GIGABYTE" +config VENDOR_GOOGLE + bool "Google" config VENDOR_HP bool "HP" config VENDOR_IBASE @@ -158,6 +160,7 @@ source "src/mainboard/ecs/Kconfig" source "src/mainboard/emulation/Kconfig" source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" +source "src/mainboard/google/Kconfig" source "src/mainboard/hp/Kconfig" source "src/mainboard/ibase/Kconfig" source "src/mainboard/ibm/Kconfig" diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig new file mode 100644 index 0000000..cf2fad3 --- /dev/null +++ b/src/mainboard/google/Kconfig @@ -0,0 +1,35 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +if VENDOR_GOOGLE + +choice + prompt "Mainboard model" + +config BOARD_GOOGLE_SNOW + bool "Snow" + +endchoice + +source "src/mainboard/google/snow/Kconfig" + +config MAINBOARD_VENDOR + string + default "Google" + +endif # VENDOR_GOOGLE diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig new file mode 100644 index 0000000..8c465b2 --- /dev/null +++ b/src/mainboard/google/snow/Kconfig @@ -0,0 +1,180 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_SNOW + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_SAMSUNG_EXYNOS5 + select HAVE_UART_MEMORY_MAPPED + select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging +# select EC_GOOGLE_CHROMEEC + select BOARD_ROMSIZE_KB_4096 + select DRIVER_MAXIM_77686 +# select HAVE_ACPI_TABLES +# select MMCONF_SUPPORT +# select CHROMEOS + +config MAINBOARD_DIR + string + default google/snow + +config MAINBOARD_PART_NUMBER + string + default "SNOW" + +#config MMCONF_BASE_ADDRESS +# hex +# default 0xf0000000 + +#config IRQ_SLOT_COUNT +# int +# default 18 + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "Samsung" + +# SPL (second-phase loader) stuff +config SPL_TEXT_BASE + hex + default 0x02023400 + help + Location of SPL. Default location is within iRAM region. + +# FIXME: increased "SPL" size to get around build issues +#config SPL_MAX_SIZE +# hex "SPL executable max size" +# default 0x3800 +# help +# Max size of SPL. Default is 14KB +config SPL_MAX_SIZE + hex + default 0x8000 + help + Max size of SPL. Let's say 32KB for now... + +config DRAM_SIZE_MB + int + default 2048 + +config NR_DRAM_BANKS + int + default 1 + +choice + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART3 + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + default 0x12c00000 if CONSOLE_SERIAL_UART0 + default 0x12c10000 if CONSOLE_SERIAL_UART1 + default 0x12c20000 if CONSOLE_SERIAL_UART2 + default 0x12c30000 if CONSOLE_SERIAL_UART3 + help + Map the UART names to the respective MMIO address. + +################################################################# +# stuff from smdk5250.h # +# FIXME: can we move some of these to exynos5250's Kconfig? # +################################################################# +config SYS_I2C_SPEED + int + default 100000 + +config SYS_I2C_SLAVE + hex + default 0x0 + +config I2C_MULTI_BUS + bool + default y + +#config HARD_I2C +# bool +# default y +#CMD_I2C +#I2C_EDID +#DRIVER_S3C24X0_I2C + +config VDD_ARM_MV + int + default 1300 #1.3V + +config VDD_INT_UV + int + default 1012500 # 1.0125v + +config VDD_MIF_MV + int + default 1000 # 1.0v + +config VDD_G3D_MV + int + default 1200 # 1.2v + +config VDD_LDO2_MV + int + default 1500 # 1.5v + +config VDD_LDO3_MV + int + default 1800 # 1.8v + +config VDD_LDO5_MV + int + default 1800 # 1.8v + +config VDD_LDO10_MV + int + default 1800 # 1.8v + +######### smdk5250.h ######## + +endif # BOARD_GOOGLE_SNOW diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc new file mode 100644 index 0000000..01488d0 --- /dev/null +++ b/src/mainboard/google/snow/Makefile.inc @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#romstage-y += romstage.c + +# ramstage-y += ec.c + +# FIXME: smdk5250_spl and mainboard.c are a mess. In the long +# run we'll want to replace low-level code that calls mainboard code +# with mainboard code that calls low-level code with appropriate +# parameters. Grep around for spl_get_machine_params for examples. +romstage-y += smdk5250_spl.c +ramstage-y += smdk5250_spl.c +#ramstage-y += mainboard.c + +# romstage-$(CONFIG_CHROMEOS) += chromeos.c + +# FIXME: we should do something similar to x86 platforms for Snow SPDs + +SRC_ROOT = $(src)/mainboard/google/snow diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb new file mode 100644 index 0000000..f88835e --- /dev/null +++ b/src/mainboard/google/snow/devicetree.cb @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# FIXME: this is just a stub for now +chip cpu/samsung/exynos5250 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end +end diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c new file mode 100644 index 0000000..00b3e93 --- /dev/null +++ b/src/mainboard/google/snow/mainboard.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2012 The ChromeOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <device/device.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + //dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM ChromeBook", + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c new file mode 100644 index 0000000..29e4555 --- /dev/null +++ b/src/mainboard/google/snow/romstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <system.h> +#include <cache.h> + +static void mmu_setup(void) +{ + dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); +} + +void main(unsigned long bist) +{ + mmu_setup(); +} diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c new file mode 100644 index 0000000..204e411 --- /dev/null +++ b/src/mainboard/google/snow/smdk5250_spl.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/gpio.h> +#include <cpu/samsung/exynos5-common/spl.h> +#include <cpu/samsung/exynos5250/gpio.h> + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirMw", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1700, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), + .mem_manuf = MEM_MANUF_SAMSUNG, + .bad_wake_gpio = GPIO_Y10, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* TODO: Call panic() here */ + while (1) + ; + } + + return &machine_param; +} + +int board_wakeup_permitted(void) +{ + struct spl_machine_param *param = spl_get_machine_params(); + const int gpio = param->bad_wake_gpio; + int is_bad_wake; + + /* We're a bad wakeup if the gpio was defined and was high */ + is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); + + return !is_bad_wake; +}

1 0

New patch to review for coreboot: fcbbff1 Fix UART8250 console prototypes
by Stefan Reinauer 11 Dec '12

11 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2021 -gerrit commit fcbbff1e28a4b978339bdf352e9d83364eb04f36 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 12:49:32 2012 -0800 Fix UART8250 console prototypes and disable IO mapped UARTs on ARMV7 per default Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 3 ++- src/include/uart8250.h | 7 +++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index d005d83..0a94ed8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -261,7 +261,8 @@ source src/console/Kconfig # This should default to N and be set by SuperI/O drivers that have an UART config HAVE_UART_IO_MAPPED bool - default y + default y if ARCH_X86 + default n if ARCH_ARMV7 config HAVE_UART_MEMORY_MAPPED bool diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 8457530..b00ff48 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -115,6 +115,7 @@ #define UART_LCS CONFIG_TTYS0_LCS #ifndef __ROMCC__ +#if CONFIG_CONSOLE_SERIAL8250 unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); void uart8250_tx_byte(unsigned base_port, unsigned char data); @@ -125,6 +126,8 @@ void uart8250_tx_flush(unsigned base_port); */ void uart8250_init(unsigned base_port, unsigned divisor); void uart_init(void); +#endif +#if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); /* and the same for memory mapped uarts */ @@ -136,13 +139,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); u32 uartmem_getbaseaddr(void); -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \ - CONFIG_CONSOLE_SERIAL8250MEM +#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE /* and special init for OXPCIe based cards */ extern int oxford_oxpcie_present; void oxford_init(void); #endif +#endif #endif /* __ROMCC__ */

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New patch to review for coreboot: c9386a2 Fix up Maxim MAX77686 driver
by Stefan Reinauer 11 Dec '12

11 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2020 -gerrit commit c9386a2f9d57d597d6de02061a3562684a1ec5b4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Dec 11 11:20:35 2012 -0800 Fix up Maxim MAX77686 driver ... to fit into the naming convention Change-Id: I4a7d81c4d6674d001fc831df863bd2343f6c636f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/samsung/exynos5250/power.c | 2 +- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/maxim/Kconfig | 20 +++ src/drivers/maxim/Makefile.inc | 20 +++ src/drivers/maxim/max77686/Kconfig | 24 +++ src/drivers/maxim/max77686/Makefile.inc | 20 +++ src/drivers/maxim/max77686/max77686.c | 257 ++++++++++++++++++++++++++++++++ src/drivers/maxim/max77686/max77686.h | 134 +++++++++++++++++ src/drivers/power/Kconfig | 5 - src/drivers/power/Makefile.inc | 20 --- src/drivers/power/max77686.c | 257 -------------------------------- src/drivers/power/max77686.h | 134 ----------------- 13 files changed, 478 insertions(+), 417 deletions(-) diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index f8062d1..7d294ed 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -29,7 +29,7 @@ #include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5250/sysreg.h> #include <cpu/samsung/exynos5-common/spl.h> -#include <drivers/power/max77686.h> +#include <drivers/maxim/max77686/max77686.h> static void ps_hold_setup(void) { diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index ef38f34..897b665 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -25,6 +25,7 @@ source src/drivers/generic/Kconfig source src/drivers/i2c/Kconfig source src/drivers/ics/Kconfig source src/drivers/ipmi/Kconfig +source src/drivers/maxim/Kconfig source src/drivers/oxford/Kconfig if PC80_SYSTEM source src/drivers/pc80/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index a02b705..b2aa0c8 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -22,6 +22,7 @@ subdirs-y += dec subdirs-y += emulation subdirs-y += generic subdirs-y += i2c +subdirs-y += maxim subdirs-y += oxford subdirs-y += realtek subdirs-y += sil diff --git a/src/drivers/maxim/Kconfig b/src/drivers/maxim/Kconfig new file mode 100644 index 0000000..7d0b0ed --- /dev/null +++ b/src/drivers/maxim/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The Chromium OS Authors. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +source src/drivers/maxim/max77686/Kconfig diff --git a/src/drivers/maxim/Makefile.inc b/src/drivers/maxim/Makefile.inc new file mode 100644 index 0000000..31c3d75 --- /dev/null +++ b/src/drivers/maxim/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The Chromium OS Authors. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_DRIVERS_MAXIM_MAX77676) += max77686 diff --git a/src/drivers/maxim/max77686/Kconfig b/src/drivers/maxim/max77686/Kconfig new file mode 100644 index 0000000..ada06f6 --- /dev/null +++ b/src/drivers/maxim/max77686/Kconfig @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config DRIVER_MAXIM_77686 + bool + default n + help + Maxim 77686 power regulator diff --git a/src/drivers/maxim/max77686/Makefile.inc b/src/drivers/maxim/max77686/Makefile.inc new file mode 100644 index 0000000..3fc7104 --- /dev/null +++ b/src/drivers/maxim/max77686/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_DRIVER_MAXIM_77686) += max77686.c diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c new file mode 100644 index 0000000..8fbcb8f --- /dev/null +++ b/src/drivers/maxim/max77686/max77686.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Alim Akhtar <alim.akhtar(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <smbus.h> +#include <max77686.h> + +/* Chip register numbers (not exported from this module) */ +enum { + REG_BBAT = 0x7e, + + /* Bits for BBAT */ + BBAT_BBCHOSTEN_MASK = 1 << 0, + BBAT_BBCVS_SHIFT = 3, + BBAT_BBCVS_MASK = 3 << BBAT_BBCVS_SHIFT, +}; + +/* + * Max77686 parameters values + * see max77686.h for parameters details + */ +struct max77686_para max77686_param[] = {/*{regnum, vol_addr, vol_bitpos, + vol_bitmask, reg_enaddr, reg_enbitpos, reg_enbitmask, reg_enbiton, + reg_enbitoff, vol_min, vol_div}*/ + {PMIC_BUCK1, 0x11, 0x0, 0x3F, 0x10, 0x0, 0x3, 0x3, 0x0, 750, 50000}, + {PMIC_BUCK2, 0x14, 0x0, 0xFF, 0x12, 0x4, 0x3, 0x1, 0x0, 600, 12500}, + {PMIC_BUCK3, 0x1E, 0x0, 0xFF, 0x1C, 0x4, 0x3, 0x1, 0x0, 600, 12500}, + {PMIC_BUCK4, 0x28, 0x0, 0xFF, 0x26, 0x4, 0x3, 0x1, 0x0, 600, 12500}, + {PMIC_BUCK5, 0x31, 0x0, 0x3F, 0x30, 0x0, 0x3, 0x3, 0x0, 750, 50000}, + {PMIC_BUCK6, 0x33, 0x0, 0x3F, 0x32, 0x0, 0x3, 0x3, 0x0, 750, 50000}, + {PMIC_BUCK7, 0x35, 0x0, 0x3F, 0x34, 0x0, 0x3, 0x3, 0x0, 750, 50000}, + {PMIC_BUCK8, 0x37, 0x0, 0x3F, 0x36, 0x0, 0x3, 0x3, 0x0, 750, 50000}, + {PMIC_BUCK9, 0x39, 0x0, 0x3F, 0x38, 0x0, 0x3, 0x3, 0x0, 750, 50000}, + {PMIC_LDO1, 0x40, 0x0, 0x3F, 0x40, 0x6, 0x3, 0x3, 0x0, 800, 25000}, + {PMIC_LDO2, 0x41, 0x0, 0x3F, 0x41, 0x6, 0x3, 0x1, 0x0, 800, 25000}, + {PMIC_LDO3, 0x42, 0x0, 0x3F, 0x42, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO4, 0x43, 0x0, 0x3F, 0x43, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO5, 0x44, 0x0, 0x3F, 0x44, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO6, 0x45, 0x0, 0x3F, 0x45, 0x6, 0x3, 0x1, 0x0, 800, 25000}, + {PMIC_LDO7, 0x46, 0x0, 0x3F, 0x46, 0x6, 0x3, 0x1, 0x0, 800, 25000}, + {PMIC_LDO8, 0x47, 0x0, 0x3F, 0x47, 0x6, 0x3, 0x1, 0x0, 800, 25000}, + {PMIC_LDO9, 0x48, 0x0, 0x3F, 0x48, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO10, 0x49, 0x0, 0x3F, 0x49, 0x6, 0x3, 0x1, 0x0, 800, 50000}, + {PMIC_LDO11, 0x4A, 0x0, 0x3F, 0x4A, 0x6, 0x3, 0x1, 0x0, 800, 50000}, + {PMIC_LDO12, 0x4B, 0x0, 0x3F, 0x4B, 0x6, 0x3, 0x1, 0x0, 800, 50000}, + {PMIC_LDO13, 0x4C, 0x0, 0x3F, 0x4C, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO14, 0x4D, 0x0, 0x3F, 0x4D, 0x6, 0x3, 0x1, 0x0, 800, 50000}, + {PMIC_LDO15, 0x4E, 0x0, 0x3F, 0x4E, 0x6, 0x3, 0x1, 0x0, 800, 25000}, + {PMIC_LDO16, 0x4F, 0x0, 0x3F, 0x4F, 0x6, 0x3, 0x1, 0x0, 800, 50000}, + {PMIC_LDO17, 0x50, 0x0, 0x3F, 0x50, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO18, 0x51, 0x0, 0x3F, 0x51, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO19, 0x52, 0x0, 0x3F, 0x52, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO20, 0x53, 0x0, 0x3F, 0x53, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO21, 0x54, 0x0, 0x3F, 0x54, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO22, 0x55, 0x0, 0x3F, 0x55, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO23, 0x56, 0x0, 0x3F, 0x56, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO24, 0x57, 0x0, 0x3F, 0x57, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO25, 0x58, 0x0, 0x3F, 0x58, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_LDO26, 0x59, 0x0, 0x3F, 0x59, 0x6, 0x3, 0x3, 0x0, 800, 50000}, + {PMIC_EN32KHZ_CP, 0x0, 0x0, 0x0, 0x7F, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0}, +}; + +/* + * Write a value to a register + * + * @param chip_addr i2c addr for max77686 + * @param reg reg number to write + * @param val value to be written + * + */ +static inline int max77686_i2c_write(unsigned char chip_addr, + unsigned int reg, unsigned char val) +{ + return i2c_write(chip_addr, reg, 1, &val, 1); +} + +/* + * Read a value from a register + * + * @param chip_addr i2c addr for max77686 + * @param reg reg number to write + * @param val value to be written + * + */ +static inline int max77686_i2c_read(unsigned char chip_addr, + unsigned int reg, unsigned char *val) +{ + return i2c_read(chip_addr, reg, 1, val, 1); +} + +/* + * Enable the max77686 register + * + * @param reg register number of buck/ldo to be enabled + * @param enable enable or disable bit + * + * REG_DISABLE = 0, + needed to set the buck/ldo enable bit OFF + * @return Return 0 if ok, else -1 + */ +static int max77686_enablereg(enum max77686_regnum reg, int enable) +{ + struct max77686_para *pmic; + unsigned char read_data; + int ret; + + pmic = &max77686_param[reg]; + + ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->reg_enaddr, + &read_data); + if (ret != 0) { + debug("max77686 i2c read failed.\n"); + return -1; + } + + if (enable == REG_DISABLE) { + clrbits_8(&read_data, + pmic->reg_enbitmask << pmic->reg_enbitpos); + } else { + clrsetbits_8(&read_data, + pmic->reg_enbitmask << pmic->reg_enbitpos, + pmic->reg_enbiton << pmic->reg_enbitpos); + } + + ret = max77686_i2c_write(MAX77686_I2C_ADDR, + pmic->reg_enaddr, read_data); + if (ret != 0) { + debug("max77686 i2c write failed.\n"); + return -1; + } + + return 0; +} + +static int max77686_do_volsetting(enum max77686_regnum reg, unsigned int volt, + int enable, int volt_units) +{ + struct max77686_para *pmic; + unsigned char read_data; + int vol_level = 0; + int ret; + + pmic = &max77686_param[reg]; + + if (pmic->vol_addr == 0) { + debug("not a voltage register.\n"); + return -1; + } + + ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->vol_addr, &read_data); + if (ret != 0) { + debug("max77686 i2c read failed.\n"); + return -1; + } + + if (volt_units == MAX77686_UV) + vol_level = volt - pmic->vol_min * 1000; + else + vol_level = (volt - pmic->vol_min) * 1000; + + if (vol_level < 0) { + debug("Not a valid voltage level to set\n"); + return -1; + } + vol_level /= pmic->vol_div; + + clrsetbits_8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, + vol_level << pmic->vol_bitpos); + + ret = max77686_i2c_write(MAX77686_I2C_ADDR, pmic->vol_addr, read_data); + if (ret != 0) { + debug("max77686 i2c write failed.\n"); + return -1; + } + + ret = max77686_enablereg(reg, enable); + if (ret != 0) { + debug("Failed to enable buck/ldo.\n"); + return -1; + } + + return 0; +} + +int max77686_volsetting(enum max77686_regnum reg, unsigned int volt, + int enable, int volt_units) +{ + int old_bus = i2c_get_bus_num(); + int ret; + + i2c_set_bus_num(0); + ret = max77686_do_volsetting(reg, volt, enable, volt_units); + i2c_set_bus_num(old_bus); + return ret; +} + +int max77686_enable_32khz_cp(void) +{ + i2c_set_bus_num(0); + return max77686_enablereg(PMIC_EN32KHZ_CP, REG_ENABLE); +} + +int max77686_disable_backup_batt(void) +{ + unsigned char val; + int ret; + + i2c_set_bus_num(0); + ret = max77686_i2c_read(MAX77686_I2C_ADDR, REG_BBAT, &val); + if (ret) { + debug("max77686 i2c read failed\n"); + return ret; + } + + /* If we already have the correct values, exit */ + if ((val & (BBAT_BBCVS_MASK | BBAT_BBCHOSTEN_MASK)) == + BBAT_BBCVS_MASK) + return 0; + + /* First disable charging */ + val &= ~BBAT_BBCHOSTEN_MASK; + ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); + if (ret) { + debug("max77686 i2c write failed\n"); + return -1; + } + + /* Finally select 3.5V to minimize power consumption */ + val |= BBAT_BBCVS_MASK; + ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); + if (ret) { + debug("max77686 i2c write failed\n"); + return -1; + } + + return 0; +} diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h new file mode 100644 index 0000000..345471e --- /dev/null +++ b/src/drivers/maxim/max77686/max77686.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Alim Akhtar <alim.akhtar(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MAX77686_H_ +#define __MAX77686_H_ + +enum max77686_regnum { + PMIC_BUCK1 = 0, + PMIC_BUCK2, + PMIC_BUCK3, + PMIC_BUCK4, + PMIC_BUCK5, + PMIC_BUCK6, + PMIC_BUCK7, + PMIC_BUCK8, + PMIC_BUCK9, + PMIC_LDO1, + PMIC_LDO2, + PMIC_LDO3, + PMIC_LDO4, + PMIC_LDO5, + PMIC_LDO6, + PMIC_LDO7, + PMIC_LDO8, + PMIC_LDO9, + PMIC_LDO10, + PMIC_LDO11, + PMIC_LDO12, + PMIC_LDO13, + PMIC_LDO14, + PMIC_LDO15, + PMIC_LDO16, + PMIC_LDO17, + PMIC_LDO18, + PMIC_LDO19, + PMIC_LDO20, + PMIC_LDO21, + PMIC_LDO22, + PMIC_LDO23, + PMIC_LDO24, + PMIC_LDO25, + PMIC_LDO26, + PMIC_EN32KHZ_CP, +}; + +/** + * struct max77686_para - max77686 register parameters + * @param vol_addr i2c address of the given buck/ldo register + * @param vol_bitpos bit position to be set or clear within register + * @param vol_bitmask bit mask value + * @param reg_enaddr control register address, which enable the given + * given buck/ldo. + * @param reg_enbitpos bit position to be enabled + * @param reg_enbiton value to be written to buck/ldo to make it ON + * @param reg_enbitoff value to be written to buck/ldo to make it OFF + * @param vol_min minimum voltage level supported by given buck/ldo + * @param vol_div voltage division value of given buck/ldo + */ +struct max77686_para { + enum max77686_regnum regnum; + u8 vol_addr; + u8 vol_bitpos; + u8 vol_bitmask; + u8 reg_enaddr; + u8 reg_enbitpos; + u8 reg_enbitmask; + u8 reg_enbiton; + u8 reg_enbitoff; + u32 vol_min; + u32 vol_div; +}; + +/* I2C device address for pmic max77686 */ +#define MAX77686_I2C_ADDR (0x12 >> 1) + +enum { + REG_DISABLE = 0, + REG_ENABLE +}; + +enum { + MAX77686_MV = 0, /* mili volt */ + MAX77686_UV /* micro volt */ +}; + +/** + * This function enables the 32KHz coprocessor clock. + * + * Return 0 if ok, else -1 + */ +int max77686_enable_32khz_cp(void); + +/** + * Set the required voltage level of pmic + * + * @param reg register number of buck/ldo to be set + * @param volt voltage level to be set + * @param enable enable or disable bit + * @param volt_units MAX77686_MV or MAX77686_UV, unit of the + * voltage parameters + * + * @return Return 0 if ok, else -1 + */ +int max77686_volsetting(enum max77686_regnum reg, unsigned int volt, + int enable, int volt_units); + +/** + * Disable charging of the RTC backup battery + * + * @return Return 0 if ok, else -1 + */ +int max77686_disable_backup_batt(void); + +#endif /* __MAX77686_PMIC_H_ */ diff --git a/src/drivers/power/Kconfig b/src/drivers/power/Kconfig deleted file mode 100644 index 84ace13..0000000 --- a/src/drivers/power/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config DRIVER_MAXIM_77686 - bool "Maxim 77686" - default n - help - Maxim 77686 power regulator diff --git a/src/drivers/power/Makefile.inc b/src/drivers/power/Makefile.inc deleted file mode 100644 index 3fc7104..0000000 --- a/src/drivers/power/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 The ChromiumOS Authors -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -driver-$(CONFIG_DRIVER_MAXIM_77686) += max77686.c diff --git a/src/drivers/power/max77686.c b/src/drivers/power/max77686.c deleted file mode 100644 index 8fbcb8f..0000000 --- a/src/drivers/power/max77686.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Alim Akhtar <alim.akhtar(a)samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <smbus.h> -#include <max77686.h> - -/* Chip register numbers (not exported from this module) */ -enum { - REG_BBAT = 0x7e, - - /* Bits for BBAT */ - BBAT_BBCHOSTEN_MASK = 1 << 0, - BBAT_BBCVS_SHIFT = 3, - BBAT_BBCVS_MASK = 3 << BBAT_BBCVS_SHIFT, -}; - -/* - * Max77686 parameters values - * see max77686.h for parameters details - */ -struct max77686_para max77686_param[] = {/*{regnum, vol_addr, vol_bitpos, - vol_bitmask, reg_enaddr, reg_enbitpos, reg_enbitmask, reg_enbiton, - reg_enbitoff, vol_min, vol_div}*/ - {PMIC_BUCK1, 0x11, 0x0, 0x3F, 0x10, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {PMIC_BUCK2, 0x14, 0x0, 0xFF, 0x12, 0x4, 0x3, 0x1, 0x0, 600, 12500}, - {PMIC_BUCK3, 0x1E, 0x0, 0xFF, 0x1C, 0x4, 0x3, 0x1, 0x0, 600, 12500}, - {PMIC_BUCK4, 0x28, 0x0, 0xFF, 0x26, 0x4, 0x3, 0x1, 0x0, 600, 12500}, - {PMIC_BUCK5, 0x31, 0x0, 0x3F, 0x30, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {PMIC_BUCK6, 0x33, 0x0, 0x3F, 0x32, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {PMIC_BUCK7, 0x35, 0x0, 0x3F, 0x34, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {PMIC_BUCK8, 0x37, 0x0, 0x3F, 0x36, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {PMIC_BUCK9, 0x39, 0x0, 0x3F, 0x38, 0x0, 0x3, 0x3, 0x0, 750, 50000}, - {PMIC_LDO1, 0x40, 0x0, 0x3F, 0x40, 0x6, 0x3, 0x3, 0x0, 800, 25000}, - {PMIC_LDO2, 0x41, 0x0, 0x3F, 0x41, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {PMIC_LDO3, 0x42, 0x0, 0x3F, 0x42, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO4, 0x43, 0x0, 0x3F, 0x43, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO5, 0x44, 0x0, 0x3F, 0x44, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO6, 0x45, 0x0, 0x3F, 0x45, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {PMIC_LDO7, 0x46, 0x0, 0x3F, 0x46, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {PMIC_LDO8, 0x47, 0x0, 0x3F, 0x47, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {PMIC_LDO9, 0x48, 0x0, 0x3F, 0x48, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO10, 0x49, 0x0, 0x3F, 0x49, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {PMIC_LDO11, 0x4A, 0x0, 0x3F, 0x4A, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {PMIC_LDO12, 0x4B, 0x0, 0x3F, 0x4B, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {PMIC_LDO13, 0x4C, 0x0, 0x3F, 0x4C, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO14, 0x4D, 0x0, 0x3F, 0x4D, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {PMIC_LDO15, 0x4E, 0x0, 0x3F, 0x4E, 0x6, 0x3, 0x1, 0x0, 800, 25000}, - {PMIC_LDO16, 0x4F, 0x0, 0x3F, 0x4F, 0x6, 0x3, 0x1, 0x0, 800, 50000}, - {PMIC_LDO17, 0x50, 0x0, 0x3F, 0x50, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO18, 0x51, 0x0, 0x3F, 0x51, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO19, 0x52, 0x0, 0x3F, 0x52, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO20, 0x53, 0x0, 0x3F, 0x53, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO21, 0x54, 0x0, 0x3F, 0x54, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO22, 0x55, 0x0, 0x3F, 0x55, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO23, 0x56, 0x0, 0x3F, 0x56, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO24, 0x57, 0x0, 0x3F, 0x57, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO25, 0x58, 0x0, 0x3F, 0x58, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_LDO26, 0x59, 0x0, 0x3F, 0x59, 0x6, 0x3, 0x3, 0x0, 800, 50000}, - {PMIC_EN32KHZ_CP, 0x0, 0x0, 0x0, 0x7F, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0}, -}; - -/* - * Write a value to a register - * - * @param chip_addr i2c addr for max77686 - * @param reg reg number to write - * @param val value to be written - * - */ -static inline int max77686_i2c_write(unsigned char chip_addr, - unsigned int reg, unsigned char val) -{ - return i2c_write(chip_addr, reg, 1, &val, 1); -} - -/* - * Read a value from a register - * - * @param chip_addr i2c addr for max77686 - * @param reg reg number to write - * @param val value to be written - * - */ -static inline int max77686_i2c_read(unsigned char chip_addr, - unsigned int reg, unsigned char *val) -{ - return i2c_read(chip_addr, reg, 1, val, 1); -} - -/* - * Enable the max77686 register - * - * @param reg register number of buck/ldo to be enabled - * @param enable enable or disable bit - * - * REG_DISABLE = 0, - needed to set the buck/ldo enable bit OFF - * @return Return 0 if ok, else -1 - */ -static int max77686_enablereg(enum max77686_regnum reg, int enable) -{ - struct max77686_para *pmic; - unsigned char read_data; - int ret; - - pmic = &max77686_param[reg]; - - ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->reg_enaddr, - &read_data); - if (ret != 0) { - debug("max77686 i2c read failed.\n"); - return -1; - } - - if (enable == REG_DISABLE) { - clrbits_8(&read_data, - pmic->reg_enbitmask << pmic->reg_enbitpos); - } else { - clrsetbits_8(&read_data, - pmic->reg_enbitmask << pmic->reg_enbitpos, - pmic->reg_enbiton << pmic->reg_enbitpos); - } - - ret = max77686_i2c_write(MAX77686_I2C_ADDR, - pmic->reg_enaddr, read_data); - if (ret != 0) { - debug("max77686 i2c write failed.\n"); - return -1; - } - - return 0; -} - -static int max77686_do_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units) -{ - struct max77686_para *pmic; - unsigned char read_data; - int vol_level = 0; - int ret; - - pmic = &max77686_param[reg]; - - if (pmic->vol_addr == 0) { - debug("not a voltage register.\n"); - return -1; - } - - ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->vol_addr, &read_data); - if (ret != 0) { - debug("max77686 i2c read failed.\n"); - return -1; - } - - if (volt_units == MAX77686_UV) - vol_level = volt - pmic->vol_min * 1000; - else - vol_level = (volt - pmic->vol_min) * 1000; - - if (vol_level < 0) { - debug("Not a valid voltage level to set\n"); - return -1; - } - vol_level /= pmic->vol_div; - - clrsetbits_8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, - vol_level << pmic->vol_bitpos); - - ret = max77686_i2c_write(MAX77686_I2C_ADDR, pmic->vol_addr, read_data); - if (ret != 0) { - debug("max77686 i2c write failed.\n"); - return -1; - } - - ret = max77686_enablereg(reg, enable); - if (ret != 0) { - debug("Failed to enable buck/ldo.\n"); - return -1; - } - - return 0; -} - -int max77686_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units) -{ - int old_bus = i2c_get_bus_num(); - int ret; - - i2c_set_bus_num(0); - ret = max77686_do_volsetting(reg, volt, enable, volt_units); - i2c_set_bus_num(old_bus); - return ret; -} - -int max77686_enable_32khz_cp(void) -{ - i2c_set_bus_num(0); - return max77686_enablereg(PMIC_EN32KHZ_CP, REG_ENABLE); -} - -int max77686_disable_backup_batt(void) -{ - unsigned char val; - int ret; - - i2c_set_bus_num(0); - ret = max77686_i2c_read(MAX77686_I2C_ADDR, REG_BBAT, &val); - if (ret) { - debug("max77686 i2c read failed\n"); - return ret; - } - - /* If we already have the correct values, exit */ - if ((val & (BBAT_BBCVS_MASK | BBAT_BBCHOSTEN_MASK)) == - BBAT_BBCVS_MASK) - return 0; - - /* First disable charging */ - val &= ~BBAT_BBCHOSTEN_MASK; - ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); - if (ret) { - debug("max77686 i2c write failed\n"); - return -1; - } - - /* Finally select 3.5V to minimize power consumption */ - val |= BBAT_BBCVS_MASK; - ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); - if (ret) { - debug("max77686 i2c write failed\n"); - return -1; - } - - return 0; -} diff --git a/src/drivers/power/max77686.h b/src/drivers/power/max77686.h deleted file mode 100644 index 345471e..0000000 --- a/src/drivers/power/max77686.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Alim Akhtar <alim.akhtar(a)samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MAX77686_H_ -#define __MAX77686_H_ - -enum max77686_regnum { - PMIC_BUCK1 = 0, - PMIC_BUCK2, - PMIC_BUCK3, - PMIC_BUCK4, - PMIC_BUCK5, - PMIC_BUCK6, - PMIC_BUCK7, - PMIC_BUCK8, - PMIC_BUCK9, - PMIC_LDO1, - PMIC_LDO2, - PMIC_LDO3, - PMIC_LDO4, - PMIC_LDO5, - PMIC_LDO6, - PMIC_LDO7, - PMIC_LDO8, - PMIC_LDO9, - PMIC_LDO10, - PMIC_LDO11, - PMIC_LDO12, - PMIC_LDO13, - PMIC_LDO14, - PMIC_LDO15, - PMIC_LDO16, - PMIC_LDO17, - PMIC_LDO18, - PMIC_LDO19, - PMIC_LDO20, - PMIC_LDO21, - PMIC_LDO22, - PMIC_LDO23, - PMIC_LDO24, - PMIC_LDO25, - PMIC_LDO26, - PMIC_EN32KHZ_CP, -}; - -/** - * struct max77686_para - max77686 register parameters - * @param vol_addr i2c address of the given buck/ldo register - * @param vol_bitpos bit position to be set or clear within register - * @param vol_bitmask bit mask value - * @param reg_enaddr control register address, which enable the given - * given buck/ldo. - * @param reg_enbitpos bit position to be enabled - * @param reg_enbiton value to be written to buck/ldo to make it ON - * @param reg_enbitoff value to be written to buck/ldo to make it OFF - * @param vol_min minimum voltage level supported by given buck/ldo - * @param vol_div voltage division value of given buck/ldo - */ -struct max77686_para { - enum max77686_regnum regnum; - u8 vol_addr; - u8 vol_bitpos; - u8 vol_bitmask; - u8 reg_enaddr; - u8 reg_enbitpos; - u8 reg_enbitmask; - u8 reg_enbiton; - u8 reg_enbitoff; - u32 vol_min; - u32 vol_div; -}; - -/* I2C device address for pmic max77686 */ -#define MAX77686_I2C_ADDR (0x12 >> 1) - -enum { - REG_DISABLE = 0, - REG_ENABLE -}; - -enum { - MAX77686_MV = 0, /* mili volt */ - MAX77686_UV /* micro volt */ -}; - -/** - * This function enables the 32KHz coprocessor clock. - * - * Return 0 if ok, else -1 - */ -int max77686_enable_32khz_cp(void); - -/** - * Set the required voltage level of pmic - * - * @param reg register number of buck/ldo to be set - * @param volt voltage level to be set - * @param enable enable or disable bit - * @param volt_units MAX77686_MV or MAX77686_UV, unit of the - * voltage parameters - * - * @return Return 0 if ok, else -1 - */ -int max77686_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units); - -/** - * Disable charging of the RTC backup battery - * - * @return Return 0 if ok, else -1 - */ -int max77686_disable_backup_batt(void); - -#endif /* __MAX77686_PMIC_H_ */

1 0

Patch set updated for coreboot: ac59b0e Add minimal mainboard support for snow
by Stefan Reinauer 11 Dec '12

11 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2018 -gerrit commit ac59b0e4901f3d1a0bb2a5a1b6b8141bcc03371d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 16:13:43 2012 -0800 Add minimal mainboard support for snow This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/google/Kconfig | 35 ++++++ src/mainboard/google/snow/Kconfig | 180 +++++++++++++++++++++++++++++++ src/mainboard/google/snow/Makefile.inc | 36 +++++++ src/mainboard/google/snow/devicetree.cb | 26 +++++ src/mainboard/google/snow/mainboard.c | 34 ++++++ src/mainboard/google/snow/romstage.c | 32 ++++++ src/mainboard/google/snow/smdk5250_spl.c | 78 ++++++++++++++ 8 files changed, 424 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index da76327..66168ea 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -58,6 +58,8 @@ config VENDOR_GETAC bool "Getac" config VENDOR_GIGABYTE bool "GIGABYTE" +config VENDOR_GOOGLE + bool "Google" config VENDOR_HP bool "HP" config VENDOR_IBASE @@ -158,6 +160,7 @@ source "src/mainboard/ecs/Kconfig" source "src/mainboard/emulation/Kconfig" source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" +source "src/mainboard/google/Kconfig" source "src/mainboard/hp/Kconfig" source "src/mainboard/ibase/Kconfig" source "src/mainboard/ibm/Kconfig" diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig new file mode 100644 index 0000000..cf2fad3 --- /dev/null +++ b/src/mainboard/google/Kconfig @@ -0,0 +1,35 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +if VENDOR_GOOGLE + +choice + prompt "Mainboard model" + +config BOARD_GOOGLE_SNOW + bool "Snow" + +endchoice + +source "src/mainboard/google/snow/Kconfig" + +config MAINBOARD_VENDOR + string + default "Google" + +endif # VENDOR_GOOGLE diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig new file mode 100644 index 0000000..8c465b2 --- /dev/null +++ b/src/mainboard/google/snow/Kconfig @@ -0,0 +1,180 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_SNOW + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_SAMSUNG_EXYNOS5 + select HAVE_UART_MEMORY_MAPPED + select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging +# select EC_GOOGLE_CHROMEEC + select BOARD_ROMSIZE_KB_4096 + select DRIVER_MAXIM_77686 +# select HAVE_ACPI_TABLES +# select MMCONF_SUPPORT +# select CHROMEOS + +config MAINBOARD_DIR + string + default google/snow + +config MAINBOARD_PART_NUMBER + string + default "SNOW" + +#config MMCONF_BASE_ADDRESS +# hex +# default 0xf0000000 + +#config IRQ_SLOT_COUNT +# int +# default 18 + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "Samsung" + +# SPL (second-phase loader) stuff +config SPL_TEXT_BASE + hex + default 0x02023400 + help + Location of SPL. Default location is within iRAM region. + +# FIXME: increased "SPL" size to get around build issues +#config SPL_MAX_SIZE +# hex "SPL executable max size" +# default 0x3800 +# help +# Max size of SPL. Default is 14KB +config SPL_MAX_SIZE + hex + default 0x8000 + help + Max size of SPL. Let's say 32KB for now... + +config DRAM_SIZE_MB + int + default 2048 + +config NR_DRAM_BANKS + int + default 1 + +choice + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART3 + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + default 0x12c00000 if CONSOLE_SERIAL_UART0 + default 0x12c10000 if CONSOLE_SERIAL_UART1 + default 0x12c20000 if CONSOLE_SERIAL_UART2 + default 0x12c30000 if CONSOLE_SERIAL_UART3 + help + Map the UART names to the respective MMIO address. + +################################################################# +# stuff from smdk5250.h # +# FIXME: can we move some of these to exynos5250's Kconfig? # +################################################################# +config SYS_I2C_SPEED + int + default 100000 + +config SYS_I2C_SLAVE + hex + default 0x0 + +config I2C_MULTI_BUS + bool + default y + +#config HARD_I2C +# bool +# default y +#CMD_I2C +#I2C_EDID +#DRIVER_S3C24X0_I2C + +config VDD_ARM_MV + int + default 1300 #1.3V + +config VDD_INT_UV + int + default 1012500 # 1.0125v + +config VDD_MIF_MV + int + default 1000 # 1.0v + +config VDD_G3D_MV + int + default 1200 # 1.2v + +config VDD_LDO2_MV + int + default 1500 # 1.5v + +config VDD_LDO3_MV + int + default 1800 # 1.8v + +config VDD_LDO5_MV + int + default 1800 # 1.8v + +config VDD_LDO10_MV + int + default 1800 # 1.8v + +######### smdk5250.h ######## + +endif # BOARD_GOOGLE_SNOW diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc new file mode 100644 index 0000000..01488d0 --- /dev/null +++ b/src/mainboard/google/snow/Makefile.inc @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#romstage-y += romstage.c + +# ramstage-y += ec.c + +# FIXME: smdk5250_spl and mainboard.c are a mess. In the long +# run we'll want to replace low-level code that calls mainboard code +# with mainboard code that calls low-level code with appropriate +# parameters. Grep around for spl_get_machine_params for examples. +romstage-y += smdk5250_spl.c +ramstage-y += smdk5250_spl.c +#ramstage-y += mainboard.c + +# romstage-$(CONFIG_CHROMEOS) += chromeos.c + +# FIXME: we should do something similar to x86 platforms for Snow SPDs + +SRC_ROOT = $(src)/mainboard/google/snow diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb new file mode 100644 index 0000000..f88835e --- /dev/null +++ b/src/mainboard/google/snow/devicetree.cb @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# FIXME: this is just a stub for now +chip cpu/samsung/exynos5250 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end +end diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c new file mode 100644 index 0000000..00b3e93 --- /dev/null +++ b/src/mainboard/google/snow/mainboard.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2012 The ChromeOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <device/device.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + //dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM ChromeBook", + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c new file mode 100644 index 0000000..29e4555 --- /dev/null +++ b/src/mainboard/google/snow/romstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <system.h> +#include <cache.h> + +static void mmu_setup(void) +{ + dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); +} + +void main(unsigned long bist) +{ + mmu_setup(); +} diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c new file mode 100644 index 0000000..204e411 --- /dev/null +++ b/src/mainboard/google/snow/smdk5250_spl.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/gpio.h> +#include <cpu/samsung/exynos5-common/spl.h> +#include <cpu/samsung/exynos5250/gpio.h> + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirMw", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1700, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), + .mem_manuf = MEM_MANUF_SAMSUNG, + .bad_wake_gpio = GPIO_Y10, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* TODO: Call panic() here */ + while (1) + ; + } + + return &machine_param; +} + +int board_wakeup_permitted(void) +{ + struct spl_machine_param *param = spl_get_machine_params(); + const int gpio = param->bad_wake_gpio; + int is_bad_wake; + + /* We're a bad wakeup if the gpio was defined and was high */ + is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); + + return !is_bad_wake; +}

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coreboot December 2012