coreboot December 2012

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Patch set updated for coreboot: f6df8ac Add minimal mainboard support for snow
by Stefan Reinauer 11 Dec '12

11 Dec '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2018 -gerrit commit f6df8ac9e6817a5a023cb1d1748c97922917f401 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 16:13:43 2012 -0800 Add minimal mainboard support for snow This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/google/snow/Kconfig | 180 +++++++++++++++++++++++++++++++ src/mainboard/google/snow/Makefile.inc | 36 +++++++ src/mainboard/google/snow/devicetree.cb | 26 +++++ src/mainboard/google/snow/mainboard.c | 34 ++++++ src/mainboard/google/snow/romstage.c | 32 ++++++ src/mainboard/google/snow/smdk5250_spl.c | 78 ++++++++++++++ 6 files changed, 386 insertions(+) diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig new file mode 100644 index 0000000..8c465b2 --- /dev/null +++ b/src/mainboard/google/snow/Kconfig @@ -0,0 +1,180 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_SNOW + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_SAMSUNG_EXYNOS5 + select HAVE_UART_MEMORY_MAPPED + select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging +# select EC_GOOGLE_CHROMEEC + select BOARD_ROMSIZE_KB_4096 + select DRIVER_MAXIM_77686 +# select HAVE_ACPI_TABLES +# select MMCONF_SUPPORT +# select CHROMEOS + +config MAINBOARD_DIR + string + default google/snow + +config MAINBOARD_PART_NUMBER + string + default "SNOW" + +#config MMCONF_BASE_ADDRESS +# hex +# default 0xf0000000 + +#config IRQ_SLOT_COUNT +# int +# default 18 + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "Samsung" + +# SPL (second-phase loader) stuff +config SPL_TEXT_BASE + hex + default 0x02023400 + help + Location of SPL. Default location is within iRAM region. + +# FIXME: increased "SPL" size to get around build issues +#config SPL_MAX_SIZE +# hex "SPL executable max size" +# default 0x3800 +# help +# Max size of SPL. Default is 14KB +config SPL_MAX_SIZE + hex + default 0x8000 + help + Max size of SPL. Let's say 32KB for now... + +config DRAM_SIZE_MB + int + default 2048 + +config NR_DRAM_BANKS + int + default 1 + +choice + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART3 + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + default 0x12c00000 if CONSOLE_SERIAL_UART0 + default 0x12c10000 if CONSOLE_SERIAL_UART1 + default 0x12c20000 if CONSOLE_SERIAL_UART2 + default 0x12c30000 if CONSOLE_SERIAL_UART3 + help + Map the UART names to the respective MMIO address. + +################################################################# +# stuff from smdk5250.h # +# FIXME: can we move some of these to exynos5250's Kconfig? # +################################################################# +config SYS_I2C_SPEED + int + default 100000 + +config SYS_I2C_SLAVE + hex + default 0x0 + +config I2C_MULTI_BUS + bool + default y + +#config HARD_I2C +# bool +# default y +#CMD_I2C +#I2C_EDID +#DRIVER_S3C24X0_I2C + +config VDD_ARM_MV + int + default 1300 #1.3V + +config VDD_INT_UV + int + default 1012500 # 1.0125v + +config VDD_MIF_MV + int + default 1000 # 1.0v + +config VDD_G3D_MV + int + default 1200 # 1.2v + +config VDD_LDO2_MV + int + default 1500 # 1.5v + +config VDD_LDO3_MV + int + default 1800 # 1.8v + +config VDD_LDO5_MV + int + default 1800 # 1.8v + +config VDD_LDO10_MV + int + default 1800 # 1.8v + +######### smdk5250.h ######## + +endif # BOARD_GOOGLE_SNOW diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc new file mode 100644 index 0000000..01488d0 --- /dev/null +++ b/src/mainboard/google/snow/Makefile.inc @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#romstage-y += romstage.c + +# ramstage-y += ec.c + +# FIXME: smdk5250_spl and mainboard.c are a mess. In the long +# run we'll want to replace low-level code that calls mainboard code +# with mainboard code that calls low-level code with appropriate +# parameters. Grep around for spl_get_machine_params for examples. +romstage-y += smdk5250_spl.c +ramstage-y += smdk5250_spl.c +#ramstage-y += mainboard.c + +# romstage-$(CONFIG_CHROMEOS) += chromeos.c + +# FIXME: we should do something similar to x86 platforms for Snow SPDs + +SRC_ROOT = $(src)/mainboard/google/snow diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb new file mode 100644 index 0000000..f88835e --- /dev/null +++ b/src/mainboard/google/snow/devicetree.cb @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# FIXME: this is just a stub for now +chip cpu/samsung/exynos5250 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end +end diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c new file mode 100644 index 0000000..00b3e93 --- /dev/null +++ b/src/mainboard/google/snow/mainboard.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2012 The ChromeOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <device/device.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + //dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM ChromeBook", + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c new file mode 100644 index 0000000..29e4555 --- /dev/null +++ b/src/mainboard/google/snow/romstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <system.h> +#include <cache.h> + +static void mmu_setup(void) +{ + dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); +} + +void main(unsigned long bist) +{ + mmu_setup(); +} diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c new file mode 100644 index 0000000..204e411 --- /dev/null +++ b/src/mainboard/google/snow/smdk5250_spl.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/gpio.h> +#include <cpu/samsung/exynos5-common/spl.h> +#include <cpu/samsung/exynos5250/gpio.h> + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirMw", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1700, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), + .mem_manuf = MEM_MANUF_SAMSUNG, + .bad_wake_gpio = GPIO_Y10, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* TODO: Call panic() here */ + while (1) + ; + } + + return &machine_param; +} + +int board_wakeup_permitted(void) +{ + struct spl_machine_param *param = spl_get_machine_params(); + const int gpio = param->bad_wake_gpio; + int is_bad_wake; + + /* We're a bad wakeup if the gpio was defined and was high */ + is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); + + return !is_bad_wake; +}

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Patch merged into coreboot/master: 0dbb329 Remove un-needed i2c.h include
by gerrit＠coreboot.org 11 Dec '12

11 Dec '12

the following patch was just integrated into master: commit 0dbb329b7d3edf9c9ac426e31109bdc14b1b7bf2 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 21:27:02 2012 -0800 Remove un-needed i2c.h include When we need i2c for this cpu we will use the coreboot smbus code. Change-Id: I4ba4cc9ae10e5ca830d621ee9c8d9f7bd2129e2f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Tue Dec 11 06:41:51 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Dec 11 19:50:27 2012, giving +2 See http://review.coreboot.org/2019 for details. -gerrit

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New patch to review for coreboot: 261af0d Remove un-needed i2c.h include
by Ronald G. Minnich 11 Dec '12

11 Dec '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2019 -gerrit commit 261af0dddc7390357feb7fd54545c59e10be31a6 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 21:27:02 2012 -0800 Remove un-needed i2c.h include When we need i2c for this cpu we will use the coreboot smbus code. Change-Id: I4ba4cc9ae10e5ca830d621ee9c8d9f7bd2129e2f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/power.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 5135ae6..f8062d1 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -29,7 +29,6 @@ #include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5250/sysreg.h> #include <cpu/samsung/exynos5-common/spl.h> -#include <device/i2c.h> #include <drivers/power/max77686.h> static void ps_hold_setup(void)

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Patch set updated for coreboot: fc6c4c8 Claim the SPI bus before writes if the IMC ROM is present
by Martin Roth 11 Dec '12

11 Dec '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1976 -gerrit commit fc6c4c8d27978ce041ee9332290e341d10cdedd6 Author: Martin Roth <martin(a)se-eng.com> Date: Wed Dec 5 16:22:54 2012 -0700 Claim the SPI bus before writes if the IMC ROM is present The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin(a)se-eng.com> --- src/cpu/amd/agesa/s3_resume.c | 12 +++++++ src/drivers/spi/eon.c | 1 + src/drivers/spi/gigadevice.c | 1 + src/drivers/spi/macronix.c | 1 + src/drivers/spi/spansion.c | 1 + src/drivers/spi/spi_flash.c | 3 ++ src/drivers/spi/sst.c | 1 + src/drivers/spi/stmicro.c | 1 + src/drivers/spi/winbond.c | 1 + src/include/spi.h | 6 +++- src/southbridge/amd/agesa/hudson/spi.c | 25 +++++++++++++++ src/southbridge/amd/cimx/sb800/spi.c | 57 ++++++++++++++++++++++++++++++++++ 12 files changed, 109 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6302c3d..42e950f 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -165,6 +165,9 @@ void OemAgesaSaveMtrr(void) return; } + flash->spi->rw = SPI_WRITE_FLAG; + spi_claim_bus(flash->spi); + /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -233,6 +236,9 @@ void OemAgesaSaveMtrr(void) flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; + flash->spi->rw = SPI_WRITE_FLAG; + spi_release_bus(flash->spi); + #endif } @@ -273,6 +279,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) return AGESA_SUCCESS; } + flash->spi->rw = SPI_WRITE_FLAG; + spi_claim_bus(flash->spi); + if (S3DataType == S3DataTypeNonVolatile) { flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); } else { @@ -287,6 +296,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); } + flash->spi->rw = SPI_WRITE_FLAG; + spi_release_bus(flash->spi); + return AGESA_SUCCESS; } #endif diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 7d9bc44..d9c654c 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -70,6 +70,7 @@ static int eon_write(struct spi_flash *flash, page_addr = offset / page_size; byte_addr = offset % page_size; + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 0647baf..33c7b58 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -131,6 +131,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); byte_addr = offset % page_size; + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 332de23..acf29c3 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -134,6 +134,7 @@ static int macronix_write(struct spi_flash *flash, page_size = min(mcx->params->page_size, CONTROLLER_PAGE_LIMIT); byte_addr = offset % page_size; + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 511091b..cbfe6d9 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -147,6 +147,7 @@ static int spansion_write(struct spi_flash *flash, page_addr = offset / page_size; byte_addr = offset % page_size; + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 7116cbf..a563e49 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -69,6 +69,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, struct spi_slave *spi = flash->spi; int ret; + spi->rw = SPI_READ_FLAG; spi_claim_bus(spi); ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); spi_release_bus(spi); @@ -148,6 +149,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, return -1; } + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); @@ -257,6 +259,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, return NULL; } + spi->rw = SPI_READ_FLAG; ret = spi_claim_bus(spi); if (ret) { printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index ebeb441..cba95e3 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -151,6 +151,7 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) int ret; u8 cmd[4]; + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index ccdfa00..d902ffa 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -148,6 +148,7 @@ static int stmicro_write(struct spi_flash *flash, page_addr = offset / page_size; byte_addr = offset % page_size; + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 50c2ed4..4f0d596 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -117,6 +117,7 @@ static int winbond_write(struct spi_flash *flash, page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); byte_addr = offset % page_size; + flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); diff --git a/src/include/spi.h b/src/include/spi.h index 5fbe51e..d394531 100644 --- a/src/include/spi.h +++ b/src/include/spi.h @@ -48,6 +48,9 @@ #define SPI_OPCODE_WREN 0x06 #define SPI_OPCODE_FAST_READ 0x0b +#define SPI_READ_FLAG 0x01 +#define SPI_WRITE_FLAG 0x02 + /*----------------------------------------------------------------------- * Representation of a SPI slave, i.e. what we're communicating with. * @@ -55,16 +58,17 @@ * * bus: ID of the bus that the slave is attached to. * cs: ID of the chip select connected to the slave. + * rw: Read or Write flag */ struct spi_slave { unsigned int bus; unsigned int cs; + unsigned int rw; }; /*----------------------------------------------------------------------- * Initialization, must be called once on start up. * - * TODO: I don't think we really need this. */ void spi_init(void); diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 3b54490..aebe4b5 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -25,6 +25,12 @@ #include <device/pci.h> #include <device/pci_ops.h> +#if defined (CONFIG_HUDSON_IMC_FWM) +#include "FchPlatform.h" + +static int bus_claimed = 0; +#endif + static u32 spibar; static void reset_internal_fifo_pointer(void) @@ -92,11 +98,30 @@ int spi_xfer(struct spi_slave *slave, const void *dout, } int spi_claim_bus(struct spi_slave *slave) { +#if defined (CONFIG_HUDSON_IMC_FWM) + + if (slave->rw == SPI_WRITE_FLAG) { + bus_claimed++; + if (bus_claimed == 1) + ImcSleep(NULL); + } +#endif + return 0; } void spi_release_bus(struct spi_slave *slave) { +#if defined (CONFIG_HUDSON_IMC_FWM) + + if (slave->rw == SPI_WRITE_FLAG) { + bus_claimed--; + if (bus_claimed <= 0) { + bus_claimed = 0; + ImcWakeup(NULL); + } + } +#endif } void spi_cs_activate(struct spi_slave *slave) diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 3b54490..46cc741 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -25,6 +25,13 @@ #include <device/pci.h> #include <device/pci_ops.h> +#if defined (CONFIG_SB800_IMC_FWM) +#include "SBPLATFORM.h" +#include <vendorcode/amd/cimx/sb800/ECfan.h> + +static int bus_claimed = 0; +#endif + static u32 spibar; static void reset_internal_fifo_pointer(void) @@ -90,13 +97,63 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return 0; } + +#if defined (CONFIG_SB800_IMC_FWM) + +static void ImcSleep(void) +{ + u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ + u8 reg0_val = 0; /* clear response register */ + u8 reg1_val = 0xB4; /* request ownership flag */ + + WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); + WriteECmsg (MSG_REG1, AccWidthUint8, &reg1_val); + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); + + WaitForEcLDN9MailboxCmdAck(); +} + + +static void ImcWakeup(void) +{ + u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ + u8 reg0_val = 0;; /* clear response register */ + u8 reg1_val = 0xB5; /* release ownership flag */ + + WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); + WriteECmsg (MSG_REG1, AccWidthUint8, &reg1_val); + WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); + + WaitForEcLDN9MailboxCmdAck(); +} +#endif + int spi_claim_bus(struct spi_slave *slave) { +#if defined (CONFIG_SB800_IMC_FWM) + + if (slave->rw == SPI_WRITE_FLAG) { + bus_claimed++; + if (bus_claimed == 1) + ImcSleep(); + } +#endif + return 0; } void spi_release_bus(struct spi_slave *slave) { +#if defined (CONFIG_SB800_IMC_FWM) + + if (slave->rw == SPI_WRITE_FLAG) { + bus_claimed--; + if (bus_claimed <= 0) { + bus_claimed = 0; + ImcWakeup(); + } + } +#endif } void spi_cs_activate(struct spi_slave *slave)

1 0

Patch set updated for coreboot: 4533033 SB800: Add IMC ROM and fan control.
by Martin Roth 11 Dec '12

11 Dec '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1977 -gerrit commit 4533033a0acbfe174f5e7a644ec7a61dd03d6c13 Author: Martin Roth <martin(a)se-eng.com> Date: Wed Dec 5 16:07:11 2012 -0700 SB800: Add IMC ROM and fan control. Add configuration for AMD's IMC ROM and fan registers for cimx/sb800 platforms. - Allows user to add the IMC rom to the build and to configure the location of the "signature" between the allowed positions. - Allows for no fan control, manual setup of SB800 Fan registers, or setup of the IMC fan configuration registers. - Register configuration is done through devicetree.cb. No files need to be added for new platform configuration. - Initial setup is for Persimmon, but may be extended to any cimx/sb800 platform. Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae Signed-off-by: Martin Roth <martin(a)se-eng.com> --- src/mainboard/amd/persimmon/devicetree.cb | 49 +++++ src/southbridge/amd/cimx/sb800/Kconfig | 95 +++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 40 ++++ src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 4 + src/southbridge/amd/cimx/sb800/cfg.c | 1 + src/southbridge/amd/cimx/sb800/chip.h | 198 +++++++++++++++++- src/southbridge/amd/cimx/sb800/fan.c | 311 ++++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/fan.h | 152 ++++++++++++++ src/southbridge/amd/cimx/sb800/late.c | 7 + src/vendorcode/amd/cimx/sb800/OEM.h | 10 + 10 files changed, 866 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 178fd76..bd40a43 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -91,6 +91,55 @@ chip northbridge/amd/agesa/family14/root_complex device pci 16.2 off end # EHCI USB3 register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" + + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + end #southbridge/amd/cimx/sb800 # end # device pci 18.0 # These seem unnecessary diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 4ac2094..2461d97 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -130,5 +130,100 @@ config S3_VOLATILE_POS For a system with S3 feature, the BIOS needs to save some data to non-volitile storage at cold boot stage. +config SB800_IMC_FWM + bool "Add IMC firmware" + default n + help + Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control. + Please contact AMD to obtain the related firmware. + +if SB800_IMC_FWM + +config SB800_IMC_FWM_FILE + string "IMC firmware path and filename" + default "3rdparty/southbridge/amd/sb800/imc.bin" + +choice + prompt "SB800 Firmware ROM Position" + +config SB800_FWM_AT_FFFA0000 + bool "0xFFFA0000" + help + The IMC and GEC ROMs requires a 'signature' located at one of several + fixed locations in memory. The location used shouldn't matter, just + select an area that doesn't conflict with anything else. + +config SB800_FWM_AT_FFF20000 + bool "0xFFF20000" + help + The IMC and GEC ROMs requires a 'signature' located at one of several + fixed locations in memory. The location used shouldn't matter, just + select an area that doesn't conflict with anything else. + +config SB800_FWM_AT_FFE20000 + depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 || BOARD_ROMSIZE_KB_2048 + bool "0xFFE20000" + help + The IMC and GEC ROMs requires a 'signature' located at one of several + fixed locations in memory. The location used shouldn't matter, just + select an area that doesn't conflict with anything else. + +config SB800_FWM_AT_FFC20000 + depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 + bool "0xFFC20000" + help + The IMC and GEC ROMs requires a 'signature' located at one of several + fixed locations in memory. The location used shouldn't matter, just + select an area that doesn't conflict with anything else. + +config SB800_FWM_AT_FF820000 + depends on BOARD_ROMSIZE_KB_8192 + bool "0xFF820000" + help + The IMC and GEC ROMs requires a 'signature' located at one of several + fixed locations in memory. The location used shouldn't matter, just + select an area that doesn't conflict with anything else. + +endchoice + +config SB800_FWM_POSITION + hex + default 0xFFFA0000 if SB800_FWM_AT_FFFA0000 + default 0xFFF20000 if SB800_FWM_AT_FFF20000 + default 0xFFE20000 if SB800_FWM_AT_FFE20000 + default 0xFFC20000 if SB800_FWM_AT_FFC20000 + default 0xFF820000 if SB800_FWM_AT_FFE20000 + +endif #SB800_IMC_FWM + +choice + prompt "Fan Control" + default SB800_NO_FAN_CONTROL + help + Select the method of SB800 fan control to be used. None would be + for either fixed maximum speed fans connected to the SB800 or for + an external chip controlling the fan speeds. Manual control sets + up the SB800 fan control registers. IMC fan control uses the SB800 + IMC to actively control the fan speeds. + +config SB800_NO_FAN_CONTROL + bool "None" + help + No SB800 Fan control - Do not set up the SB800 fan control registers. + +config SB800_MANUAL_FAN_CONTROL + bool "Manual" + help + Configure the SB800 fan control registers in devicetree.cb. + +config SB800_IMC_FAN_CONTROL + bool "IMC Based" + depends on SB800_IMC_FWM + help + Set up the SB800 to use the IMC based Fan controller. This requires + the IMC rom from AMD. Configure the registers in devicetree.cb. + +endchoice + endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index bea9763..064cbc7 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -27,6 +27,8 @@ romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c +ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c +ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c @@ -53,3 +55,41 @@ ifeq ($(CONFIG_SB800_SATA_RAID), y) raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION) raid/misc.bin-type := raw endif + +ifeq ($(CONFIG_SB800_IMC_FWM), y) + +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address | | +# +-----------+---------------+----------------+------------+ +# EC ROM should be 64K aligned. +SB800_FWM_POSITION=$(shell printf %u $(CONFIG_SB800_FWM_POSITION)) +#assume the cbfs header is less than 128 bytes. +ROMSIG_SIZE=16 + +SB800_IMC_POSITION_UNALIGN=$(shell echo $(SB800_FWM_POSITION) $(ROMSIG_SIZE) 128 65535 | awk '{print $$1 + $$2 + $$3 + $$4}') +SB800_IMC_POSITION=$(shell echo $(SB800_IMC_POSITION_UNALIGN) | awk '{print $$1 - $$1 % 65536}') + +$(obj)/coreboot_SB800_romsig.bin: \ + $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) \ + $(obj)/config.h \ + $(obj)/mainboard/$(MAINBOARDDIR)/static.c + echo " SB800 FW $@" + for fwm in 1437226410 \ + $(SB800_IMC_POSITION) \ + 0 \ + 0 ; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done > $@ + +cbfs-files-y += SB800/fwm +SB800/fwm-file := $(obj)/coreboot_SB800_romsig.bin +SB800/fwm-position := $(SB800_FWM_POSITION) +SB800/fwm-type := raw + +cbfs-files-y += SB800/imc +SB800/imc-file := $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) +SB800/imc-position := $(SB800_IMC_POSITION) +SB800/imc-type := raw + +endif diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 22d7724..1966eb4 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -57,6 +57,10 @@ typedef union _PCI_ADDR { #endif #define FIXUP_PTR(ptr) ptr +#if CONFIG_SB800_IMC_FWM + #define IMC_ENABLE_OVER_WRITE 0x01 +#endif + #include <console/console.h> #include "AmdSbLib.h" #include "Amd.h" diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 71fea67..ebc9918 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -112,6 +112,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->BuildParameters.PCIBSsid = PCIB_SSID; sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type; sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; /* General */ sb_config->SpreadSpectrum = SPREAD_SPECTRUM; diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h index 7fc7b88..4742c6f 100644 --- a/src/southbridge/amd/cimx/sb800/chip.h +++ b/src/southbridge/amd/cimx/sb800/chip.h @@ -19,6 +19,7 @@ #ifndef _CIMX_SB800_CHIP_H_ #define _CIMX_SB800_CHIP_H_ +#include "fan.h" /* include for #defines used in devicetree.cb */ /* * configuration set in mainboard/devicetree.cb @@ -35,6 +36,201 @@ struct southbridge_amd_cimx_sb800_config { u32 boot_switch_sata_ide : 1; u8 gpp_configuration; -}; + /* + * SB800 IMC and fan control + */ + + u16 imc_port_address; + + u32 fan0_enabled : 1; + u32 fan1_enabled : 1; + u32 fan2_enabled : 1; + u32 fan3_enabled : 1; + u32 fan4_enabled : 1; + u32 imc_fan_zone0_enabled : 1; + u32 imc_fan_zone1_enabled : 1; + u32 imc_fan_zone2_enabled : 1; + u32 imc_fan_zone3_enabled : 1; + u32 imc_tempin0_enabled : 1; + u32 imc_tempin1_enabled : 1; + u32 imc_tempin2_enabled : 1; + u32 imc_tempin3_enabled : 1; + + union { + struct { + u8 fan0_control_reg_value; + u8 fan0_frequency_reg_value; + u8 fan0_low_duty_reg_value; + u8 fan0_med_duty_reg_value; + u8 fan0_multiplier_reg_value; + u8 fan0_low_temp_lo_reg_value; + u8 fan0_low_temp_hi_reg_value; + u8 fan0_med_temp_lo_reg_value; + u8 fan0_med_temp_hi_reg_value; + u8 fan0_high_temp_lo_reg_value; + u8 fan0_high_temp_hi_reg_value; + u8 fan0_linear_range_reg_value; + u8 fan0_linear_hold_reg_value; + }; + u8 fan0_config_vals[FAN_REGISTER_COUNT]; + }; + + union { + struct { + u8 fan1_control_reg_value; + u8 fan1_frequency_reg_value; + u8 fan1_low_duty_reg_value; + u8 fan1_med_duty_reg_value; + u8 fan1_multiplier_reg_value; + u8 fan1_low_temp_lo_reg_value; + u8 fan1_low_temp_hi_reg_value; + u8 fan1_med_temp_lo_reg_value; + u8 fan1_med_temp_hi_reg_value; + u8 fan1_high_temp_lo_reg_value; + u8 fan1_high_temp_hi_reg_value; + u8 fan1_linear_range_reg_value; + u8 fan1_linear_hold_reg_value; + }; + u8 fan1_config_vals[FAN_REGISTER_COUNT]; + }; + + union { + struct { + u8 fan2_control_reg_value; + u8 fan2_frequency_reg_value; + u8 fan2_low_duty_reg_value; + u8 fan2_med_duty_reg_value; + u8 fan2_multiplier_reg_value; + u8 fan2_low_temp_lo_reg_value; + u8 fan2_low_temp_hi_reg_value; + u8 fan2_med_temp_lo_reg_value; + u8 fan2_med_temp_hi_reg_value; + u8 fan2_high_temp_lo_reg_value; + u8 fan2_high_temp_hi_reg_value; + u8 fan2_linear_range_reg_value; + u8 fan2_linear_hold_reg_value; + }; + u8 fan2_config_vals[FAN_REGISTER_COUNT]; + }; + + union { + struct { + u8 fan3_control_reg_value; + u8 fan3_frequency_reg_value; + u8 fan3_low_duty_reg_value; + u8 fan3_med_duty_reg_value; + u8 fan3_multiplier_reg_value; + u8 fan3_low_temp_lo_reg_value; + u8 fan3_low_temp_hi_reg_value; + u8 fan3_med_temp_lo_reg_value; + u8 fan3_med_temp_hi_reg_value; + u8 fan3_high_temp_lo_reg_value; + u8 fan3_high_temp_hi_reg_value; + u8 fan3_linear_range_reg_value; + u8 fan3_linear_hold_reg_value; + }; + u8 fan3_config_vals[FAN_REGISTER_COUNT]; + }; + + union { + struct { + u8 fan4_control_reg_value; + u8 fan4_frequency_reg_value; + u8 fan4_low_duty_reg_value; + u8 fan4_med_duty_reg_value; + u8 fan4_multiplier_reg_value; + u8 fan4_low_temp_lo_reg_value; + u8 fan4_low_temp_hi_reg_value; + u8 fan4_med_temp_lo_reg_value; + u8 fan4_med_temp_hi_reg_value; + u8 fan4_high_temp_lo_reg_value; + u8 fan4_high_temp_hi_reg_value; + u8 fan4_linear_range_reg_value; + u8 fan4_linear_hold_reg_value; + }; + u8 fan4_config_vals[FAN_REGISTER_COUNT]; + }; + + union { + struct { + u8 imc_zone0_mode1; + u8 imc_zone0_mode2; + u8 imc_zone0_temp_offset; + u8 imc_zone0_hysteresis; + u8 imc_zone0_smbus_addr; + u8 imc_zone0_smbus_num; + u8 imc_zone0_pwm_step; + u8 imc_zone0_ramping; + }; + u8 imc_zone0_config_vals[IMC_FAN_CONFIG_COUNT]; + }; + u8 imc_zone0_thresholds[IMC_FAN_THRESHOLD_COUNT]; + u8 imc_zone0_fanspeeds[IMC_FAN_SPEED_COUNT]; + + union { + struct { + u8 imc_zone1_mode1; + u8 imc_zone1_mode2; + u8 imc_zone1_temp_offset; + u8 imc_zone1_hysteresis; + u8 imc_zone1_smbus_addr; + u8 imc_zone1_smbus_num; + u8 imc_zone1_pwm_step; + u8 imc_zone1_ramping; + }; + u8 imc_zone1_config_vals[IMC_FAN_CONFIG_COUNT]; + }; + u8 imc_zone1_thresholds[IMC_FAN_THRESHOLD_COUNT]; + u8 imc_zone1_fanspeeds[IMC_FAN_SPEED_COUNT]; + + union { + struct { + u8 imc_zone2_mode1; + u8 imc_zone2_mode2; + u8 imc_zone2_temp_offset; + u8 imc_zone2_hysteresis; + u8 imc_zone2_smbus_addr; + u8 imc_zone2_smbus_num; + u8 imc_zone2_pwm_step; + u8 imc_zone2_ramping; + }; + u8 imc_zone2_config_vals[IMC_FAN_CONFIG_COUNT]; + }; + u8 imc_zone2_thresholds[IMC_FAN_THRESHOLD_COUNT]; + u8 imc_zone2_fanspeeds[IMC_FAN_SPEED_COUNT]; + + union { + struct { + u8 imc_zone3_mode1; + u8 imc_zone3_mode2; + u8 imc_zone3_temp_offset; + u8 imc_zone3_hysteresis; + u8 imc_zone3_smbus_addr; + u8 imc_zone3_smbus_num; + u8 imc_zone3_pwm_step; + u8 imc_zone3_ramping; + }; + u8 imc_zone3_config_vals[IMC_FAN_CONFIG_COUNT]; + }; + u8 imc_zone3_thresholds[IMC_FAN_THRESHOLD_COUNT]; + u8 imc_zone3_fanspeeds[IMC_FAN_SPEED_COUNT]; + + u32 imc_tempin0_at; + u32 imc_tempin0_ct; + u8 imc_tempin0_tuning_param; + + u32 imc_tempin1_at; + u32 imc_tempin1_ct; + u8 imc_tempin1_tuning_param; + + u32 imc_tempin2_at; + u32 imc_tempin2_ct; + u8 imc_tempin2_tuning_param; + + u32 imc_tempin3_at; + u32 imc_tempin3_ct; + u8 imc_tempin3_tuning_param; + +}; #endif /* _CIMX_SB800_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c new file mode 100644 index 0000000..115da65 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <southbridge/amd/cimx/cimx_util.h> +#include <device/device.h> /* device_t */ +#include <device/pci.h> /* device_operations */ +#include "SBPLATFORM.h" +#include "sb_cimx.h" +#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ +#include "fan.h" + +void init_sb800_MANUAL_fans(device_t dev) +{ + int i; + struct southbridge_amd_cimx_sb800_config *sb_chip = + (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); + + /* Init Fan 0 */ + if (sb_chip->fan0_enabled) + for (i = 0; i < FAN_REGISTER_COUNT; i++) + pm2_iowrite(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); + + /* Init Fan 1 */ + if (sb_chip->fan1_enabled) + for (i = 0; i < FAN_REGISTER_COUNT; i++) + pm2_iowrite(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); + + /* Init Fan 2 */ + if (sb_chip->fan2_enabled) + for (i = 0; i < FAN_REGISTER_COUNT; i++) + pm2_iowrite(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); + + /* Init Fan 3 */ + if (sb_chip->fan3_enabled) + for (i = 0; i < FAN_REGISTER_COUNT; i++) + pm2_iowrite(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); + + /* Init Fan 4 */ + if (sb_chip->fan4_enabled) + for (i = 0; i < FAN_REGISTER_COUNT; i++) + pm2_iowrite(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); + +} + +void init_sb800_IMC_fans(device_t dev) +{ + + AMDSBCFG sb_config; + unsigned char *message_ptr; + int i; + struct southbridge_amd_cimx_sb800_config *sb_chip = + (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); + + /* + * The default I/O address of the IMC configuration register index + * port is 0x6E. Change the IMC Config port I/O Address if it + * conflicts with other components in the system. + * + * Device 20, Function 3, Reg 0xA4 + * [0]: if 1, the address specified in IMC_PortAddress is used. + * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E ) + */ + + pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01); + + + /* + * Do an initial manual setup of the fans for things like polarity + * and frequency. + */ + init_sb800_MANUAL_fans(dev); + + /* + * FLAG for Func 81/83/85/89 support (1=On,0=Off) + * Bit0-3 = Func 81 Zone0-Zone3 + * Bit4-7 = Func 83 Zone0-Zone3 + * Bit8-11 = Func 85 Zone0-Zone3 + * Bit12-15 = Func 89 Tempin Channel0-Channel3 + */ + sb_config.Pecstruct.IMCFUNSupportBitMap = 0; + +/* + ********** Zone 0 ********** + */ +if (sb_chip->imc_fan_zone0_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE0; + + /* EC LDN9 function 81 zone 0 */ + sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; + message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; + for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; + + /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ + sb_config.Pecstruct.MSGFun83zone0MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; + sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; + message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; + + /*EC LDN9 function 85 zone 0 - Fan Speeds */ + sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; + message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; + for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; + +} + +/* + ********** Zone 1 ********** + */ +if (sb_chip->imc_fan_zone1_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE1; + + /* EC LDN9 function 81 zone 1 */ + sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; + message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; + for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; + + /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ + sb_config.Pecstruct.MSGFun83zone1MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; + sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; + message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; + + /* EC LDN9 function 85 zone 1 - Fan Speeds */ + sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; + message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; + for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; + +} + + +/* + ********** Zone 2 ********** + */ +if (sb_chip->imc_fan_zone2_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE2; + + /* EC LDN9 function 81 zone 2 */ + sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; + message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; + for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; + + /* EC LDN9 function 83 zone 2 */ + sb_config.Pecstruct.MSGFun83zone2MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; + sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; + message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; + + /* EC LDN9 function 85 zone 2 */ + sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; + message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; + for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; + +} + +/* + ********** Zone 3 ********** + */ + +if (sb_chip->imc_fan_zone3_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE3; + + /* EC LDN9 function 81 zone 3 */ + sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; + message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; + for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; + + /* EC LDN9 function 83 zone 3 */ + sb_config.Pecstruct.MSGFun83zone3MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; + sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; + message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; + + /* EC LDN9 function 85 zone 3 */ + sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; + message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; + for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ ) + *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; + +} + + /* + * EC LDN9 funtion 89 - Set HWM TEMPIN Temperature Calculation Parameters + * This function provides the critical parameters of the HWM TempIn + * sensors, IMC would not perform temperature measurement using those + * sensors until the parameters are provided. + */ + +if (sb_chip->imc_tempin0_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN0; + + /* EC LDN9 funtion 89 TEMPIN channel 0 */ + sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00; + sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG6 = ( sb_chip->imc_tempin0_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREGA = sb_chip->imc_tempin0_tuning_param; +} + +if (sb_chip->imc_tempin1_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN1; + + /* EC LDN9 funtion 89 TEMPIN channel 1 */ + sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01; + sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG3 = ((sb_chip->imc_tempin1_at >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG4 = ((sb_chip->imc_tempin1_at >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG5 = ((sb_chip->imc_tempin1_at >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG6 = ( sb_chip->imc_tempin1_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG7 = ((sb_chip->imc_tempin1_ct >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG8 = ((sb_chip->imc_tempin1_ct >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG9 = ((sb_chip->imc_tempin1_ct >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREGA = sb_chip->imc_tempin1_tuning_param; +} + +if (sb_chip->imc_tempin2_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN2; + + /* EC LDN9 funtion 89 TEMPIN channel 2 */ + sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02; + sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG3 = ((sb_chip->imc_tempin2_at >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG4 = ((sb_chip->imc_tempin2_at >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG5 = ((sb_chip->imc_tempin2_at >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG6 = ( sb_chip->imc_tempin2_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG7 = ((sb_chip->imc_tempin2_ct >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG8 = ((sb_chip->imc_tempin2_ct >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG9 = ((sb_chip->imc_tempin2_ct >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREGA = sb_chip->imc_tempin2_tuning_param; +} + +if (sb_chip->imc_tempin3_enabled) { + + sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN3; + + /* EC LDN9 funtion 89 TEMPIN channel 3 */ + sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00; + sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03; + sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG3 = ((sb_chip->imc_tempin3_at >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG4 = ((sb_chip->imc_tempin3_at >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG5 = ((sb_chip->imc_tempin3_at >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG6 = ( sb_chip->imc_tempin3_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG7 = ((sb_chip->imc_tempin3_ct >> 8) & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG8 = ((sb_chip->imc_tempin3_ct >> 16) & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG9 = ((sb_chip->imc_tempin3_ct >> 24) & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREGA = sb_chip->imc_tempin3_tuning_param; +} + + /* Set up the sb_config structure for the fan control initialization */ + sb_config.StdHeader.Func = SB_EC_FANCONTROL; + + AmdSbDispatcher(&sb_config); + + return; +} + + diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h new file mode 100644 index 0000000..a0fc04e --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB800_FAN_H_ +#define _SB800_FAN_H_ + +#ifndef __PRE_RAM__ +void init_sb800_IMC_fans(device_t dev); +void init_sb800_MANUAL_fans(device_t dev); +#endif + +/* Fan Register Definitions */ +#define FAN_0_OFFSET 0x00 +#define FAN_1_OFFSET 0x10 +#define FAN_2_OFFSET 0x20 +#define FAN_3_OFFSET 0x30 +#define FAN_4_OFFSET 0x40 + +#define FAN_INPUT_CONTROL_REG 0x00 +#define FAN_CONTROL_REG 0x01 +#define FAN_FREQUENCY_REG 0x02 +#define FAN_LOW_DUTY_REG 0x03 +#define FAN_MED_DUTY_REG 0x04 +#define FAN_MULTIPLIER_REG 0x05 +#define FAN_LOW_TEMP_LO_REG 0x06 +#define FAN_LOW_TEMP_HI_REG 0x07 +#define FAN_MED_TEMP_LO_REG 0x08 +#define FAN_MED_TEMP_HI_REG 0x09 +#define FAN_HIGH_TEMP_LO_REG 0x0A +#define FAN_HIGH_TEMP_HI_REG 0x0B +#define FAN_LINEAR_RANGE_REG 0x0C +#define FAN_LINEAR_HOLD_REG 0x0D + +/* FanXInputControl Definitions */ +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +/* FanXControl Definitions */ +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE 0 /* ~(1 << 1) */ +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW 0 /*~(1 << 2) */ + +/* FanXLowDuty Definitions */ +#define FAN_POLARITY_HIGH_MAX_SPEED 0xff +#define FAN_POLARITY_LOW_MAX_SPEED 0x00 + +/* FanXFreq Definitions */ +/* Typically, fans run at 25KHz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +/* Any value > 05h and < F7: Freq = 1/(FreqDiv * 2048 * 15ns) */ +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + + +/* IMC Fan Control Definitions */ +#define IMC_MODE1_FAN_ENABLED ( 1 << 0 ) +#define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 ) +#define IMC_MODE1_FAN_LINEAR_MODE ( 1 << 4 ) +#define IMC_MODE1_FAN_STEP_MODE 0 /* ~( 1 << 4 ) */ +#define IMC_MODE1_NO_FANOUT 0 /* ~( 7 << 5 ) */ +#define IMC_MODE1_FANOUT0 ( 1 << 5 ) +#define IMC_MODE1_FANOUT1 ( 2 << 5 ) +#define IMC_MODE1_FANOUT2 ( 3 << 5 ) +#define IMC_MODE1_FANOUT3 ( 4 << 5 ) +#define IMC_MODE1_FANOUT4 ( 5 << 5 ) + +#define IMC_MODE2_TEMPIN_NONE 0 /* ~( 7 << 0) */ +#define IMC_MODE2_TEMPIN_0 1 +#define IMC_MODE2_TEMPIN_1 2 +#define IMC_MODE2_TEMPIN_2 3 +#define IMC_MODE2_TEMPIN_3 4 +#define IMC_MODE2_INT_TEMPIN 5 +#define IMC_MODE2_TEMPIN_SB_TSI 6 +#define IMC_MODE2_TEMPIN_OTHER 7 +#define IMC_MODE2_FANIN_NONE 0 /* ~ (7 << 3) */ +#define IMC_MODE2_FANIN0 ( 1 << 3 ) +#define IMC_MODE2_FANIN1 ( 2 << 3 ) +#define IMC_MODE2_FANIN2 ( 3 << 3 ) +#define IMC_MODE2_FANIN3 ( 4 << 3 ) +#define IMC_MODE2_FANIN4 ( 5 << 3 ) +#define IMC_MODE2_TEMP_AVERAGING_ENABLED ( 1 << 6 ) +#define IMC_MODE2_TEMP_AVERAGING_DISABLED 0 /* ~( 1 << 6 ) */ + +#define IMC_TEMP_SENSOR_ON_SMBUS_0 0 +#define IMC_TEMP_SENSOR_ON_SMBUS_2 1 +#define IMC_TEMP_SENSOR_ON_SMBUS_3 2 +#define IMC_TEMP_SENSOR_ON_SMBUS_4 3 + +#define IMC_ZONE0 0 +#define IMC_ZONE1 1 +#define IMC_ZONE2 2 +#define IMC_ZONE3 3 +#define IMC_ZONE4 4 + +#define IMC_TEMPIN_TUNING_DEFAULT_MODE 0 +#define IMC_TEMPIN_TUNING_HIGH_CURRENT_RATIO 1 +#define IMC_TEMPIN_TUNING_HIGH_CURRENT 2 +#define IMC_TEMPIN_TUNING_DISABLE_FILTERING ( 1 << 2 ) + +/* IMCFUNSupportBitMap - Zone enable values */ +#define IMC_ENABLE_ZONE0 0x111 +#define IMC_ENABLE_ZONE1 0x222 +#define IMC_ENABLE_ZONE2 0x333 +#define IMC_ENABLE_ZONE3 0x444 +#define IMC_ENABLE_TEMPIN0 ( 1 << 12 ) +#define IMC_ENABLE_TEMPIN1 ( 1 << 13 ) +#define IMC_ENABLE_TEMPIN2 ( 1 << 14 ) +#define IMC_ENABLE_TEMPIN3 ( 1 << 15 ) + +/* Array size settings */ +#define IMC_FAN_THRESHOLD_COUNT 9 +#define IMC_FAN_SPEED_COUNT 8 +#define IMC_FAN_CONFIG_COUNT 8 +#define FAN_REGISTER_COUNT 15 + +#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 6067e39..ef3a34b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -32,6 +32,7 @@ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "smbus.h" +#include "fan.h" /*implement in mainboard.c*/ void set_pcie_reset(void); @@ -418,6 +419,12 @@ static void sb800_enable(device_t dev) case (0x14 << 3) | 3: /* 0:14:3 LPC */ + /* Initialize the fans */ +#if CONFIG_SB800_IMC_FAN_CONTROL + init_sb800_IMC_fans(dev); +#elif CONFIG_SB800_MANUAL_FAN_CONTROL + init_sb800_MANUAL_fans(dev); +#endif break; case (0x14 << 3) | 4: /* 0:14:4 PCI */ diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h index c2d8670..640f740 100644 --- a/src/vendorcode/amd/cimx/sb800/OEM.h +++ b/src/vendorcode/amd/cimx/sb800/OEM.h @@ -293,3 +293,13 @@ #ifndef Spread_Spectrum_Type #define Spread_Spectrum_Type 0x00 #endif + +/** + * Imc Enable OverWrite + * 2 - by default strapping + * 1 - On + * 0 - Off + */ +#ifndef IMC_ENABLE_OVER_WRITE + #define IMC_ENABLE_OVER_WRITE 0x02 +#endif

1 0

Patch set updated for coreboot: c47c0b6 Add include file for i2c code
by Ronald G. Minnich 11 Dec '12

11 Dec '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2016 -gerrit commit c47c0b6350b8acbd99d6fa4c459ffd295b97c755 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 13:59:07 2012 -0800 Add include file for i2c code This formalizes a lot of i2c defines that can be placed here. Change-Id: Id378bac5ae719bd3f5063f18dc8b34486add73d2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/include/device/i2c.h | 279 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h new file mode 100644 index 0000000..f1275e3 --- /dev/null +++ b/src/include/device/i2c.h @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * The original I2C interface was + * (C) 2000 by Paolo Scaffardi (arsenio(a)tin.it) + * AIRVENT SAM s.p.a - RIMINI(ITALY) + * but has been changed substantially. + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +/* + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + * + * The implementation MUST NOT use static or global variables if the + * I2C routines are used to read SDRAM configuration information + * because this is done before the memories are initialized. Limited + * use of stack-based variables are OK (the initial stack size is + * limited). + * + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + */ + +/* + * Configuration items. + */ +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + +#ifdef CONFIG_I2C_MULTI_BUS +#define MAX_I2C_BUS 2 +#define I2C_MULTI_BUS 1 +#else +#define MAX_I2C_BUS 1 +#define I2C_MULTI_BUS 0 +#endif + +#if !defined(CONFIG_SYS_MAX_I2C_BUS) +#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS +#endif + +/* define the I2C bus number for RTC and DTT if not already done */ +#if !defined(CONFIG_SYS_RTC_BUS_NUM) +#define CONFIG_SYS_RTC_BUS_NUM 0 +#endif +#if !defined(CONFIG_SYS_DTT_BUS_NUM) +#define CONFIG_SYS_DTT_BUS_NUM 0 +#endif +#if !defined(CONFIG_SYS_SPD_BUS_NUM) +#define CONFIG_SYS_SPD_BUS_NUM 0 +#endif + +#ifndef I2C_SOFT_DECLARATIONS +# if defined(CONFIG_MPC8260) +# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); +# elif defined(CONFIG_8xx) +# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + +# elif (defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; +# else +# define I2C_SOFT_DECLARATIONS +# endif +#endif + +#ifdef CONFIG_8xx +/* Set default value for the I2C bus speed on 8xx. In the + * future, we'll define these in all 8xx board config files. + */ +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 +#endif +#endif + +/* + * Many boards/controllers/drivers don't support an I2C slave interface so + * provide a default slave address for them for use in common code. A real + * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does + * support a slave interface. + */ +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xfe +#endif + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr); +void i2c_init_board(void); +#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT +void i2c_board_late_init(void); +#endif + +#if defined(CONFIG_I2C_MUX) + +typedef struct _mux { + uchar chip; + uchar channel; + char *name; + struct _mux *next; +} I2C_MUX; + +typedef struct _mux_device { + int busid; + I2C_MUX *mux; /* List of muxes, to reach the device */ + struct _mux_device *next; +} I2C_MUX_DEVICE; + +I2C_MUX_DEVICE *i2c_mux_search_device(int id); +I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf); +int i2x_mux_select_mux(int bus); +int i2c_mux_ident_muxstring_f (uchar *buf); +#endif + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +static inline u8 i2c_reg_read(u8 addr, u8 reg) +{ + u8 buf; + +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); +#endif + + i2c_read(addr, reg, 1, &buf, 1); + + return buf; +} + +static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) +{ +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", + __func__, addr, reg, val); +#endif + + i2c_write(addr, reg, 1, &val, 1); +} + +/* + * Functions for setting the current I2C bus and its speed + */ + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus); + +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ + +unsigned int i2c_get_bus_num(void); + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_speed(unsigned int); + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void); + +/* NOTE: These two functions MUST be always_inline to avoid code growth! */ +static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); +static inline unsigned int I2C_GET_BUS(void) +{ + return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; +} + +static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); +static inline void I2C_SET_BUS(unsigned int bus) +{ + if (I2C_MULTI_BUS) + i2c_set_bus_num(bus); +} + +/* + * Set an early register base for a given i2c peripheral. + * This is used to access a single i2c bus early on in the boot sequence. + * + * @param base: The base address of the i2c peripheral's register map + */ +void i2c_set_early_reg(unsigned int base); + +/** + * Find the I2C bus number by given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return the number of I2C bus (zero based), or -1 on error + */ +int i2c_get_bus_num_fdt(const void *blob, int node); + +/** + * Reset the I2C bus represented by the given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return 0 if port was reset, -1 if not found + */ +int i2c_reset_port_fdt(const void *blob, int node); + +#endif /* _I2C_H_ */

1 0

Patch set updated for coreboot: 5d4b0b8 Add minimal mainboard support for snow
by Ronald G. Minnich 11 Dec '12

11 Dec '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2018 -gerrit commit 5d4b0b84066ccdbe3eee4527acb37932fa557f78 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 16:13:43 2012 -0800 Add minimal mainboard support for snow This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/google/snow/Kconfig | 161 +++++++++++++++++++++++++++++++ src/mainboard/google/snow/Makefile.inc | 36 +++++++ src/mainboard/google/snow/board.h | 33 +++++++ src/mainboard/google/snow/devicetree.cb | 7 ++ src/mainboard/google/snow/mainboard.c | 37 +++++++ src/mainboard/google/snow/romstage.c | 33 +++++++ src/mainboard/google/snow/smdk5250_spl.c | 81 ++++++++++++++++ 7 files changed, 388 insertions(+) diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig new file mode 100644 index 0000000..98ffa0e --- /dev/null +++ b/src/mainboard/google/snow/Kconfig @@ -0,0 +1,161 @@ +if BOARD_GOOGLE_SNOW + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_SAMSUNG_EXYNOS5 + select HAVE_UART_MEMORY_MAPPED + select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging +# select EC_GOOGLE_CHROMEEC + select BOARD_ROMSIZE_KB_4096 + select DRIVER_MAXIM_77686 +# select HAVE_ACPI_TABLES +# select MMCONF_SUPPORT +# select CHROMEOS + +config MAINBOARD_DIR + string + default google/snow + +config MAINBOARD_PART_NUMBER + string + default "SNOW" + +#config MMCONF_BASE_ADDRESS +# hex +# default 0xf0000000 + +#config IRQ_SLOT_COUNT +# int +# default 18 + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "Samsung" + +# SPL (second-phase loader) stuff +config SPL_TEXT_BASE + hex "SPL executable base" + default 0x02023400 + help + Location of SPL. Default location is within iRAM region. + +#FIXME: increased "SPL" size to get around build issues +#config SPL_MAX_SIZE +# hex "SPL executable max size" +# default 0x3800 +# help +# Max size of SPL. Default is 14KB +config SPL_MAX_SIZE + hex "SPL executable max size" + default 0x8000 + help + Max size of SPL. Let's say 32KB for now... + +config DRAM_SIZE_MB + int "DRAM size (MB)" + default 2048 + +config NR_DRAM_BANKS + int "Number of DRAM banks" + default 1 + +choice + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART3 + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + default 0x12c00000 if CONSOLE_SERIAL_UART0 + default 0x12c10000 if CONSOLE_SERIAL_UART1 + default 0x12c20000 if CONSOLE_SERIAL_UART2 + default 0x12c30000 if CONSOLE_SERIAL_UART3 + help + Map the UART names to the respective MMIO address. + +################################################################# +# stuff from smdk5250.h # +# FIXME: can we move some of these to exynos5250's Kconfig? # +################################################################# +config SYS_I2C_SPEED + int + default 100000 + +config SYS_I2C_SLAVE + hex + default 0x0 + +config I2C_MULTI_BUS + bool + default y + +#config HARD_I2C +# bool +# default y +#CMD_I2C +#I2C_EDID +#DRIVER_S3C24X0_I2C + +config VDD_ARM_MV + int + default 1300 #1.3V + +config VDD_INT_UV + int + default 1012500 # 1.0125v + +config VDD_MIF_MV + int + default 1000 # 1.0v + +config VDD_G3D_MV + int + default 1200 # 1.2v + +config VDD_LDO2_MV + int + default 1500 # 1.5v + +config VDD_LDO3_MV + int + default 1800 # 1.8v + +config VDD_LDO5_MV + int + default 1800 # 1.8v + +config VDD_LDO10_MV + int + default 1800 # 1.8v + +######### smdk5250.h ######## + +endif # BOARD_GOOGLE_SNOW diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc new file mode 100644 index 0000000..01488d0 --- /dev/null +++ b/src/mainboard/google/snow/Makefile.inc @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#romstage-y += romstage.c + +# ramstage-y += ec.c + +# FIXME: smdk5250_spl and mainboard.c are a mess. In the long +# run we'll want to replace low-level code that calls mainboard code +# with mainboard code that calls low-level code with appropriate +# parameters. Grep around for spl_get_machine_params for examples. +romstage-y += smdk5250_spl.c +ramstage-y += smdk5250_spl.c +#ramstage-y += mainboard.c + +# romstage-$(CONFIG_CHROMEOS) += chromeos.c + +# FIXME: we should do something similar to x86 platforms for Snow SPDs + +SRC_ROOT = $(src)/mainboard/google/snow diff --git a/src/mainboard/google/snow/board.h b/src/mainboard/google/snow/board.h new file mode 100644 index 0000000..bedd740 --- /dev/null +++ b/src/mainboard/google/snow/board.h @@ -0,0 +1,33 @@ +/* + * Board header file for Exynos boards + * + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SAMSUNG_BOARD_H +#define __SAMSUNG_BOARD_H + +/* Init the SPI driver */ +void spi_init(void); + +/* Init the I2C driver */ +void board_i2c_init(const void *blob); + +#endif diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb new file mode 100644 index 0000000..1d9d553 --- /dev/null +++ b/src/mainboard/google/snow/devicetree.cb @@ -0,0 +1,7 @@ +# FIXME: this is just a stub for now +chip cpu/samsung/exynos5250 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end +end diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c new file mode 100644 index 0000000..8e51b73 --- /dev/null +++ b/src/mainboard/google/snow/mainboard.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 The ChromeOS Authors + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <device/device.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + //dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM ChromeBook", + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c new file mode 100644 index 0000000..a059f2b --- /dev/null +++ b/src/mainboard/google/snow/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <system.h> +#include <cache.h> + +static void mmu_setup(void) +{ + dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); +} + +void main(unsigned long bist) +{ + mmu_setup(); +} diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c new file mode 100644 index 0000000..f3a88f3 --- /dev/null +++ b/src/mainboard/google/snow/smdk5250_spl.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/gpio.h> +#include <cpu/samsung/exynos5-common/spl.h> +#include <cpu/samsung/exynos5250/gpio.h> + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirMw", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1700, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), + .mem_manuf = MEM_MANUF_SAMSUNG, + .bad_wake_gpio = GPIO_Y10, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* TODO: Call panic() here */ + while (1) + ; + } + + return &machine_param; +} + +int board_wakeup_permitted(void) +{ + struct spl_machine_param *param = spl_get_machine_params(); + const int gpio = param->bad_wake_gpio; + int is_bad_wake; + + /* We're a bad wakeup if the gpio was defined and was high */ + is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); + + return !is_bad_wake; +}

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Patch merged into coreboot/master: ae06e61 Correct the location of the include file
by gerrit＠coreboot.org 11 Dec '12

11 Dec '12

the following patch was just integrated into master: commit ae06e61ee388c02f4c446cb6af65980070de87ce Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 14:51:09 2012 -0800 Correct the location of the include file The max include file is in src/drivers/power. Change-Id: I2e663b472cade17fc50edbb449c0e54fd4a991eb Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2017 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Mon Dec 10 23:58:18 2012, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Dec 11 02:21:36 2012, giving +2 See http://review.coreboot.org/2017 for details. -gerrit

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New patch to review for coreboot: ad10188 Add minimal mainboard support for snow
by Ronald G. Minnich 11 Dec '12

11 Dec '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2018 -gerrit commit ad1018829dd9a9c526caae9313f60b95f10bf6ea Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Dec 10 16:13:43 2012 -0800 Add minimal mainboard support for snow This is the minimal set of sources that allow the board to build. These need to be filled in with actual code. But if we get these in upstream we can stop working against a WIP patch. Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/google/snow/Kconfig | 161 +++++++++++++++++++++++++++++++ src/mainboard/google/snow/Makefile.inc | 36 +++++++ src/mainboard/google/snow/board.h | 33 +++++++ src/mainboard/google/snow/devicetree.cb | 7 ++ src/mainboard/google/snow/mainboard.c | 37 +++++++ src/mainboard/google/snow/romstage.c | 33 +++++++ src/mainboard/google/snow/smdk5250_spl.c | 81 ++++++++++++++++ 7 files changed, 388 insertions(+) diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig new file mode 100644 index 0000000..98ffa0e --- /dev/null +++ b/src/mainboard/google/snow/Kconfig @@ -0,0 +1,161 @@ +if BOARD_GOOGLE_SNOW + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_ARMV7 + select CPU_SAMSUNG_EXYNOS5 + select HAVE_UART_MEMORY_MAPPED + select CONSOLE_SERIAL_NONSTANDARD_MEM # enable serial debugging +# select EC_GOOGLE_CHROMEEC + select BOARD_ROMSIZE_KB_4096 + select DRIVER_MAXIM_77686 +# select HAVE_ACPI_TABLES +# select MMCONF_SUPPORT +# select CHROMEOS + +config MAINBOARD_DIR + string + default google/snow + +config MAINBOARD_PART_NUMBER + string + default "SNOW" + +#config MMCONF_BASE_ADDRESS +# hex +# default 0xf0000000 + +#config IRQ_SLOT_COUNT +# int +# default 18 + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "Samsung" + +# SPL (second-phase loader) stuff +config SPL_TEXT_BASE + hex "SPL executable base" + default 0x02023400 + help + Location of SPL. Default location is within iRAM region. + +#FIXME: increased "SPL" size to get around build issues +#config SPL_MAX_SIZE +# hex "SPL executable max size" +# default 0x3800 +# help +# Max size of SPL. Default is 14KB +config SPL_MAX_SIZE + hex "SPL executable max size" + default 0x8000 + help + Max size of SPL. Let's say 32KB for now... + +config DRAM_SIZE_MB + int "DRAM size (MB)" + default 2048 + +config NR_DRAM_BANKS + int "Number of DRAM banks" + default 1 + +choice + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART3 + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_NONSTANDARD_MEM + default 0x12c00000 if CONSOLE_SERIAL_UART0 + default 0x12c10000 if CONSOLE_SERIAL_UART1 + default 0x12c20000 if CONSOLE_SERIAL_UART2 + default 0x12c30000 if CONSOLE_SERIAL_UART3 + help + Map the UART names to the respective MMIO address. + +################################################################# +# stuff from smdk5250.h # +# FIXME: can we move some of these to exynos5250's Kconfig? # +################################################################# +config SYS_I2C_SPEED + int + default 100000 + +config SYS_I2C_SLAVE + hex + default 0x0 + +config I2C_MULTI_BUS + bool + default y + +#config HARD_I2C +# bool +# default y +#CMD_I2C +#I2C_EDID +#DRIVER_S3C24X0_I2C + +config VDD_ARM_MV + int + default 1300 #1.3V + +config VDD_INT_UV + int + default 1012500 # 1.0125v + +config VDD_MIF_MV + int + default 1000 # 1.0v + +config VDD_G3D_MV + int + default 1200 # 1.2v + +config VDD_LDO2_MV + int + default 1500 # 1.5v + +config VDD_LDO3_MV + int + default 1800 # 1.8v + +config VDD_LDO5_MV + int + default 1800 # 1.8v + +config VDD_LDO10_MV + int + default 1800 # 1.8v + +######### smdk5250.h ######## + +endif # BOARD_GOOGLE_SNOW diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc new file mode 100644 index 0000000..01488d0 --- /dev/null +++ b/src/mainboard/google/snow/Makefile.inc @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#romstage-y += romstage.c + +# ramstage-y += ec.c + +# FIXME: smdk5250_spl and mainboard.c are a mess. In the long +# run we'll want to replace low-level code that calls mainboard code +# with mainboard code that calls low-level code with appropriate +# parameters. Grep around for spl_get_machine_params for examples. +romstage-y += smdk5250_spl.c +ramstage-y += smdk5250_spl.c +#ramstage-y += mainboard.c + +# romstage-$(CONFIG_CHROMEOS) += chromeos.c + +# FIXME: we should do something similar to x86 platforms for Snow SPDs + +SRC_ROOT = $(src)/mainboard/google/snow diff --git a/src/mainboard/google/snow/board.h b/src/mainboard/google/snow/board.h new file mode 100644 index 0000000..bedd740 --- /dev/null +++ b/src/mainboard/google/snow/board.h @@ -0,0 +1,33 @@ +/* + * Board header file for Exynos boards + * + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SAMSUNG_BOARD_H +#define __SAMSUNG_BOARD_H + +/* Init the SPI driver */ +void spi_init(void); + +/* Init the I2C driver */ +void board_i2c_init(const void *blob); + +#endif diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb new file mode 100644 index 0000000..1d9d553 --- /dev/null +++ b/src/mainboard/google/snow/devicetree.cb @@ -0,0 +1,7 @@ +# FIXME: this is just a stub for now +chip cpu/samsung/exynos5250 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end +end diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c new file mode 100644 index 0000000..8e51b73 --- /dev/null +++ b/src/mainboard/google/snow/mainboard.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 The ChromeOS Authors + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <device/device.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + //dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM ChromeBook", + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c new file mode 100644 index 0000000..a059f2b --- /dev/null +++ b/src/mainboard/google/snow/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <system.h> +#include <cache.h> + +static void mmu_setup(void) +{ + dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); +} + +void main(unsigned long bist) +{ + mmu_setup(); +} diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c new file mode 100644 index 0000000..f3a88f3 --- /dev/null +++ b/src/mainboard/google/snow/smdk5250_spl.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/gpio.h> +#include <cpu/samsung/exynos5-common/spl.h> +#include <cpu/samsung/exynos5250/gpio.h> + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirMw", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1700, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), + .mem_manuf = MEM_MANUF_SAMSUNG, + .bad_wake_gpio = GPIO_Y10, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* TODO: Call panic() here */ + while (1) + ; + } + + return &machine_param; +} + +int board_wakeup_permitted(void) +{ + struct spl_machine_param *param = spl_get_machine_params(); + const int gpio = param->bad_wake_gpio; + int is_bad_wake; + + /* We're a bad wakeup if the gpio was defined and was high */ + is_bad_wake = ((gpio != -1) && gpio_get_value(gpio)); + + return !is_bad_wake; +}

1 0

Patch set updated for coreboot: 1f33e8f coreinfo: changes to get the USB keyboard working
by Dave Frodin 11 Dec '12

11 Dec '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1983 -gerrit commit 1f33e8f212ddc7fd76f6b661b24243af4c34a91b Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Dec 5 17:22:47 2012 -0700 coreinfo: changes to get the USB keyboard working A call to usb_initialize() was needed. Also needed to set several curses flags. One to prevent keystrokes echoing to the display, and one to allow extended keystrokes (like the KEY_F(n)) to be seen when calling getch(); Change-Id: I495b42055a54603e4efb92b2845051434d88432d Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- payloads/coreinfo/coreinfo.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 7e8b201..97538a0 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -271,6 +271,10 @@ int main(void) { int i, j; +#if defined(CONFIG_USB) + usb_initialize(); +#endif + initscr(); start_color(); @@ -292,6 +296,9 @@ int main(void) categories[i].modules[j]->init(); } + noecho(); /* don't let curses echo keyboard chars */ + keypad(stdscr, TRUE); /* allow KEY_F(n) keys to be seen */ + loop(); return 0;

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coreboot December 2012