the following patch was just integrated into master:
commit bb626346ea32479cab9801c183317a383c07196f
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Dec 7 17:26:41 2012 -0800
cbfs_core.h: support for ARMv7 CBFS master header
Change-Id: I59626200b4a92d90b46625f8dcc2ed28e6376e46
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: http://review.coreboot.org/2008
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Sat Dec 8 03:46:32 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Dec 8 06:50:01 2012, giving +2
See http://review.coreboot.org/2008 for details.
-gerrit
the following patch was just integrated into master:
commit 9fe20cb3814df88f181648860102a9da249a4da1
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Dec 7 17:18:43 2012 -0800
WIP: Initial support for Samsung Exynos 5250 ARM CPU
Samsung SoC files, including Exynos5 (a Cortex-A15
implementation). Since this is an SoC we'll forego the x86-style
{north,south}bridge and cpu distinction. We may try to split some
stuff out before the final version if prudent.
Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: http://review.coreboot.org/2005
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Sat Dec 8 03:12:31 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Dec 8 06:48:02 2012, giving +2
See http://review.coreboot.org/2005 for details.
-gerrit
the following patch was just integrated into master:
commit 747127d50545c1fbd0dcc10baacc742d3151ddfe
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Mon Dec 3 22:16:29 2012 -0700
Limit SPI device debug prints with CONFIG_DEBUG_SPI_FLASH
Fix debug printks which were not using CONFIG_DEBUG_SPI_FLASH,
which would cause long delays durring boot when SPI devices
were written.
Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/1965
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Sat Dec 8 02:57:23 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Dec 8 06:47:19 2012, giving +2
See http://review.coreboot.org/1965 for details.
-gerrit
the following patch was just integrated into master:
commit 91f1423cac0460ab79492a9c167765359b9dd3e2
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Dec 7 16:55:12 2012 -0800
Fix Yabel compilation on non-x86 platforms
Mostly preventing inb/outb being used on non-x86
Change-Id: I0434df4ce477c262337672867dc6ce398ff95279
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Sat Dec 8 02:29:52 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Dec 8 06:46:11 2012, giving +2
See http://review.coreboot.org/2002 for details.
-gerrit
the following patch was just integrated into master:
commit 4c4dd93be7fc7d7ae0d5802fe15f8e5e533a6872
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Dec 7 17:28:02 2012 -0800
Only include libgcc wrappers on x86
ARM does not need them, and they're causing trouble
Change-Id: I6c70a52c68fdcdbf211217d30c96e1c2877c7f90
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2009
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Sat Dec 8 03:40:17 2012, giving +1
Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Sat Dec 8 02:36:13 2012, giving +2
See http://review.coreboot.org/2009 for details.
-gerrit
the following patch was just integrated into master:
commit bca9b9d53e9d742d313f028f34aa4b153f7de469
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Dec 7 17:01:21 2012 -0800
Makefile cosmetics
align architectures
Change-Id: Ie3fe29d830d45e76c183411c04598e82b4b3a010
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2003
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Build-Tested: build bot (Jenkins) at Sat Dec 8 02:23:59 2012, giving +1
Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Sat Dec 8 02:54:59 2012, giving +2
See http://review.coreboot.org/2003 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2011
-gerrit
commit 2b8dde95746dc03b971717c27fa497c45316b190
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Dec 7 17:31:37 2012 -0800
WIP: Add support for non-8250 built-in UARTs
Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
---
src/console/Kconfig | 24 ++++++++++++++++++++----
src/include/uart.h | 33 +++++++++++++++++++++++++++++++++
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/src/console/Kconfig b/src/console/Kconfig
index f4e3528..117fdb8 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -1,18 +1,33 @@
menu "Console"
-# TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete.
-config CONSOLE_SERIAL8250
+config SERIAL_CONSOLE
bool "Serial port console output"
+ default y
+ help
+ Send coreboot debug output to a serial port
+
+config CONSOLE_SERIAL8250
+ bool "Serial port console output (I/O mapped, 8250-compatible)"
+ depends on SERIAL_CONSOLE
depends on HAVE_UART_IO_MAPPED
default y
help
Send coreboot debug output to an I/O mapped serial port console.
config CONSOLE_SERIAL8250MEM
- bool "Serial port console output (memory mapped)"
+ bool "Serial port console output (memory mapped, 8250-compatible)"
+ depends on SERIAL_CONSOLE
depends on HAVE_UART_MEMORY_MAPPED
help
Send coreboot debug output to a memory mapped serial port console.
+config CONSOLE_SERIAL_NONSTANDARD_MEM
+ bool "Serial port console output (memory-mapped, device-specific)"
+ depends on SERIAL_CONSOLE
+ depends on HAVE_UART_MEMORY_MAPPED
+ help
+ Send coreboot debug output to a memory mapped serial port console
+ on a device-specific UART.
+
choice
prompt "Serial port"
default CONSOLE_SERIAL_COM1
@@ -50,7 +65,7 @@ config TTYS0_BASE
choice
prompt "Baud rate"
default CONSOLE_SERIAL_115200
- depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
+ depends on SERIAL_CONSOLE
config CONSOLE_SERIAL_115200
bool "115200"
@@ -75,6 +90,7 @@ config CONSOLE_SERIAL_9600
endchoice
+#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
config TTYS0_BAUD
int
default 115200 if CONSOLE_SERIAL_115200
diff --git a/src/include/uart.h b/src/include/uart.h
new file mode 100644
index 0000000..931d6dc
--- /dev/null
+++ b/src/include/uart.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * FIXME(dhendrix): This file contains generic prototypes for UART functions.
+ * The existing headers are too specific to the 8250, so we need a better
+ * abstraction for use with non-8250 UARTs.
+ */
+
+#ifndef UART_H
+#define UART_H
+
+unsigned char uart_rx_byte(void);
+void uart_tx_byte(unsigned char data);
+void uart_tx_flush(void);
+
+void uart_init(void);
+
+#endif /* UART_H */