coreboot December 2012

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Patch merged into coreboot/master: 6bf11cf libpayload: Use usb_debug() to show USB messages
by gerrit＠coreboot.org 18 Dec '12

18 Dec '12

the following patch was just integrated into master: commit 6bf11cf50c2b682f8c09a53af774588123b250b6 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Dec 11 13:08:07 2012 -0700 libpayload: Use usb_debug() to show USB messages Previously printf()'s were used to show USB messages which results in lots of USB information being shown when it isn't needed. This will now use the usb_debug() printing funtion that already exists in usb.h. Change-Id: I2199814de3327417417eb2e26a660f4a5557cb9f Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2044 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Dec 18 19:48:15 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Dec 18 19:59:22 2012, giving +2 See http://review.coreboot.org/2044 for details. -gerrit

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New patch to review for coreboot: c1b2f2e rd890: clear IO-APIC before setup
by Aladyshev Konstantin 18 Dec '12

18 Dec '12

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2045 -gerrit commit c1b2f2e20714d1b4b45ae435ed8f722d37f0df46 Author: Kostr <aladyshev(a)nicevt.ru> Date: Tue Dec 18 22:44:01 2012 +0400 rd890: clear IO-APIC before setup Add function "clear_ioapic" before "setup_ioapic" for rd890 northbridge Change-Id: I1fd87692d8bf35c166141c9b7a6a1e748c19a636 Signed-off-by: Kostr <aladyshev(a)nicevt.ru> --- src/northbridge/amd/cimx/rd890/late.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 1a345a2..13ca09c 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -123,6 +123,7 @@ static void ioapic_init(struct device *dev) pci_write_config32(dev, 0xF8, 0x1); ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + clear_ioapic(ioapic_base); setup_ioapic(ioapic_base, 1); }

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New patch to review for coreboot: e7a60ac libpayload: Use usb_debug() to show USB messages
by Dave Frodin 18 Dec '12

18 Dec '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2044 -gerrit commit e7a60aca61f3538aa3fa9a8742c87aa091ef33b0 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Dec 11 13:08:07 2012 -0700 libpayload: Use usb_debug() to show USB messages Previously printf()'s were used to show USB messages which results in lots of USB information being shown when it isn't needed. This will now use the usb_debug() printing funtion that already exists in usb.h. Change-Id: I2199814de3327417417eb2e26a660f4a5557cb9f Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- payloads/libpayload/drivers/usb/ehci.c | 8 +++---- payloads/libpayload/drivers/usb/ehci_rh.c | 2 +- payloads/libpayload/drivers/usb/ohci.c | 6 ++--- payloads/libpayload/drivers/usb/uhci.c | 2 +- payloads/libpayload/drivers/usb/usb.c | 40 +++++++++++++++---------------- payloads/libpayload/drivers/usb/usbhid.c | 4 ++-- payloads/libpayload/drivers/usb/usbinit.c | 20 ++++++++-------- payloads/libpayload/drivers/usb/usbmsc.c | 22 ++++++++--------- payloads/libpayload/drivers/usb/xhci.c | 4 ++-- 9 files changed, 54 insertions(+), 54 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 6a1cfb5..f27658d 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -206,7 +206,7 @@ static int wait_for_tds(qtd_t *head) && timeout--) udelay(50); if (timeout < 0) { - printf("Error: ehci: queue transfer " + usb_debug("Error: ehci: queue transfer " "processing timed out.\n"); return 1; } @@ -362,7 +362,7 @@ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq (EHCI_SETUP << QTD_PID_SHIFT) | (3 << QTD_CERR_SHIFT); if (fill_td(cur, devreq, drlen) != drlen) { - printf("ERROR: couldn't send the entire device request\n"); + usb_debug("ERROR: couldn't send the entire device request\n"); } qtd_t *next = memalign(32, sizeof(qtd_t)); cur->next_qtd = virt_to_phys(next); @@ -379,7 +379,7 @@ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq (((dir == OUT)?EHCI_OUT:EHCI_IN) << QTD_PID_SHIFT) | (3 << QTD_CERR_SHIFT); if (fill_td(cur, data, dalen) != dalen) { - printf("ERROR: couldn't send the entire control payload\n"); + usb_debug("ERROR: couldn't send the entire control payload\n"); } next = memalign(32, sizeof(qtd_t)); cur->next_qtd = virt_to_phys(next); @@ -556,7 +556,7 @@ static void *ehci_create_intr_queue( } } if (nothing_placed) { - printf("Error: Failed to place ehci interrupt queue head " + usb_debug("Error: Failed to place ehci interrupt queue head " "into periodic schedule: no space left\n"); ehci_destroy_intr_queue(ep, intrq); return NULL; diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index f58e1cf..8982804 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -107,7 +107,7 @@ ehci_rh_scanport (usbdev_t *dev, int port) while ((RH_INST(dev)->ports[port] & P_PORT_RESET) && timeout--) udelay(100); if (RH_INST(dev)->ports[port] & P_PORT_RESET) { - printf("Error: ehci_rh: port reset timed out.\n"); + usb_debug("Error: ehci_rh: port reset timed out.\n"); return; } diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 7db3141..ece31e4 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -130,7 +130,7 @@ ohci_init (pcidev_t addr) * BASE ADDRESS only [31-12] bits. All other usually 0, but not all */ controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base); - printf("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf); + usb_debug("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf); if ((OHCI_INST (controller)->opreg->HcControl & HostControllerFunctionalStateMask) == USBReset) { /* cold boot */ @@ -245,7 +245,7 @@ wait_for_ed(usbdev_t *dev, ed_t *head, int pages) mdelay(1); } if (timeout < 0) - printf("Error: ohci: endpoint " + usb_debug("Error: ohci: endpoint " "descriptor processing timed out.\n"); /* Clear the done queue. */ ohci_process_done_queue(OHCI_INST(dev->controller), 1); @@ -609,7 +609,7 @@ ohci_create_intr_queue(endpoint_t *const ep, const int reqsize, } } if (nothing_placed) { - printf("Error: Failed to place ohci interrupt endpoint " + usb_debug("Error: Failed to place ohci interrupt endpoint " "descriptor into periodic table: no space left\n"); ohci_destroy_intr_queue(ep, intrq); return NULL; diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index bf611d2..b4ccb98 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -532,7 +532,7 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming } } if (nothing_placed) { - printf("Error: Failed to place UHCI interrupt queue " + usb_debug("Error: Failed to place UHCI interrupt queue " "head into framelist: no space left\n"); uhci_destroy_intr_queue(ep, q); return NULL; diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index e51adac..ff67e0c 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -286,7 +286,7 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) (device_to_host, standard_type, dev_recp), 1, 0, 0); dd = (device_descriptor_t *) dev->descriptor; - printf ("* found device (0x%04x:0x%04x, USB %x.%x)", + usb_debug ("* found device (0x%04x:0x%04x, USB %x.%x)", dd->idVendor, dd->idProduct, dd->bcdUSB >> 8, dd->bcdUSB & 0xff); dev->quirks = usb_quirk_check(dd->idVendor, dd->idProduct); @@ -294,7 +294,7 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) usb_debug ("\ndevice has %x configurations\n", dd->bNumConfigurations); if (dd->bNumConfigurations == 0) { /* device isn't usable */ - printf ("... no usable configuration!\n"); + usb_debug ("... no usable configuration!\n"); dev->address = 0; return -1; } @@ -317,7 +317,7 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) num = interfaces; } else { - printf ("\nNOTICE: This driver defaults to using the first interface.\n" + usb_debug ("\nNOTICE: This driver defaults to using the first interface.\n" "This might be the wrong choice and lead to limited functionality\n" "of the device. Please report such a case to coreboot(a)coreboot.org\n" "as you might be the first.\n"); @@ -390,16 +390,16 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) wireless_device = 0xe0, misc_device = 0xef, }; - printf(", class: "); + usb_debug(", class: "); switch (class) { case audio_device: - printf("audio\n"); + usb_debug("audio\n"); break; case comm_device: - printf("communication\n"); + usb_debug("communication\n"); break; case hid_device: - printf ("HID\n"); + usb_debug ("HID\n"); #ifdef CONFIG_USB_HID controller->devices[adr]->init = usb_hid_init; #else @@ -407,16 +407,16 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) #endif break; case physical_device: - printf("physical\n"); + usb_debug("physical\n"); break; case imaging_device: - printf("camera\n"); + usb_debug("camera\n"); break; case printer_device: - printf("printer\n"); + usb_debug("printer\n"); break; case msc_device: - printf ("MSC\n"); + usb_debug ("MSC\n"); #ifdef CONFIG_USB_MSC controller->devices[adr]->init = usb_msc_init; #else @@ -424,7 +424,7 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) #endif break; case hub_device: - printf ("hub\n"); + usb_debug ("hub\n"); #ifdef CONFIG_USB_HUB controller->devices[adr]->init = usb_hub_init; #else @@ -432,28 +432,28 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) #endif break; case cdc_device: - printf("CDC\n"); + usb_debug("CDC\n"); break; case ccid_device: - printf("smartcard / CCID\n"); + usb_debug("smartcard / CCID\n"); break; case security_device: - printf("content security\n"); + usb_debug("content security\n"); break; case video_device: - printf("video\n"); + usb_debug("video\n"); break; case healthcare_device: - printf("healthcare\n"); + usb_debug("healthcare\n"); break; case diagnostic_device: - printf("diagnostic\n"); + usb_debug("diagnostic\n"); break; case wireless_device: - printf("wireless\n"); + usb_debug("wireless\n"); break; default: - printf("unsupported class %x\n", class); + usb_debug("unsupported class %x\n", class); break; } return adr; diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index 6af2568..ee8ba63 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -407,11 +407,11 @@ static int usb_hid_set_layout (const char *country) /* Found, changing keyboard layout */ map = &keyboard_layouts[i]; - printf(" Keyboard layout '%s'\n", map->country); + usb_debug(" Keyboard layout '%s'\n", map->country); return 0; } - printf(" Keyboard layout '%s' not found, using '%s'\n", + usb_debug(" Keyboard layout '%s' not found, using '%s'\n", country, map->country); /* Nothing found, not changed */ diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index f95e9c1..2e466d3 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -67,47 +67,47 @@ static int usb_controller_initialize(int bus, int dev, int func) pci_command |= PCI_COMMAND_MASTER; pci_write_config32(addr, PCI_COMMAND, pci_command); - printf("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, + usb_debug("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, pciid >> 16, pciid & 0xFFFF, func); switch (prog_if) { case 0x00: #ifdef CONFIG_USB_UHCI - printf("UHCI controller\n"); + usb_debug("UHCI controller\n"); uhci_init (addr); #else - printf("UHCI controller (not supported)\n"); + usb_debug("UHCI controller (not supported)\n"); #endif break; case 0x10: #ifdef CONFIG_USB_OHCI - printf("OHCI controller\n"); + usb_debug("OHCI controller\n"); ohci_init(addr); #else - printf("OHCI controller (not supported)\n"); + usb_debug("OHCI controller (not supported)\n"); #endif break; case 0x20: #ifdef CONFIG_USB_EHCI - printf("EHCI controller\n"); + usb_debug("EHCI controller\n"); ehci_init(addr); #else - printf("EHCI controller (not supported)\n"); + usb_debug("EHCI controller (not supported)\n"); #endif break; case 0x30: #ifdef CONFIG_USB_XHCI - printf("xHCI controller\n"); + usb_debug("xHCI controller\n"); xhci_init(addr); #else - printf("xHCI controller (not supported)\n"); + usb_debug("xHCI controller (not supported)\n"); #endif break; default: - printf("unknown controller %x not supported\n", + usb_debug("unknown controller %x not supported\n", prog_if); break; } diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 7e8b360..0032f58 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -143,7 +143,7 @@ reset_transport (usbdev_t *dev) if (dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0) || clear_stall (MSC_INST (dev)->bulk_in) || clear_stall (MSC_INST (dev)->bulk_out)) { - printf ("Detaching unresponsive device.\n"); + usb_debug ("Detaching unresponsive device.\n"); usb_detach_device (dev->controller, dev->address); return MSC_COMMAND_DETACHED; } @@ -394,14 +394,14 @@ read_capacity (usbdev_t *dev) } if (count >= 20) { // still not successful, assume 2tb in 512byte sectors, which is just the same garbage as any other number, but probably more usable. - printf (" assuming 2 TB with 512-byte sectors as READ CAPACITY didn't answer.\n"); + usb_debug (" assuming 2 TB with 512-byte sectors as READ CAPACITY didn't answer.\n"); MSC_INST (dev)->numblocks = 0xffffffff; MSC_INST (dev)->blocksize = 512; } else { MSC_INST (dev)->numblocks = ntohl (*(u32 *) buf) + 1; MSC_INST (dev)->blocksize = ntohl (*(u32 *) (buf + 4)); } - printf (" %d %d-byte sectors (%d MB)\n", MSC_INST (dev)->numblocks, + usb_debug (" %d %d-byte sectors (%d MB)\n", MSC_INST (dev)->numblocks, MSC_INST (dev)->blocksize, /* round down high block counts to avoid integer overflow */ MSC_INST (dev)->numblocks > 1000000 @@ -433,7 +433,7 @@ usb_msc_init (usbdev_t *dev) if (interface->bInterfaceProtocol != 0x50) { - printf (" Protocol not supported.\n"); + usb_debug (" Protocol not supported.\n"); return; } @@ -441,7 +441,7 @@ usb_msc_init (usbdev_t *dev) (interface->bInterfaceSubClass != 5) && // ATAPI 8070 (interface->bInterfaceSubClass != 6)) { // SCSI /* Other protocols, such as ATAPI don't seem to be very popular. looks like ATAPI would be really easy to add, if necessary. */ - printf (" Interface SubClass not supported.\n"); + usb_debug (" Interface SubClass not supported.\n"); return; } @@ -468,11 +468,11 @@ usb_msc_init (usbdev_t *dev) } if (MSC_INST (dev)->bulk_in == 0) { - printf("couldn't find bulk-in endpoint"); + usb_debug("couldn't find bulk-in endpoint"); return; } if (MSC_INST (dev)->bulk_out == 0) { - printf("couldn't find bulk-out endpoint"); + usb_debug("couldn't find bulk-out endpoint"); return; } usb_debug (" using endpoint %x as in, %x as out\n", @@ -481,7 +481,7 @@ usb_msc_init (usbdev_t *dev) usb_debug (" has %d luns\n", get_max_luns (dev) + 1); - printf (" Waiting for device to become ready..."); + usb_debug (" Waiting for device to become ready..."); timeout = 30 * 10; /* SCSI/ATA specs say we have to wait up to 30s. Ugh */ while (timeout--) { switch (test_unit_ready (dev)) { @@ -490,7 +490,7 @@ usb_msc_init (usbdev_t *dev) case MSC_COMMAND_FAIL: mdelay (100); if (!(timeout % 10)) - printf ("."); + usb_debug ("."); continue; default: /* if it's worse return */ return; @@ -498,9 +498,9 @@ usb_msc_init (usbdev_t *dev) break; } if (timeout < 0) { - printf ("timeout. Device not ready. Still trying...\n"); + usb_debug ("timeout. Device not ready. Still trying...\n"); } else { - printf ("ok.\n"); + usb_debug ("ok.\n"); } usb_debug (" spin up"); diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 2a8bcb4..083b331 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -120,9 +120,9 @@ xhci_init (pcidev_t addr) XHCI_INST (controller)->opreg->dcbaap_lo = virt_to_phys(XHCI_INST (controller)->dcbaa); XHCI_INST (controller)->opreg->dcbaap_hi = 0; - printf("waiting for controller to be ready - "); + usb_debug("waiting for controller to be ready - "); while ((XHCI_INST (controller)->opreg->usbsts & USBSTS_CNR) != 0) mdelay(1); - printf("ok.\n"); + usb_debug("ok.\n"); usb_debug("ERST Max: %lx -> %lx entries\n", XHCI_INST (controller)->capreg->ERST_Max, 1<<(XHCI_INST (controller)->capreg->ERST_Max));

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New patch to review for coreboot: d93aea6 Supermicro H8QGI: Add onboard VGA to devicetree.cb
by Aladyshev Konstantin 18 Dec '12

18 Dec '12

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2042 -gerrit commit d93aea6b92a00c059d13f867889590acadf1537b Author: Kostr <aladyshev(a)nicevt.ru> Date: Tue Dec 18 21:52:46 2012 +0400 Supermicro H8QGI: Add onboard VGA to devicetree.cb Supermicro H8QGI have integrated Matrox G200 16MB DDR2 graphics. List it in devicetree.cb to mark it as onboard VGA to coreboot. Change-Id: Ia6b9f60e3ae705689f22babd544ad6e628a85df1 Signed-off-by: Kostr <aladyshev(a)nicevt.ru> --- src/mainboard/supermicro/h8qgi/devicetree.cb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 8ecf968..48797d5 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -111,7 +111,9 @@ chip northbridge/amd/agesa/family15/root_complex end end #drivers/i2c/w83795 end # LPC - device pci 14.4 on end # PCI 0x4384 + device pci 14.4 on + device pci 4.0 on end # onboard VGA + end # PCI 0x4384 device pci 14.5 on end # USB 3 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end # southbridge/amd/cimx/sb700

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Patch merged into coreboot/master: 8024b65 libpayload: Update configs/defconfig file
by gerrit＠coreboot.org 18 Dec '12

18 Dec '12

the following patch was just integrated into master: commit 8024b655507441646b2158fc61532364cbe65972 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Dec 17 14:40:47 2012 -0700 libpayload: Update configs/defconfig file Several settings have been added to the config without any changes to the default settings file. Change-Id: Iaf9259d77fb3c4645fc68bc0108de79c0298f0a1 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Dec 18 15:05:36 2012, giving +2 See http://review.coreboot.org/2039 for details. -gerrit

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Re: [coreboot] Asus F2A85-M progress
by David Hubbard 18 Dec '12

18 Dec '12

Hi Idwer, On Tue, Dec 18, 2012 at 4:41 AM, Idwer Vollering <vidwer(a)gmail.com> wrote: >> I got SerialICE to start up and respond to simple commands. (I haven't >> run the BIOS image in Qemu yet, but commands such as *mb work.) >> >> I selected the Asus M4A77TD_PRO board. Since SerialICE only needs to >> know how to init the chipset and superio enough to talk to the serial >> port, this is close enough. If you'd like to try SerialICE on a board >> other than mine (f2a85-m/csm) you should check src/mainboard/<your >> board>/romstage.c and start at cache_as_ram_main() >> >> For example, src/mainboard/amd/thatcher/ >> romstage.c has only a few lines before it8712f_enable_serial() gets >> called. The code in it8712f_enable_serial() is also important. >> >> I compared the coreboot code to SerialICE/mainboard/asus_m4a77td_pro.c >> chipset_init() >> >> The same i/o is done even though it is for a different chipset and >> superio, so I decided to give it a try. I made sure to have a backup >> flash chip in a safe place in case this didn't work. >> >> Here's a shell script to build SerialICE -- checks it out from svn, > > SerialICE code is in a git repo nowadays: git clone > http://review.coreboot.org/p/serialice.git > > You should read this wiki page, http://www.coreboot.org/Git and push a > changeset with git. > Replace '/coreboot' with '/serialice', in this chapter: > http://www.coreboot.org/Git#Pushing_changes Ok thanks! I think serialice.com/Installation.html is out of date. The git version should be fine. Thanks, David

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Re: [coreboot] Asus F2A85-M progress
by Idwer Vollering 18 Dec '12

18 Dec '12

2012/12/18 David Hubbard <david.c.hubbard+coreboot(a)gmail.com>: > Hi all, > > On Mon, Dec 17, 2012 at 6:40 AM, Bernhard Urban <lewurm(a)gmail.com> wrote: >> >> On Mon, Dec 17, 2012 at 2:33 PM, <darkdefende(a)gmail.com> wrote: >> > Rudolf Marek writes: >> >> Maybe it is slowly time to prepare a patch, I think I will need to write a >> >> porting guide + specific AGESA bits. >> > >> > I would be really helpful if you would write a guide. I've been trying to >> > port the asus m5a88 board to agesa but I haven't managed to get it working >> > correctly yet. >> > So a guide explaining how to port + AGESA would be great. >> >> +1 >> similar situation here with the asus m5a99x (yeah, progress is slow... :)) >> >> >> btw, great work ruik :-) >> > > Seconded! (Thirded?) I'd also be very interested to read a porting > guide even though I have the f2a85-m board. > > If I can assist with the m5a99x and m5a88 in any way, I'd be happy to. > > I got SerialICE to start up and respond to simple commands. (I haven't > run the BIOS image in Qemu yet, but commands such as *mb work.) > > I selected the Asus M4A77TD_PRO board. Since SerialICE only needs to > know how to init the chipset and superio enough to talk to the serial > port, this is close enough. If you'd like to try SerialICE on a board > other than mine (f2a85-m/csm) you should check src/mainboard/<your > board>/romstage.c and start at cache_as_ram_main() > > For example, src/mainboard/amd/thatcher/ > romstage.c has only a few lines before it8712f_enable_serial() gets > called. The code in it8712f_enable_serial() is also important. > > I compared the coreboot code to SerialICE/mainboard/asus_m4a77td_pro.c > chipset_init() > > The same i/o is done even though it is for a different chipset and > superio, so I decided to give it a try. I made sure to have a backup > flash chip in a safe place in case this didn't work. > > Here's a shell script to build SerialICE -- checks it out from svn, SerialICE code is in a git repo nowadays: git clone http://review.coreboot.org/p/serialice.git You should read this wiki page, http://www.coreboot.org/Git and push a changeset with git. Replace '/coreboot' with '/serialice', in this chapter: http://www.coreboot.org/Git#Pushing_changes > then builds serialice.rom in the current directory. The flash image is > filled with 0xff bytes because flashrom is smart enough to only write > to blocks that differ. SerialICE itself generates a flash image by > repeating the same 64K SerialICE rom from the start of the chip to the > end -- nothing wrong with that, I just wanted faster flashing by not > changing blocks unless necessary. > > You will most likely need to edit the script to change the size of the > flash image. SerialICE itself is only 64K, but for an 8MB flash I get: > sha256sum serialice.rom > cd5b283bdcc017b3f27ee4064b9ec238d8223a7b04a7e69cad2e85a158b3cd90 serialice.rom > > > ************************************************* > #!/bin/bash > # use set -e once errors handle ok > > MISSING="" > INSTALL="" > C="" > if type apt-get >/dev/null 2>&1; then > C="apt-get install" > elif type emerge >/dev/null 2>&1; then > C="emerge -av" > elif type yum >/dev/null 2>&1; then > C="yum install" > fi > export C > > add_install() > { > MISSING="$MISSING $1" > export MISSING > INSTALL="$INSTALL $2" > export INSTALL > } > > is_installed() > { > type $1 >/dev/null 2>&1 || add_install $* > } > > is_installed svn subversion > is_installed gcc gcc > if [ -n "$INSTALL" ]; then > echo "Missing tools:$MISSING" > echo " Please type: sudo $C$INSTALL" > echo " and try again" > exit 1 > fi > > if [ ! -d SerialICE ]; then > svn co svn://serialice.com/serialice/trunk/SerialICE SerialICE || exit 1 > fi > > cd SerialICE || exit 1 > > # > # copy of my .config file: Asus M4A77TD_PRO board > # note: build/config.h is tightly coupled to .config: update both at > the same time > # > cat <<EOF > .config || exit 1 > CONFIG_BOARD_ASUS_M4A77TD_PRO=y > CONFIG_BOARD_INIT="asus_m4a77td-pro.c" > CONFIG_SERIAL=y > # CONFIG_USB is not set > CONFIG_SERIAL_COM1=y > # CONFIG_SERIAL_COM2 is not set > CONFIG_SERIAL_PORT=0x3f8 > CONFIG_SERIAL_115200=y > # CONFIG_SERIAL_57600 is not set > # CONFIG_SERIAL_38400 is not set > # CONFIG_SERIAL_19200 is not set > # CONFIG_SERIAL_9600 is not set > CONFIG_SERIAL_BAUDRATE=115200 > # CONFIG_EXPERIMENTAL is not set > CONFIG_EXPERT=y > CONFIG_HAVE_SSE=y > CONFIG_BUILD_ROMCC=y > # CONFIG_BUILD_XMMSTACK is not set > EOF > > mkdir -p build || exit 1 > cat <<EOF > build/config.h || exit 1 > /* > * Automatically generated C config: don't edit > * SerialICE version: 1.5 > * Mon Dec 17 21:09:33 2012 > */ > #define AUTOCONF_INCLUDED > #define CONFIG_SERIAL_COM1 1 > #define CONFIG_BUILD_ROMCC 1 > #define CONFIG_SERIAL_115200 1 > #define CONFIG_SERIAL_PORT 0x3f8 > #define CONFIG_SERIAL_BAUDRATE 115200 > #define CONFIG_HAVE_SSE 1 > #define CONFIG_BOARD_ASUS_M4A77TD_PRO 1 > #define CONFIG_SERIAL 1 > #define CONFIG_EXPERT 1 > #define CONFIG_BOARD_INIT "asus_m4a77td-pro.c" > EOF > > # > # build serialice.rom > # > make -j5 || exit 1 > cd .. || exit 1 > > # pad serialice.rom to the size of the flash chip > S=$(( 8*1048576 )) > awk "BEGIN{for (i=0; i<$(( $S / 16 )); i++) printf > \"\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\";exit}" >> serialice.rom > dd if=SerialICE/build/serialice.rom of=serialice.rom bs=4096 > conv=notrunc # put serialice.rom at start of flash > dd if=SerialICE/build/serialice.rom of=serialice.rom bs=4096 seek=$(( > ( $S - `stat -c %s SerialICE/build/serialice.rom` )/4096 )) # and at > end of flash > echo "" > echo "Now build SerialICE QEMU Host (see SerialICE/patches/* and > serialice.com/Installation.html)" > ls --color=always -l serialice.rom > > > ************************************************* > > Regards, > David > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Asus F2A85-M progress
by David Hubbard 18 Dec '12

18 Dec '12

Hi all, On Mon, Dec 17, 2012 at 6:40 AM, Bernhard Urban <lewurm(a)gmail.com> wrote: > > On Mon, Dec 17, 2012 at 2:33 PM, <darkdefende(a)gmail.com> wrote: > > Rudolf Marek writes: > >> Maybe it is slowly time to prepare a patch, I think I will need to write a > >> porting guide + specific AGESA bits. > > > > I would be really helpful if you would write a guide. I've been trying to > > port the asus m5a88 board to agesa but I haven't managed to get it working > > correctly yet. > > So a guide explaining how to port + AGESA would be great. > > +1 > similar situation here with the asus m5a99x (yeah, progress is slow... :)) > > > btw, great work ruik :-) > Seconded! (Thirded?) I'd also be very interested to read a porting guide even though I have the f2a85-m board. If I can assist with the m5a99x and m5a88 in any way, I'd be happy to. I got SerialICE to start up and respond to simple commands. (I haven't run the BIOS image in Qemu yet, but commands such as *mb work.) I selected the Asus M4A77TD_PRO board. Since SerialICE only needs to know how to init the chipset and superio enough to talk to the serial port, this is close enough. If you'd like to try SerialICE on a board other than mine (f2a85-m/csm) you should check src/mainboard/<your board>/romstage.c and start at cache_as_ram_main() For example, src/mainboard/amd/thatcher/ romstage.c has only a few lines before it8712f_enable_serial() gets called. The code in it8712f_enable_serial() is also important. I compared the coreboot code to SerialICE/mainboard/asus_m4a77td_pro.c chipset_init() The same i/o is done even though it is for a different chipset and superio, so I decided to give it a try. I made sure to have a backup flash chip in a safe place in case this didn't work. Here's a shell script to build SerialICE -- checks it out from svn, then builds serialice.rom in the current directory. The flash image is filled with 0xff bytes because flashrom is smart enough to only write to blocks that differ. SerialICE itself generates a flash image by repeating the same 64K SerialICE rom from the start of the chip to the end -- nothing wrong with that, I just wanted faster flashing by not changing blocks unless necessary. You will most likely need to edit the script to change the size of the flash image. SerialICE itself is only 64K, but for an 8MB flash I get: sha256sum serialice.rom cd5b283bdcc017b3f27ee4064b9ec238d8223a7b04a7e69cad2e85a158b3cd90 serialice.rom ************************************************* #!/bin/bash # use set -e once errors handle ok MISSING="" INSTALL="" C="" if type apt-get >/dev/null 2>&1; then C="apt-get install" elif type emerge >/dev/null 2>&1; then C="emerge -av" elif type yum >/dev/null 2>&1; then C="yum install" fi export C add_install() { MISSING="$MISSING $1" export MISSING INSTALL="$INSTALL $2" export INSTALL } is_installed() { type $1 >/dev/null 2>&1 || add_install $* } is_installed svn subversion is_installed gcc gcc if [ -n "$INSTALL" ]; then echo "Missing tools:$MISSING" echo " Please type: sudo $C$INSTALL" echo " and try again" exit 1 fi if [ ! -d SerialICE ]; then svn co svn://serialice.com/serialice/trunk/SerialICE SerialICE || exit 1 fi cd SerialICE || exit 1 # # copy of my .config file: Asus M4A77TD_PRO board # note: build/config.h is tightly coupled to .config: update both at the same time # cat <<EOF > .config || exit 1 CONFIG_BOARD_ASUS_M4A77TD_PRO=y CONFIG_BOARD_INIT="asus_m4a77td-pro.c" CONFIG_SERIAL=y # CONFIG_USB is not set CONFIG_SERIAL_COM1=y # CONFIG_SERIAL_COM2 is not set CONFIG_SERIAL_PORT=0x3f8 CONFIG_SERIAL_115200=y # CONFIG_SERIAL_57600 is not set # CONFIG_SERIAL_38400 is not set # CONFIG_SERIAL_19200 is not set # CONFIG_SERIAL_9600 is not set CONFIG_SERIAL_BAUDRATE=115200 # CONFIG_EXPERIMENTAL is not set CONFIG_EXPERT=y CONFIG_HAVE_SSE=y CONFIG_BUILD_ROMCC=y # CONFIG_BUILD_XMMSTACK is not set EOF mkdir -p build || exit 1 cat <<EOF > build/config.h || exit 1 /* * Automatically generated C config: don't edit * SerialICE version: 1.5 * Mon Dec 17 21:09:33 2012 */ #define AUTOCONF_INCLUDED #define CONFIG_SERIAL_COM1 1 #define CONFIG_BUILD_ROMCC 1 #define CONFIG_SERIAL_115200 1 #define CONFIG_SERIAL_PORT 0x3f8 #define CONFIG_SERIAL_BAUDRATE 115200 #define CONFIG_HAVE_SSE 1 #define CONFIG_BOARD_ASUS_M4A77TD_PRO 1 #define CONFIG_SERIAL 1 #define CONFIG_EXPERT 1 #define CONFIG_BOARD_INIT "asus_m4a77td-pro.c" EOF # # build serialice.rom # make -j5 || exit 1 cd .. || exit 1 # pad serialice.rom to the size of the flash chip S=$(( 8*1048576 )) awk "BEGIN{for (i=0; i<$(( $S / 16 )); i++) printf \"\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\\xff\";exit}" > serialice.rom dd if=SerialICE/build/serialice.rom of=serialice.rom bs=4096 conv=notrunc # put serialice.rom at start of flash dd if=SerialICE/build/serialice.rom of=serialice.rom bs=4096 seek=$(( ( $S - `stat -c %s SerialICE/build/serialice.rom` )/4096 )) # and at end of flash echo "" echo "Now build SerialICE QEMU Host (see SerialICE/patches/* and serialice.com/Installation.html)" ls --color=always -l serialice.rom ************************************************* Regards, David

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Patch set updated for coreboot: 80e6927 Simplify romstage.ld for armv7
by David Hendricks 18 Dec '12

18 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2041 -gerrit commit 80e6927b276da22ff7369af5141421fd8c397b59 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 17 20:41:32 2012 -0800 Simplify romstage.ld for armv7 This is still a work-in-progress, but it seems to work better than before and is less complicated... Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/romstage.ld | 58 ++++++++++------------------------------------ 1 file changed, 12 insertions(+), 46 deletions(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0a2f7f2..c723c30 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -29,7 +29,7 @@ * FIXME 2: Somehow linker didn't like CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE... */ /* MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x3800 } */ -MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 } +/*MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 }*/ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -41,56 +41,22 @@ SECTIONS { . = ROMSTAGE_BASE; - /* - .rom . : { + .romtext . : { _rom = .; - *(.rom.text); - *(.rom.data); + *(.text); + } + + .romdata . : { *(.rodata); - *(.rodata.*); - *(.rom.data.*); + *(.machine_param); + *(.data); . = ALIGN(16); _erom = .; } - */ - - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(4); - _etext = .; - } >.sram - - .rodata : { - _rodata = .; - . = ALIGN(4); - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - _erodata = .; - } >.sram - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } >.sram + .xidx . : { + //*(.*.exidx); + } __image_copy_end = .; @@ -104,7 +70,7 @@ SECTIONS *(.bss) *(.sbss) *(COMMON) - } >.sram + } _ebss = .; _end = .;

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New patch to review for coreboot: dc92352 Simplify and make corrections to romstage.ld
by David Hendricks 18 Dec '12

18 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2041 -gerrit commit dc9235245a4196d53cddaa9aaaa24cff96eb7aa1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 17 20:41:32 2012 -0800 Simplify and make corrections to romstage.ld This is still a work-in-progress, but it seems to work better than before and is less complicated... Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/romstage.ld | 58 ++++++++++------------------------------------ 1 file changed, 12 insertions(+), 46 deletions(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0a2f7f2..3603ac2 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -29,7 +29,7 @@ * FIXME 2: Somehow linker didn't like CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE... */ /* MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x3800 } */ -MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 } +/*MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 }*/ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -41,56 +41,22 @@ SECTIONS { . = ROMSTAGE_BASE; - /* - .rom . : { + .romtext . : { _rom = .; - *(.rom.text); - *(.rom.data); + *(.text); + } + + .romdata . : { *(.rodata); - *(.rodata.*); - *(.rom.data.*); + *(.machine_param); + *(.data); . = ALIGN(16); _erom = .; } - */ - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(4); - _etext = .; - } >.sram - - .rodata : { - _rodata = .; - . = ALIGN(4); - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } >.sram - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } >.sram + .xidx . : { + //*(.*.exidx); + } __image_copy_end = .; @@ -104,7 +70,7 @@ SECTIONS *(.bss) *(.sbss) *(COMMON) - } >.sram + } _ebss = .; _end = .;

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coreboot December 2012