coreboot September 2011

coreboot@coreboot.org

40 participants
224 discussions

Patch set updated for coreboot: 7f2d27b rs780: hide unused gpp ports
by Kerry Sheh 14 Sep '11

14 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/206 -gerrit commit 7f2d27b0bddf97948fff2f81fab52633e0f77709 Author: Kerry She <shekairui(a)gmail.com> Date: Tue Sep 13 18:29:27 2011 +0800 rs780: hide unused gpp ports hide unused gpp ports, test on avalue/eax-785e Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/southbridge/amd/rs780/gfx.c | 2 ++ src/southbridge/amd/rs780/pcie.c | 13 +++++++++++++ src/southbridge/amd/rs780/rs780.c | 5 ++++- src/southbridge/amd/rs780/rs780.h | 1 + 4 files changed, 20 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 9262bb9..3c06d44 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -1009,6 +1009,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3); } } else { /* step 13.b Link Training was successful */ + AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */ set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1); reg32 = nbpcie_p_read_index(dev, 0x29); width = reg32 & 0xFF; @@ -1064,6 +1065,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind); } else { /* step 16.b Link Training was successful */ + AtiPcieCfg.PortDetect |= 1 << dev_ind; reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index 9cbd832..5e2d985 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -390,3 +390,16 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev) switching_gpp_configurations(nb_dev, sb_dev); ValidatePortEn(nb_dev); } + +/** + * Hide unused Gpp port + */ +void pcie_hide_unused_ports(device_t nb_dev) +{ + u16 hide = 0x6FC; /* skip port 0, 1, 8 */ + + hide &= ~(AtiPcieCfg.PortDetect | AtiPcieCfg.PortHp); + printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide); + set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */ + set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */ +} diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index d8f1be3..b8c7d04 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -362,7 +362,10 @@ void rs780_enable(device_t dev) if (dev->enabled) rs780_gpp_sb_init(nb_dev, dev, dev_ind); - if (dev_ind == 10) disable_pcie_bar3(nb_dev); + if (dev_ind == 10) { + disable_pcie_bar3(nb_dev); + pcie_hide_unused_ports(nb_dev); + } break; default: printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index aba3e69..5b8d251 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -213,4 +213,5 @@ u32 extractbits(u32 source, int lsb, int msb); int cpuidFamily(void); int is_family0Fh(void); int is_family10h(void); +void pcie_hide_unused_ports(device_t nb_dev); #endif /* RS780_H */

3 3

Patch merged into coreboot/master: eb9d043 rs780: hide unused gfx ports and gpp ports
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit eb9d043e335aac286fd564ae01afca35d4cc9712 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Sep 14 10:04:19 2011 +0800 rs780: hide unused gfx ports and gpp ports Hide the unused gfx ports and gpp ports if they are not configured as hotplug. lspci -vvv will get more accurate information under Linux, tested on avalue/eax-785e. Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/206 for details. -gerrit

1 0

Patch merged into coreboot/master: 7dfe549 Provide mechanism to local additions to the build
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit 7dfe5496ff3d9acf8283a64bca1bc982f3ccd7ce Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Sep 2 09:57:01 2011 +0200 Provide mechanism to local additions to the build site-local/ is an optional directory for local additions to the build. If site-local/Makefile.inc exists it will be parsed and used. Use it to define VGA option roms, splash screens, extra rules to the tree... Change-Id: I0c6ee43ffa40e6c3f193db081ab551ab75bc7478 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/212 for details. -gerrit

1 0

Patch merged into coreboot/master: e62854c superiotool: Don't compile with -Werror
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit e62854c3fad7f47dee91a2119f46bece5a7f6cb4 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Wed Mar 9 11:37:16 2011 +0100 superiotool: Don't compile with -Werror Older libpci version have headers using 'long long' which isn't allowed in ANSI C. Since we cannot control the libpci version installed in the system nor in generall have complete control over system headers, simply skip using -Werror in our makefile. Change-Id: Ibc1e57bef033bf4971f4108d078222dcf168d5e3 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> See http://review.coreboot.org/210 for details. -gerrit

1 0

Patch merged into coreboot/master: 6c800a2 inteltool: fixed 64 bit build
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit 6c800a257772c52df37e0babf8637ce0de394a42 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Mon Jun 27 14:35:00 2011 +0200 inteltool: fixed 64 bit build The inline assembly for cpuid() was 32 bit specific. Additionally a format string referencing a size_t argument wasn't using the %z length modifier. Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> See http://review.coreboot.org/211 for details. -gerrit

1 0

Patch merged into coreboot/master: c1c064a inteltool: Fixed building of position independent executables
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit c1c064a15d20f3591784ab91d80f8d7789cb3096 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Wed Mar 9 11:30:55 2011 +0100 inteltool: Fixed building of position independent executables When building a position independent executable (PIE) EBX is used internally by the compiler to generate position independent address references so it cannot be used in the clobber list. Use the already existing code for the Darwin plattform for that case, too -- it'll preserve the EBX value. Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> See http://review.coreboot.org/209 for details. -gerrit

1 0

Patch merged into coreboot/master: 5c492e1 libpayload: Add get_option_from()
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit 5c492e1e4da04d8f348f92c40b8285d6420f5043 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 12 11:40:29 2011 +0200 libpayload: Add get_option_from() This function allows reading the nvram configuration table from locations other than the cbtable. Change-Id: I56c9973a9ea45ad7bf0185b70d11c9ce5d0e0e1b Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/213 for details. -gerrit

1 0

Patch merged into coreboot/master: 9b79a7d Add IT8721F support
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit 9b79a7d880b17acc91010f94dc6cea0a230f1e9a Author: QingPei Wang <wangqingpei(a)gmail.com> Date: Tue Sep 13 13:35:43 2011 +0800 Add IT8721F support only the serial port is tested, keyboard/mouse are gonna to be tested later, it may also need some more patches to make it work completely. Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f Signed-off-by: QingPei Wang <wangqingpei(a)gmail.com> See http://review.coreboot.org/204 for details. -gerrit

1 0

Patch set updated for coreboot: c7b3404 sb800: hide unused gpp ports
by Kerry Sheh 14 Sep '11

14 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/207 -gerrit commit c7b34042bcb2080ed22f8f258045940e02c4ab5f Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Sep 14 10:19:46 2011 +0800 sb800: hide unused gpp ports add a configure option SB_GPP_UNHIDE_PORTS to hide the unused gpp ports, if certain gpp port is not configured as hotplug and no device on the port, the port will be hidden. hidden unused ports make lspci -vvv get more accurate information under Linux, test on avalue/eax-785e. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/advansus/a785e-i/platform_cfg.h | 6 ++++++ src/mainboard/amd/inagua/platform_cfg.h | 6 ++++++ src/mainboard/amd/persimmon/platform_cfg.h | 6 ++++++ src/mainboard/asrock/e350m1/platform_cfg.h | 6 ++++++ src/southbridge/amd/cimx/sb800/cfg.c | 2 +- 5 files changed, 25 insertions(+), 1 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index ee68386..5fd49d6 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -211,6 +211,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index d37c7e6..ed761c4 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -211,6 +211,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index c6d2bd5..5c88719 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -211,6 +211,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 3267651..201d107 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -211,6 +211,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 45a460b..3245449 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -110,7 +110,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; - sb_config->GppUnhidePorts = TRUE; //visable always, even port empty + sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS; sb_config->NbSbGen2 = NB_SB_GEN2; sb_config->GppGen2 = SB_GPP_GEN2;

1 0

Patch set updated for coreboot: eb9d043 rs780: hide unused gfx ports and gpp ports
by Kerry Sheh 14 Sep '11

14 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/206 -gerrit commit eb9d043e335aac286fd564ae01afca35d4cc9712 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Sep 14 10:04:19 2011 +0800 rs780: hide unused gfx ports and gpp ports Hide the unused gfx ports and gpp ports if they are not configured as hotplug. lspci -vvv will get more accurate information under Linux, tested on avalue/eax-785e. Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/rs780/gfx.c | 2 ++ src/southbridge/amd/rs780/pcie.c | 13 +++++++++++++ src/southbridge/amd/rs780/rs780.c | 5 ++++- src/southbridge/amd/rs780/rs780.h | 1 + 4 files changed, 20 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 9262bb9..3c06d44 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -1009,6 +1009,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3); } } else { /* step 13.b Link Training was successful */ + AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */ set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1); reg32 = nbpcie_p_read_index(dev, 0x29); width = reg32 & 0xFF; @@ -1064,6 +1065,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind); } else { /* step 16.b Link Training was successful */ + AtiPcieCfg.PortDetect |= 1 << dev_ind; reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index 9cbd832..5e2d985 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -390,3 +390,16 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev) switching_gpp_configurations(nb_dev, sb_dev); ValidatePortEn(nb_dev); } + +/** + * Hide unused Gpp port + */ +void pcie_hide_unused_ports(device_t nb_dev) +{ + u16 hide = 0x6FC; /* skip port 0, 1, 8 */ + + hide &= ~(AtiPcieCfg.PortDetect | AtiPcieCfg.PortHp); + printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide); + set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */ + set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */ +} diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index d8f1be3..b8c7d04 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -362,7 +362,10 @@ void rs780_enable(device_t dev) if (dev->enabled) rs780_gpp_sb_init(nb_dev, dev, dev_ind); - if (dev_ind == 10) disable_pcie_bar3(nb_dev); + if (dev_ind == 10) { + disable_pcie_bar3(nb_dev); + pcie_hide_unused_ports(nb_dev); + } break; default: printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index aba3e69..5b8d251 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -213,4 +213,5 @@ u32 extractbits(u32 source, int lsb, int msb); int cpuidFamily(void); int is_family0Fh(void); int is_family10h(void); +void pcie_hide_unused_ports(device_t nb_dev); #endif /* RS780_H */

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
23
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot September 2011