coreboot September 2011

coreboot@coreboot.org

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New patch to review for coreboot: 5c492e1 libpayload: Add get_option_from()
by Patrick Georgi 13 Sep '11

13 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/213 -gerrit commit 5c492e1e4da04d8f348f92c40b8285d6420f5043 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 12 11:40:29 2011 +0200 libpayload: Add get_option_from() This function allows reading the nvram configuration table from locations other than the cbtable. Change-Id: I56c9973a9ea45ad7bf0185b70d11c9ce5d0e0e1b Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/options.c | 9 +++++++-- payloads/libpayload/include/libpayload.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 1c692f4..fdb4be3 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -93,9 +93,8 @@ static int get_cmos_value(u32 bitnum, u32 len, void *valptr) return 0; } -int get_option(void *dest, char *name) +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) { - struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); struct cb_cmos_entries *cmos_entry; int len = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -118,3 +117,9 @@ int get_option(void *dest, char *name) printf("ERROR: No such CMOS option (%s)\n", name); return 1; } + +int get_option(void *dest, char *name) +{ + struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); + return get_option_from(option_table, dest, name); +} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 6ce7548..80eaaa4 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -194,6 +194,7 @@ void video_console_set_cursor(unsigned int cursorx, unsigned int cursory); /* drivers/option.c */ void fix_options_checksum(void); +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name); int get_option(void *dest, char *name); /**

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New patch to review for coreboot: 7dfe549 Provide mechanism to local additions to the build
by Patrick Georgi 13 Sep '11

13 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/212 -gerrit commit 7dfe5496ff3d9acf8283a64bca1bc982f3ccd7ce Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Sep 2 09:57:01 2011 +0200 Provide mechanism to local additions to the build site-local/ is an optional directory for local additions to the build. If site-local/Makefile.inc exists it will be parsed and used. Use it to define VGA option roms, splash screens, extra rules to the tree... Change-Id: I0c6ee43ffa40e6c3f193db081ab551ab75bc7478 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- Makefile.inc | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 167ab5b..4c87bd2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -45,6 +45,8 @@ subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-$(CONFIG_ARCH_X86) += src/pc80 +subdirs-y += site-local + ####################################################################### # Add source classes and their build options classes-y := ramstage romstage driver smm

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New patch to review for coreboot: 6c800a2 inteltool: fixed 64 bit build
by Patrick Georgi 13 Sep '11

13 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/211 -gerrit commit 6c800a257772c52df37e0babf8637ce0de394a42 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Mon Jun 27 14:35:00 2011 +0200 inteltool: fixed 64 bit build The inline assembly for cpuid() was 32 bit specific. Additionally a format string referencing a size_t argument wasn't using the %z length modifier. Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- util/inteltool/cpu.c | 12 +++++++++--- util/inteltool/inteltool.c | 2 +- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 9037d5d..20748bd 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -26,6 +26,12 @@ #include "inteltool.h" +#ifdef __x86_64__ +# define BREG "%%rbx" +#else +# define BREG "%%ebx" +#endif + int fd_msr; unsigned int cpuid(unsigned int op) @@ -34,9 +40,9 @@ unsigned int cpuid(unsigned int op) #if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__) asm volatile ( - "pushl %%ebx\n" - "cpuid\n" - "popl %%ebx\n" + "push " BREG "\n\t" + "cpuid\n\t" + "pop " BREG "\n\t" : "=a" (ret) : "a" (op) : "%ecx", "%edx" ); #else diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 93169d3..6fab118 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -95,7 +95,7 @@ void *map_physical(uint64_t phys_addr, size_t len) fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len); + printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len); return NULL; }

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New patch to review for coreboot: e62854c superiotool: Don't compile with -Werror
by Patrick Georgi 13 Sep '11

13 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/210 -gerrit commit e62854c3fad7f47dee91a2119f46bece5a7f6cb4 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Wed Mar 9 11:37:16 2011 +0100 superiotool: Don't compile with -Werror Older libpci version have headers using 'long long' which isn't allowed in ANSI C. Since we cannot control the libpci version installed in the system nor in generall have complete control over system headers, simply skip using -Werror in our makefile. Change-Id: Ibc1e57bef033bf4971f4108d078222dcf168d5e3 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- util/superiotool/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 38a4127..6f3cfa3 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -29,7 +29,7 @@ PREFIX = /usr/local SVNDEF := -D'SUPERIOTOOL_VERSION="$(shell svnversion -cn . \ | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' -CFLAGS += -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ +CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) LDFLAGS += -lz

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New patch to review for coreboot: c1c064a inteltool: Fixed building of position independent executables
by Patrick Georgi 13 Sep '11

13 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/209 -gerrit commit c1c064a15d20f3591784ab91d80f8d7789cb3096 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Wed Mar 9 11:30:55 2011 +0100 inteltool: Fixed building of position independent executables When building a position independent executable (PIE) EBX is used internally by the compiler to generate position independent address references so it cannot be used in the clobber list. Use the already existing code for the Darwin plattform for that case, too -- it'll preserve the EBX value. Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- util/inteltool/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index e79380a..9037d5d 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -32,7 +32,7 @@ unsigned int cpuid(unsigned int op) { uint32_t ret; -#if defined(__DARWIN__) && !defined(__LP64__) +#if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__) asm volatile ( "pushl %%ebx\n" "cpuid\n"

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Patch set updated for coreboot: 8522fe8 Add AMD Family 10h PH-EO support
by QingPei Wang 13 Sep '11

13 Sep '11

QingPei Wang (wangqingpei(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/202 -gerrit commit 8522fe8eff497bb7bd3fe125664a9d4f36227bf3 Author: QingPei Wang <wangqingpei(a)gmail.com> Date: Tue Sep 13 16:12:18 2011 +0800 Add AMD Family 10h PH-EO support the patch file comes from src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE /F10MicrocodePatch010000bf.c Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802 Signed-off-by: QingPei Wang <wangqingpei(a)gmail.com> --- src/cpu/amd/model_10xxx/model_10xxx_init.c | 1 + src/cpu/amd/model_10xxx/update_microcode.c | 2 ++ src/northbridge/amd/amdfam10/raminit_amdmct.c | 3 +++ src/northbridge/amd/amdmct/amddefs.h | 3 ++- 4 files changed, 8 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index 2e8bbfe..cf11135 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -157,6 +157,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */ { 0, 0 }, }; diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index fa3b4f8..a9faafa 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -51,6 +51,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100F62h (DA-C2) 1062h 0100009Fh * 00100F63h (DA-C3) 1043h 010000b6h * 00100F81h (HY-D1) 1081h 010000c4h + * 00100FA0h (PH-E0) 10A0h 010000bfh */ #include CONFIG_AMD_UCODE_PATCH_FILE @@ -78,6 +79,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) { 0x100f62, 0x1062, 0x100f63, 0x1043, 0x100f81, 0x1081, + 0x100fa0, 0x10A0, }; u32 new_id; diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 0c01cf1..4ac6c76 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -211,6 +211,9 @@ u32 mctGetLogicalCPUID(u32 Node) case 0x10081: ret = AMD_HY_D1; break; + case 0x100A0: + ret = AMD_PH_E0; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 7852668..d2bef38 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -46,6 +46,7 @@ #define AMD_RB_C3 0x08000000 /* ??? C3 */ #define AMD_DA_C3 0x10000000 /* XXXX C3 */ #define AMD_HY_D1 0x20000000 /* Istanbul D1 */ +#define AMD_PH_E0 0x40000000 /* Phenom II X4 X6 */ /* * Groups - Create as many as you wish, from the above public values @@ -64,7 +65,7 @@ #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) #define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)

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Patch set updated for coreboot: 93adaaa Add AMD Family 10h PH-EO support
by QingPei Wang 13 Sep '11

13 Sep '11

QingPei Wang (wangqingpei(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/202 -gerrit commit 93adaaa7c6041797f72eb3532fd500a1f13262ec Author: QingPei Wang <wangqingpei(a)gmail.com> Date: Tue Sep 13 13:58:23 2011 +0800 Add AMD Family 10h PH-EO support the patch file comes from src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE /F10MicrocodePatch010000bf.c Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802 Signed-off-by: QingPei Wang <wangqingpei(a)gmail.com> --- src/cpu/amd/model_10xxx/mc_patch_010000bf.h | 169 +++++++++++++++++++++++++ src/cpu/amd/model_10xxx/model_10xxx_init.c | 1 + src/cpu/amd/model_10xxx/update_microcode.c | 2 + src/northbridge/amd/amdfam10/raminit_amdmct.c | 3 + src/northbridge/amd/amdmct/amddefs.h | 3 +- 5 files changed, 177 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h new file mode 100644 index 0000000..6bb1308 --- /dev/null +++ b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h @@ -0,0 +1,169 @@ +/* + ============================================================ + Copyright (c) Advanced Micro Devices, Inc., 2004-2008 + Copyright QingPei Wang <wangqingpei(a)gmail.com> + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +/* + * this file comes from src/vendorcode/amd/agesa/f12 + * /Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c + */ + +0x10, 0x20, 0x17, 0x02, 0xbf, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x42, 0x82, 0x02, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xa0, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x74, 0x0f, 0x00, 0x00, +0xbe, 0x01, 0x00, 0x00, 0x33, 0x0e, 0x00, 0x00, 0xa9, 0x01, 0x00, 0x00, +0x75, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xa0, 0xfd, 0xff, 0x28, 0xc3, 0x3f, 0xc0, 0xcf, +0xff, 0x07, 0xe2, 0x01, 0x0f, 0xde, 0x50, 0xfe, 0xf2, 0xdf, 0xff, 0x0f, +0x3b, 0xfc, 0x01, 0xc5, 0x40, 0x03, 0xd4, 0x00, 0x80, 0xff, 0xfe, 0x7f, +0xfe, 0xe1, 0x1b, 0xc8, 0x5b, 0xf6, 0xff, 0xff, 0x7b, 0x87, 0x5f, 0xad, +0x6b, 0xf9, 0x6f, 0xfe, 0xfa, 0x1f, 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0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index 2e8bbfe..cf11135 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -157,6 +157,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */ { 0, 0 }, }; diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index fa3b4f8..a9faafa 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -51,6 +51,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100F62h (DA-C2) 1062h 0100009Fh * 00100F63h (DA-C3) 1043h 010000b6h * 00100F81h (HY-D1) 1081h 010000c4h + * 00100FA0h (PH-E0) 10A0h 010000bfh */ #include CONFIG_AMD_UCODE_PATCH_FILE @@ -78,6 +79,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) { 0x100f62, 0x1062, 0x100f63, 0x1043, 0x100f81, 0x1081, + 0x100fa0, 0x10A0, }; u32 new_id; diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 0c01cf1..88bbfab 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -211,6 +211,9 @@ u32 mctGetLogicalCPUID(u32 Node) case 0x10081: ret = AMD_HY_D1; break; + case 0x100A0: + ret = AMD_PH_EO; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 7852668..d302085 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -46,6 +46,7 @@ #define AMD_RB_C3 0x08000000 /* ??? C3 */ #define AMD_DA_C3 0x10000000 /* XXXX C3 */ #define AMD_HY_D1 0x20000000 /* Istanbul D1 */ +#define AMD_PH_E0 0x40000000 /* Phenom II X4 X6 */ /* * Groups - Create as many as you wish, from the above public values @@ -64,7 +65,7 @@ #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) #define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)

1 0

Patch set updated for coreboot: 5d309cb Add IT8721F support
by QingPei Wang 13 Sep '11

13 Sep '11

QingPei Wang (wangqingpei(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/204 -gerrit commit 5d309cb75821600495e77769b225b89476de8493 Author: QingPei Wang <wangqingpei(a)gmail.com> Date: Tue Sep 13 13:35:43 2011 +0800 Add IT8721F support only the serial port is tested, keyboard/mouse are gonna to be tested later, it may also need some more patches to make it work completely. Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f Signed-off-by: QingPei Wang <wangqingpei(a)gmail.com> --- src/superio/ite/Kconfig | 2 + src/superio/ite/Makefile.inc | 1 + src/superio/ite/it8721f/Makefile.inc | 22 ++++++++ src/superio/ite/it8721f/chip.h | 34 ++++++++++++ src/superio/ite/it8721f/early_serial.c | 93 ++++++++++++++++++++++++++++++++ src/superio/ite/it8721f/it8721f.h | 41 ++++++++++++++ src/superio/ite/it8721f/superio.c | 78 ++++++++++++++++++++++++++ 7 files changed, 271 insertions(+), 0 deletions(-) diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index cb0c571..d045bf4 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -36,3 +36,5 @@ config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL default n config SUPERIO_ITE_IT8718F bool +config SUPERIO_ITE_IT8721F + bool diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 21f7707..1e734fe 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -24,3 +24,4 @@ subdirs-y += it8705f subdirs-y += it8712f subdirs-y += it8716f subdirs-y += it8718f +subdirs-y += it8721f diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc new file mode 100644 index 0000000..3908237 --- /dev/null +++ b/src/superio/ite/it8721f/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c + diff --git a/src/superio/ite/it8721f/chip.h b/src/superio/ite/it8721f/chip.h new file mode 100644 index 0000000..3717d19 --- /dev/null +++ b/src/superio/ite/it8721f/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8721F_CHIP_H +#define SUPERIO_ITE_IT8721F_CHIP_H + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +extern struct chip_operations superio_ite_it8721f_ops; + +struct superio_ite_it8721f_config { + struct pc_keyboard keyboard; +}; + +#endif diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c new file mode 100644 index 0000000..cf17d0e --- /dev/null +++ b/src/superio/ite/it8721f/early_serial.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/romcc_io.h> +#include "it8721f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + +static void it8721f_sio_write(u8 ldn, u8 index, u8 value) +{ + outb(IT8721F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8721f_enter_conf(void) +{ + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void it8721f_exit_conf(void) +{ + it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CC, 0x02); +} + +/* Select 24MHz CLKIN (48MHz default). */ +void it8721f_24mhz_clkin(void) +{ + it8721f_enter_conf(); + it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CLOCKSEL, 0x1); + it8721f_exit_conf(); +} + + +/* Enable the serial port(s). */ +void it8721f_enable_serial(device_t dev, u16 iobase) +{ + /* (1) Enter the configuration state (MB PnP mode). */ + it8721f_enter_conf(); + + /* (2) Modify the data of configuration registers. */ + + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ + + /* Enable serial port(s). */ + it8721f_sio_write(IT8721F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8721f_sio_write(IT8721F_SP2, 0x30, 0x1); /* Serial port 2 */ + + /* Clear software suspend mode (clear bit 0). TODO: Needed? */ + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ + + /* (3) Exit the configuration state (MB PnP mode). */ + it8721f_exit_conf(); +} diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h new file mode 100644 index 0000000..2242a2e --- /dev/null +++ b/src/superio/ite/it8721f/it8721f.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8721F_IT8721F_H +#define SUPERIO_ITE_IT8721F_IT8721F_H + +#define IT8721F_FDC 0x00 /* Floppy */ +#define IT8721F_SP1 0x01 /* Com1 */ +#define IT8721F_SP2 0x02 /* Com2 */ +#define IT8721F_PP 0x03 /* Parallel port */ +#define IT8721F_EC 0x04 /* Environment controller */ +#define IT8721F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8721F_KBCM 0x06 /* PS/2 mouse */ +#define IT8721F_GPIO 0x07 /* GPIO */ +#define IT8721F_IR 0x0a /* Consumer IR */ + +#if defined(__PRE_RAM__) && !defined(__ROMCC__) +void it8721f_24mhz_clkin(void); +void it8721f_disable_reboot(void); +void it8721f_enable_serial(device_t dev, u16 iobase); +#endif + +#endif diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c new file mode 100644 index 0000000..846afef --- /dev/null +++ b/src/superio/ite/it8721f/superio.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "it8721f.h" + +static void init(device_t dev) +{ + struct superio_ite_it8721f_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8721F_FDC: /* TODO. */ + break; + case IT8721F_PP: /* TODO. */ + break; + case IT8721F_EC: /* TODO. */ + break; + case IT8721F_KBCK: + pc_keyboard_init(&conf->keyboard); + break; + case IT8721F_KBCM: /* TODO. */ + break; + case IT8721F_IR: /* TODO. */ + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +/* TODO: FDC, PP, EC, KBCM, IR. */ +static struct pnp_info pnp_dev_info[] = { + { &ops, IT8721F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8721F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, IT8721F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8721f_ops = { + CHIP_NAME("ITE IT8721F Super I/O") + .enable_dev = enable_dev, +};

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Re: [coreboot] I am reading the source code of coreboot, how do I understand the functions
by Patrick Georgi 13 Sep '11

13 Sep '11

Am Mo 12 Sep 2011 17:48:07 CEST schrieb Jianmin Pan: > I am used to use vim. > So, anybody have good suggestions? Install ctags, run "ctags -R src" in the toplevel directory, which creates the "tags" file. Then in vi, use ":ta identifier" to look up the declaration of identifier, ctrl-] to look up the current word (see http://ctags.sourceforge.net/ctags.html#HOW%20TO%20USE%20WITH%20VI) Patrick

2 1

Re: [coreboot] I am reading the source code of coreboot, how do I understand the functions
by Tom Sylla 12 Sep '11

12 Sep '11

If you want to browse around a bit, there is an LXR cross reference of coreboot available here: http://lxr.linux.no/coreboot Tom On Mon, Sep 12, 2011 at 8:48 AM, Jianmin Pan <dspjm1(a)gmail.com> wrote: > I am a newbie to coreboot, I am wondering is there an easy approach to > understand the functions. > For instance, when I am reading fallback_boot.c, it's very difficult for me > to understand such functions as inb(), outb(),RTC_PORT(). > The method I am using now is to grep the function name and find out which > file it is in. Then read it. However, I still feel inconvenient. > I am used to use vim. > So, anybody have good suggestions? > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot September 2011