September 2011 - coreboot - mail.coreboot.org

Patch merged into coreboot/master: 95ca382 AMD Agesa changes to fix F14 boot issues
by gerrit＠coreboot.org Sept. 15, 2011

Sept. 15, 2011

the following patch was just integrated into master: commit 95ca38286912069da0c9251972cc3665d24d8a83 Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 15:52:09 2011 -0600 AMD Agesa changes to fix F14 boot issues This collection of changes fixes a buffer addressing issue by removing one level of indirection, fixes an Agesa HT mailbox retrieval bug, and fixes a buffer location-by-signature issue. Change-Id: Ic8a8cb3f9abddd9ad59343a85dbbee5aa7633be3 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/215 for details. -gerrit

1 0

New patch to review for coreboot: f1776cd AMD SB800 early console use fix
by Frank Vibrans III Sept. 15, 2011

Sept. 15, 2011

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/216 -gerrit commit f1776cd4f022aee49fad497dc0adcc6c224d62fb Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 16:22:31 2011 -0600 AMD SB800 early console use fix This change removes printk's that occur before console init is called. In the best case, these would cause an extremely slow boot, and in the worst case would cause a complete post failure. Change-Id: I50388e71225e95db602aa45835c39126c1c920a3 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/southbridge/amd/cimx/sb800/cfg.c | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 45a460b..a7801a8 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -31,10 +31,8 @@ void sb800_cimx_config(AMDSBCFG *sb_config) { if (!sb_config) { - printk(BIOS_DEBUG, "SB800 - Cfg.c - sb800_cimx_config - No sb_config.\n"); return; } - printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - Start.\n"); //memset(sb_config, 0, sizeof(AMDSBCFG)); /* header */ @@ -128,6 +126,5 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; } #endif //!__PRE_RAM__ - printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - End.\n"); }

1 0

New patch to review for coreboot: 95ca382 AMD Agesa changes to fix F14 boot issues
by Frank Vibrans III Sept. 14, 2011

Sept. 14, 2011

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/215 -gerrit commit 95ca38286912069da0c9251972cc3665d24d8a83 Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 15:52:09 2011 -0600 AMD Agesa changes to fix F14 boot issues This collection of changes fixes a buffer addressing issue by removing one level of indirection, fixes an Agesa HT mailbox retrieval bug, and fixes a buffer location-by-signature issue. Change-Id: Ic8a8cb3f9abddd9ad59343a85dbbee5aa7633be3 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- .../f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c | 16 ++++++++-------- .../GNB/Modules/GnbPcieConfig/PcieConfigData.c | 2 +- .../f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c | 2 +- .../amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c | 4 ++-- .../agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c | 13 ++++++++++++- .../agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h | 7 ++++++- 6 files changed, 30 insertions(+), 14 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c index a1fd419..b2b96f7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c @@ -188,7 +188,7 @@ PcieAlibBuildAcpiTable ( LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); // Set PCI MMIO configuration // AmlObjName = '10DA'; - AmlObjName = Int32FromChar ('1', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '1'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); if (AmlObjPtr != NULL) { UINT64 MsrReg; @@ -205,7 +205,7 @@ PcieAlibBuildAcpiTable ( PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); if (PpFuseArray != NULL) { // AmlObjName = '30DA'; - AmlObjName = Int32FromChar ('3', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '3'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -235,7 +235,7 @@ PcieAlibBuildAcpiTable ( } } // AmlObjName = '40DA'; - AmlObjName = Int32FromChar ('4', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '4'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -244,7 +244,7 @@ PcieAlibBuildAcpiTable ( Status = AGESA_ERROR; } // AmlObjName = '50DA'; - AmlObjName = Int32FromChar ('5', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '5'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -255,7 +255,7 @@ PcieAlibBuildAcpiTable ( // Set PCIe configuration if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { // AmlObjName = '20DA'; - AmlObjName = Int32FromChar ('2', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '2'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -264,7 +264,7 @@ PcieAlibBuildAcpiTable ( Status = AGESA_ERROR; } // AmlObjName = '60DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '6'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -278,7 +278,7 @@ PcieAlibBuildAcpiTable ( Status = AGESA_ERROR; } // AmlObjName = '80DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '8'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -292,7 +292,7 @@ PcieAlibBuildAcpiTable ( Status = AGESA_ERROR; } // AmlObjName = '70DA'; - AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', '7'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c index d911847..16167d2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c @@ -153,7 +153,7 @@ PcieConfigurationInit ( IDS_ERROR_TRAP; return AGESA_FATAL; } - Pcie->ComplexList[ComplexIndex].SiliconList = (PCIe_SILICON_CONFIG *) &Buffer; + Pcie->ComplexList[ComplexIndex].SiliconList = (PCIe_SILICON_CONFIG *) Buffer; PcieFmBuildComplexConfiguration (Buffer, StdHeader); for (Index = 0; Index < NumberOfComplexes; Index++) { ComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexList, Index); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c index ef6fae7..b984194 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c @@ -120,7 +120,7 @@ PcieFmAlibBuildAcpiTable ( ); if (D18F4x15C.Field.BoostSrc != 0 || PpFuseArray->GpuBoostCap != 0) { // AmlObjName = 'B0DA'; - AmlObjName = Int32FromChar ('B', '0', 'D', 'A'); + AmlObjName = Int32FromChar ('A', 'D', '0', 'B'); AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c index baf39bd..3d4579a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: HyperTransport - * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ * */ /* @@ -128,7 +128,7 @@ CONST NORTHBRIDGE ROMDATA HtFam14Nb = (PF_MAKE_LINK_BASE)CommonReturnZero32, (PF_GET_MODULE_INFO)CommonVoid, (PF_POST_MAILBOX)CommonVoid, - (PF_RETRIEVE_MAILBOX)CommonReturnZero32, + Fam14RetrieveMailbox, (PF_GET_SOCKET)CommonReturnZero8, (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c index f6475c4..b780b0b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c @@ -10,7 +10,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: HyperTransport - * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ * */ /* @@ -126,3 +126,14 @@ Fam14GetNodeCount ( return (1); } +AP_MAIL_INFO +Fam14RetrieveMailbox ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ) +{ + AP_MAIL_INFO NodeApMailBox; + ASSERT (Nb != NULL); + NodeApMailBox.Info = 0; + return NodeApMailBox; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h index eeb84ec..533a79c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: HyperTransport - * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ * */ /* @@ -60,4 +60,9 @@ Fam14GetNodeCount ( IN NORTHBRIDGE *Nb ); +AP_MAIL_INFO +Fam14RetrieveMailbox ( + IN UINT8 Node, + IN NORTHBRIDGE *Nb + ); #endif // _HT_NB_UTILITIES_FAM14_H_

1 0

Patch merged into coreboot/master: 84d8ea5 AMD F14 Northbridge updates
by gerrit＠coreboot.org Sept. 14, 2011

Sept. 14, 2011

the following patch was just integrated into master: commit 84d8ea5c4438159f2871157ad89a80969255008d Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 13:47:17 2011 -0600 AMD F14 Northbridge updates This change is warning and whitespace fixes in the northbridge code for AMD Family 14 rev C0 cpu update. This does not address warnings in the mainboard, Agesa, Cimx, or southbridge code. Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/134 for details. -gerrit

1 0

Patch merged into coreboot/master: abade61 Update to Asrock E350m1 for AMD F14 C0
by gerrit＠coreboot.org Sept. 14, 2011

Sept. 14, 2011

the following patch was just integrated into master: commit abade616d0d2b24571588cec8766d450278a2fe8 Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 12:04:16 2011 -0600 Update to Asrock E350m1 for AMD F14 C0 This updates the E350m1 Agesa wrapper code to fix an issue with AmdLateRunApTask. It now passes the function parameter through to the Agesa routine. There is also a change to the platform_cfg.h file that makes the definition of BIOS_SIZE dependent on whether or not it was defined earlier. Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/139 for details. -gerrit

1 0

Patch set updated for coreboot: 84d8ea5 AMD F14 Northbridge updates
by Frank Vibrans III Sept. 14, 2011

Sept. 14, 2011

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/134 -gerrit commit 84d8ea5c4438159f2871157ad89a80969255008d Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 13:47:17 2011 -0600 AMD F14 Northbridge updates This change is warning and whitespace fixes in the northbridge code for AMD Family 14 rev C0 cpu update. This does not address warnings in the mainboard, Agesa, Cimx, or southbridge code. Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/northbridge/amd/agesa/Kconfig | 4 ++++ src/northbridge/amd/agesa/family12/northbridge.c | 5 +++-- src/northbridge/amd/agesa/family14/Kconfig | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 22 +++++++++++----------- src/northbridge/amd/agesa/family14/northbridge.h | 2 ++ 5 files changed, 21 insertions(+), 14 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 463da5d..3bcb0bb 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,10 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config CONSOLE_VGA_MULTI + bool + default n + source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 473e769..55109b5 100755 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -33,6 +33,7 @@ #include "chip.h" #include "northbridge.h" +#include "SbEarly.h" #include "agesawrapper.h" //#define FX_DEVS NODE_NUMS @@ -427,7 +428,7 @@ static void set_resource(device_t dev, struct resource *resource, } -#if CONFIG_CONSOLE_VGA_MULTI == 1 +#if CONFIG_CONSOLE_VGA_MULTI extern device_t vga_pri; // the primary vga device, defined in device.c #endif @@ -441,7 +442,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_CONSOLE_VGA_MULTI == 1 +#if CONFIG_CONSOLE_VGA_MULTI printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index cdc207b..44f93c1 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -37,7 +37,7 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int - default 16 + default 16 config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 80b9ca6..b2ca256 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -31,6 +31,7 @@ #include <cpu/x86/lapic.h> +#include "agesawrapper.h" #include "chip.h" #include "northbridge.h" #if CONFIG_AMD_SB_CIMX @@ -289,7 +290,6 @@ struct hw_mem_hole_info { static struct hw_mem_hole_info get_hw_mem_hole_info(void) { struct hw_mem_hole_info mem_hole; - int i; mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; @@ -420,7 +420,7 @@ static void set_resource(device_t dev, struct resource *resource, } -#if CONFIG_CONSOLE_VGA_MULTI == 1 +#if CONFIG_CONSOLE_VGA_MULTI extern device_t vga_pri; // the primary vga device, defined in device.c #endif @@ -434,7 +434,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_CONSOLE_VGA_MULTI == 1 +#if CONFIG_CONSOLE_VGA_MULTI printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -548,7 +548,7 @@ static void domain_read_resources(device_t dev) static void domain_set_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n"); - printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev); + printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n",(u32)dev); #if CONFIG_PCI_64BIT_PREF_MEM == 1 struct resource *io, *mem1, *mem2; @@ -556,7 +556,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; - int i, idx; + int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; @@ -574,9 +574,9 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); mem2 = find_resource(dev, 2|(link->link_num<<2)); printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); + (u32)(mem1->base), (u32)(mem1->limit), (u32)(mem1->size), u32)(mem1->align)); printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + (u32)(mem2->base), (u32)(mem2->limit), (u32)(mem2->size), (u32)(mem2->align)); /* See if both resources have roughly the same limits */ if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || @@ -676,7 +676,7 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); } -printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_basek, basek, limitk); +printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmio_basek, basek, limitk); /* split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -722,7 +722,7 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); - printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base); + printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n",uma_memory_base); #else high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; #endif @@ -730,8 +730,8 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas } #endif } -printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek); -printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size); +printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n",mmio_basek); +printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); #if CONFIG_GFXUMA == 1 printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); diff --git a/src/northbridge/amd/agesa/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h index fb8df38..cbb2b84 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.h +++ b/src/northbridge/amd/agesa/family14/northbridge.h @@ -23,4 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; +device_t get_node_pci(u32 nodeid, u32 fn); + #endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */

1 0

Patch set updated for coreboot: abade61 Update to Asrock E350m1 for AMD F14 C0
by Frank Vibrans III Sept. 14, 2011

Sept. 14, 2011

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/139 -gerrit commit abade616d0d2b24571588cec8766d450278a2fe8 Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 12:04:16 2011 -0600 Update to Asrock E350m1 for AMD F14 C0 This updates the E350m1 Agesa wrapper code to fix an issue with AmdLateRunApTask. It now passes the function parameter through to the Agesa routine. There is also a change to the platform_cfg.h file that makes the definition of BIOS_SIZE dependent on whether or not it was defined earlier. Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 2 +- src/mainboard/asrock/e350m1/agesawrapper.c | 70 +++++++++++++--------------- src/mainboard/asrock/e350m1/agesawrapper.h | 1 + src/mainboard/asrock/e350m1/platform_cfg.h | 32 +++++++------ 4 files changed, 52 insertions(+), 53 deletions(-) diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index de5d547e..ae67c3f 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -377,7 +377,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; } diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index e98d874..802e00e 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -437,69 +437,65 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = {0}; - AMD_LATE_PARAMS *AmdLateParams; + AMD_LATE_PARAMS AmdLateParams; - return 0; // this causes bad ACPI SSDT, need to debug + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdCreateStruct (&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate (AmdLateParams); + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; - AmdReleaseStruct (&AmdParamStruct); return (UINT32)Status; } UINT32 agesawrapper_amdlaterunaptask ( + UINT32 Func, UINT32 Data, VOID *ConfigPtr ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&AmdLateParams, + LibAmdMemFill (&ApExeParams, 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdLateRunApTask (&AmdLateParams); + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; } diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h index e45d09f..6d7d9cd 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.h +++ b/src/mainboard/asrock/e350m1/agesawrapper.h @@ -86,6 +86,7 @@ UINT32 agesawrapper_amdinitmid (void); UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdinitcpuio (void); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); #endif diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 3267651..a0cbd11 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -36,14 +36,16 @@ * bigger than 1M you have to set the ROM size outside CIMx module and * before AGESA module get call. */ -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 - #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 - #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 - #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 - #define BIOS_SIZE BIOS_SIZE_8M +#ifndef BIOS_SIZE + #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M + #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M + #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M + #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M + #endif #endif /** @@ -56,7 +58,7 @@ /** * @def SB_HPET_TIMER - * @breif + * @brief * 0 - Disable hpet * 1 - Enable hpet */ @@ -79,7 +81,7 @@ /** * @def PCI_CLOCK_CTRL - * @breif bit[0-4] used for PCI Slots Clock Control, + * @brief bit[0-4] used for PCI Slots Clock Control, * 0 - disable * 1 - enable * PCI SLOT 0 define at BIT0 @@ -92,26 +94,26 @@ /** * @def SATA_CONTROLLER - * @breif INCHIP Sata Controller + * @brief INCHIP Sata Controller */ #define SATA_CONTROLLER CIMX_OPTION_ENABLED /** * @def SATA_MODE - * @breif INCHIP Sata Controller Mode + * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_MODE NATIVE_IDE_MODE /** - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode */ #define IDE_LEGACY_MODE 0 #define IDE_NATIVE_MODE 1 /** * @def SATA_IDE_MODE - * @breif INCHIP Sata IDE Controller Mode + * @brief INCHIP Sata IDE Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #define SATA_IDE_MODE IDE_LEGACY_MODE @@ -155,7 +157,7 @@ #define AZALIA_ENABLE 2 /** - * @breif INCHIP HDA controller + * @brief INCHIP HDA controller */ #define AZALIA_CONTROLLER AZALIA_AUTO

1 0

Patch merged into coreboot/master: 8ef54d0 mainboard: add avalue/eax-785 ITX mainboard
by gerrit＠coreboot.org Sept. 14, 2011

Sept. 14, 2011

the following patch was just integrated into master: commit 8ef54d0e84cdf9959c209815f511802a9cf230e1 Author: Kerry She <shekairui(a)gmail.com> Date: Thu Sep 8 21:16:19 2011 +0800 mainboard: add avalue/eax-785 ITX mainboard It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i. Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie slot, Lan, audio, PS2 keyboard/mouse and USB are verified. Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> See http://review.coreboot.org/208 for details. -gerrit

1 0

ASUS M5A88-V support
by QingPei Wang Sept. 14, 2011

Sept. 14, 2011

hi all, after several times update, i committed three patches[1]. the board basic info is AM3+/880G/SB850. the details can be found at[2]. The latest status is it can boot opensuse 11.2 without X windows. Asus have three types of 880G/SB850, they are almost the same, so the code maybe can run under the other two motherboards[3]. A list to TODO will be updated later: 1) X windows support. 2) ITE8721F modification which including SIO_BASE problems, only serial port are test at this moment. 3) ACPI(maybe) improvement, i got a BSOD with windows XP pack 2. Any more suggestions would be welcome all of the time. [1]a) Ie9464d01 <http://review.coreboot.org/204> b) If701c8a9<http://review.coreboot.org/202>c) I9725ccdb <http://review.coreboot.org/205> [2]http://www.asus.com/Motherboards/AMD_AM3Plus/M5A88V_EVO/ [3]http://www.asus.com/Motherboards/AMD_AM3Plus/AMD_880GSB850 Best wishes QingPei Wang Phone: 86+018930528086

1 0

Re: [coreboot] Patch set updated for coreboot: b0cd5ca Add AMD Family 10h PH-EO support
by Paul Menzel Sept. 14, 2011

Sept. 14, 2011

Am Mittwoch, den 14.09.2011, 14:12 +0800 schrieb QingPei Wang: > the content of 010000bf.c comes from > > src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c > > but F10MicrocodePatch010000bf.c is used by amd agesa, could not be used > directly. i > port the code. just mentioned in the commit message that where is comes from Thank you for the explanation. Please add such elaborate explanations to the commit message. Mark Brown has a nice blog post about this [1]. Thanks, Paul [1] http://www.sirena.org.uk/log/2011/09/09/making-patches-easy-to-review/

2 1