coreboot September 2011

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Patch set updated for coreboot: 3376324 Persimmon updates for AMD F14 rev C0
by Frank Vibrans III 15 Sep '11

15 Sep '11

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/137 -gerrit commit 337632466e167e5dd89a11ca995f3bdddc09d656 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 These are the changes for the AMD Persimmon mainboard required to support the update of the AMD Family 14 cpu to rev C0. There are many warning fixes; the agesa- wrapper.c file has been changed to fix the amdinitlate and amdlaterunaptask routines, and more. Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 101 +++++++++------- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 37 ++++--- src/mainboard/amd/persimmon/Makefile.inc | 2 +- src/mainboard/amd/persimmon/OptionsIds.h | 4 +- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- src/mainboard/amd/persimmon/acpi_tables.c | 12 +- src/mainboard/amd/persimmon/agesawrapper.c | 151 +++++++++++++------------ src/mainboard/amd/persimmon/agesawrapper.h | 17 ++-- src/mainboard/amd/persimmon/buildOpts.c | 78 +++++++++----- src/mainboard/amd/persimmon/devicetree.cb | 1 - src/mainboard/amd/persimmon/dimmSpd.h | 63 ++++++++++ src/mainboard/amd/persimmon/get_bus_conf.c | 1 + src/mainboard/amd/persimmon/irq_tables.c | 3 +- src/mainboard/amd/persimmon/mainboard.c | 3 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/persimmon/platform_cfg.h | 2 + src/mainboard/amd/persimmon/romstage.c | 1 - 18 files changed, 300 insertions(+), 184 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index f4a5cb6..3fb0e87 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -16,19 +16,15 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "agesawrapper.h" #include "amdlib.h" +#include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" #include "SB800.h" -AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - UINTN i; - AGESA_STATUS CalloutStatus; - -CONST BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] = +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer @@ -58,36 +54,44 @@ CONST BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] = BiosRunFuncOnAp }, - {AGESA_HOOKBEFORE_DQS_TRAINING, - BiosHookBeforeDQSTraining + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset }, - + {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, BiosHookBeforeExitSelfRefresh }, - {AGESA_GNB_PCIE_SLOT_RESET, - BiosGnbPcieSlotReset - }, }; - for (i = 0; i < REQUIRED_CALLOUTS; i++) +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + CalloutStatus = AGESA_UNSUPPORTED; + + for (i = 0; i < CallOutCount; i++) { if (BiosCallouts[i].CalloutName == Func) { - break; + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return CalloutStatus; } } - - if(i >= REQUIRED_CALLOUTS) - { - return AGESA_UNSUPPORTED; - } - - CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); - + return CalloutStatus; } @@ -149,7 +153,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points to the end of the allocated nodes list. */ - + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -199,7 +203,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If BestFitNode is the first buffer in the list, then update StartOfFreedNodes to reflect the new free node - */ + */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; } else { @@ -284,10 +288,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) FreedNodePtr->NextNodeOffset = 0; } else { - /* Otherwise, add freed node to the start of the list + /* Otherwise, add freed node to the start of the list Update NextNodeOffset and BufferSize to include the size of BIOS_BUFFER_NODE - */ + */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } /* Update StartOfFreedNodes to the new first node */ @@ -295,7 +299,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } else { /* Traverse list of freed nodes to find where the deallocated node should be place - */ + */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { @@ -309,7 +313,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* If deallocated node is adjacent to the next node, concatenate both nodes - */ + */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); AllocNodePtr->BufferSize += NextNodePtr->BufferSize; @@ -323,7 +327,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If deallocated node is adjacent to the previous node, concatenate both nodes - */ + */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { @@ -377,7 +381,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; } @@ -387,10 +391,10 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT8 Value; UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader; - + ResetType = Data; StdHeader = ConfigPtr; - + // // Perform the RESET based upon the ResetType. In case of // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to @@ -402,17 +406,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) case WARM_RESET_WHENEVER: case COLD_RESET_WHENEVER: break; - + case WARM_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY: Value = 0x06; LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - + default: break; } - + Status = 0; return Status; } @@ -420,7 +424,7 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); return Status; } @@ -445,12 +449,12 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT8 Data8; UINT16 Data16; UINT8 TempData8; - + FcnData = Data; MemData = ConfigPtr; - + Status = AGESA_SUCCESS; - /* Get SB800 MMIO Base (AcpiMmioAddr) */ + /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); Data8 = ReadIo8(0xCD7); Data16 = Data8<<8; @@ -459,7 +463,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~BIT5; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -473,19 +477,21 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) TempData8 &= 0x23; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); Data8 &= ~BIT5; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); TempData8 &= 0x03; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + Data8 |= BIT2+BIT3; Data8 &= ~BIT4; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); TempData8 &= 0x23; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - + switch(MemData->ParameterListPtr->DDR3Voltage){ case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -514,6 +520,13 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } return Status; } + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { @@ -525,12 +538,12 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS Status; UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; - + UINT32 GpioMmioAddr; UINT32 AcpiMmioAddr; UINT8 Data8; UINT16 Data16; - + FcnData = Data; ResetInfo = ConfigPtr; // Get SB800 MMIO Base (AcpiMmioAddr) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index 2912ec6..b187fa2 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -45,7 +45,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* REQUIRED CALLOUTS * AGESA ADVANCED CALLOUTS - CPU - */ + */ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -64,6 +64,8 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index f900584..5f85688 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -108,34 +108,43 @@ config SIO_PORT default 0x4e config ONBOARD_VGA_IS_PRIMARY - bool - default y + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVbios.bin" config VGA_BIOS_ID string default "1002,9802" config AHCI_BIOS - bool - default n + bool + default n #config AHCI_BIOS_FILE -# string "AHCI ROM path and filename" -# depends on AHCI_BIOS -# default "rom/ahci/sb900.bin" +# string "AHCI ROM path and filename" +# depends on AHCI_BIOS +# default "rom/ahci/sb900.bin" config AHCI_BIOS_ID - string "AHCI device PCI IDs" - depends on AHCI_BIOS - default "1002,4391" + string "AHCI device PCI IDs" + depends on AHCI_BIOS + default "1002,4391" config DRIVERS_PS2_KEYBOARD - bool - default n + bool + default n config WARNINGS_ARE_ERRORS - bool - default n + bool + default n endif # BOARD_AMD_PERSIMMON diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index 6a19bb6..afad9ac 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -38,4 +38,4 @@ ramstage-y += PlatformGnbPcie.c ramstage-y += reset.c -subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14 +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../vendorcode/amd/agesa/f14 diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h index 5094444..028d58f 100644 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ b/src/mainboard/amd/persimmon/OptionsIds.h @@ -51,11 +51,9 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED + //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW //#define IDSOPT_HOST_SIMNOW FALSE diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 0d79077..59d31ef 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -128,7 +128,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR ASSERT(FALSE); - return Status; + return; } BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 189c104..7c5aa39 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -24,11 +24,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -//#include <cpu/amd/amdfam10_sysconf.h> - -//#include "mb_sysconf.h" #include "agesawrapper.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam14.h> #define DUMP_ACPI_TABLES 0 @@ -177,7 +175,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { - memcpy(current, srat, srat->header.length); + memcpy((void *)current, srat, srat->header.length); srat = (acpi_srat_t *) current; //acpi_create_srat(srat); current += srat->header.length; @@ -189,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { - memcpy(current, slit, slit->header.length); + memcpy((void *)current, slit, slit->header.length); slit = (acpi_slit_t *) current; //acpi_create_slit(slit); current += slit->header.length; @@ -201,7 +199,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); + memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; } diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index e98d874..74aa73d 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -21,7 +21,7 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - + #include <stdint.h> #include <string.h> #include "agesawrapper.h" @@ -36,6 +36,7 @@ #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <arch/io.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -44,6 +45,8 @@ *---------------------------------------------------------------------------------------- */ +#define MMCONF_ENABLE 1 + /* ACPI table pointers returned by AmdInitLate */ VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; @@ -52,8 +55,7 @@ VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - +VOID *AcpiAlib = NULL; /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S @@ -64,17 +66,17 @@ VOID *AcpiAlib = NULL; * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ -UINT32 +UINT32 agesawrapper_amdinitcpuio ( VOID ) @@ -122,8 +124,8 @@ agesawrapper_amdinitcpuio ( Status = AGESA_SUCCESS; return (UINT32)Status; } - -UINT32 + +UINT32 agesawrapper_amdinitmmio ( VOID ) @@ -134,21 +136,33 @@ agesawrapper_amdinitmmio ( PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; + /* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - + /* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. */ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; + MsrReg = MsrReg | 0x0000400000000000ull; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - + /* Set Ontario Link Data */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); PciData = 0x01308002; @@ -156,12 +170,12 @@ agesawrapper_amdinitmmio ( PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - + Status = AGESA_SUCCESS; return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdinitreset ( VOID ) @@ -169,13 +183,12 @@ agesawrapper_amdinitreset ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); - LibAmdMemFill (&AmdResetParams, 0, sizeof (AMD_RESET_PARAMS), @@ -191,14 +204,14 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; - + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); return (UINT32)status; - } - -UINT32 + } + +UINT32 agesawrapper_amdinitearly ( VOID ) @@ -206,7 +219,7 @@ agesawrapper_amdinitearly ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -219,10 +232,10 @@ agesawrapper_amdinitearly ( AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); - + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; OemCustomizeInitEarly (AmdEarlyParamsPtr); - + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); @@ -230,7 +243,7 @@ agesawrapper_amdinitearly ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitpost ( VOID ) @@ -257,6 +270,7 @@ agesawrapper_amdinitpost ( status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; @@ -272,7 +286,7 @@ agesawrapper_amdinitpost ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitenv ( VOID ) @@ -349,7 +363,6 @@ agesawrapper_amdinitenv ( PciValue |= 0x80000000; LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize MMIO Base and Limit Address * Modify B0D1F0x20 */ @@ -399,17 +412,17 @@ agesawrapper_getlateinitptr ( } } -UINT32 +UINT32 agesawrapper_amdinitmid ( VOID ) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - + /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - + LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -431,79 +444,75 @@ agesawrapper_amdinitmid ( return (UINT32)status; } -UINT32 +UINT32 agesawrapper_amdinitlate ( VOID ) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = {0}; - AMD_LATE_PARAMS *AmdLateParams; + AMD_LATE_PARAMS AmdLateParams; - return 0; // this causes bad ACPI SSDT, need to debug + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdCreateStruct (&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate (AmdLateParams); + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; - AmdReleaseStruct (&AmdParamStruct); return (UINT32)Status; } UINT32 agesawrapper_amdlaterunaptask ( + UINT32 Func, UINT32 Data, VOID *ConfigPtr ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&AmdLateParams, + LibAmdMemFill (&ApExeParams, 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdLateRunApTask (&AmdLateParams); + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdreadeventlog ( VOID ) @@ -522,9 +531,9 @@ agesawrapper_amdreadeventlog ( AmdEventParams.StdHeader.ImageBasePtr = 0; Status = AmdReadEventLog (&AmdEventParams); while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); Status = AmdReadEventLog (&AmdEventParams); } diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index e45d09f..f8d924e 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -21,8 +21,7 @@ * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ - - + #ifndef _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_ @@ -39,7 +38,6 @@ #define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ @@ -50,8 +48,6 @@ enum { PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ }; - - /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- @@ -66,26 +62,29 @@ typedef struct { * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + /*--------------------------------------------------------------------------------------- * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ - + UINT32 agesawrapper_amdinitreset (void); UINT32 agesawrapper_amdinitearly (void); UINT32 agesawrapper_amdinitenv (void); UINT32 agesawrapper_amdinitlate (void); UINT32 agesawrapper_amdinitpost (void); UINT32 agesawrapper_amdinitmid (void); + UINT32 agesawrapper_amdreadeventlog (void); -UINT32 agesawrapper_amdinitmmio (void); + UINT32 agesawrapper_amdinitcpuio (void); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index cde9df7..c6dc43d 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -33,8 +33,6 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -125,29 +123,6 @@ #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -/* - * Agesa configuration values selection. - * Uncomment and specify the value for the configuration options - * needed by the system. - */ - -/* The fixed MTRR values to be set after memory initialization. */ -CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E }, - { CPU_LIST_TERMINAL } -}; - #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -244,7 +219,33 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +/* + * Agesa configuration values selection. + * Uncomment and specify the value for the configuration options + * needed by the system. + */ +#include "AGESA.h" +#include "CommonReturns.h" + +/* The fixed MTRR values to be set after memory initialization. */ +CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull }, + { CPU_LIST_TERMINAL } +}; + /* Include the files that instantiate the configuration definitions. */ + #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -253,7 +254,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" @@ -277,7 +277,31 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 3cb8d1e..7da2169 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -93,7 +93,6 @@ chip northbridge/amd/agesa/family14/root_complex # end # device pci 18.0 # These seem unnecessary device pci 18.0 on end - #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/amd/persimmon/dimmSpd.h b/src/mainboard/amd/persimmon/dimmSpd.h new file mode 100755 index 0000000..069c34a --- /dev/null +++ b/src/mainboard/amd/persimmon/dimmSpd.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 355c27f..4bc5b48 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -24,6 +24,7 @@ #include <stdint.h> #include <stdlib.h> #include <cpu/amd/amdfam14.h> +#include "agesawrapper.h" #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index a8ea5aa..28432dd 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -23,8 +23,7 @@ #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> -//#include <cpu/amd/amdfam10_sysconf.h> - +#include <cpu/amd/amdfam14.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 7de76e8..135f8f4 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -28,7 +28,8 @@ //#include <southbridge/amd/sb800/sb800.h> #include "chip.h" -//#define SMBUS_IO_BASE 0x6000 +void set_pcie_reset(void); +void set_pcie_dereset(void); /** * TODO diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index a5aa79e..ec74b92 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <string.h> #include <stdint.h> +#include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> extern u8 bus_sb800[2]; @@ -61,7 +62,6 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ - device_t dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index c6d2bd5..3323624 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -36,6 +36,7 @@ * bigger than 1M you have to set the ROM size outside CIMx module and * before AGESA module get call. */ +#ifndef BIOS_SIZE #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 @@ -45,6 +46,7 @@ #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 #define BIOS_SIZE BIOS_SIZE_8M #endif +#endif /** * @def SPREAD_SPECTRUM diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 6067803..0eb7490 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -45,7 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - u8 reg8; // all cores: allow caching of flash chip code and data // (there are no cache-as-ram reliability concerns with family 14h)

1 0

Patch merged into coreboot/master: 97678d2 Build warning fix for AMD Family 12
by gerrit＠coreboot.org 15 Sep '11

15 Sep '11

the following patch was just integrated into master: commit 97678d28e7833d98b9c1e40e0d5d579b66981136 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 11:24:29 2011 -0600 Build warning fix for AMD Family 12 This trivial change adds a prototype to an existing header file to fix a build warning for the AMD family 12 cpus. Change-Id: Ic666bfbef867d17607eaa0f59570aea987a31f93 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/218 for details. -gerrit

1 0

New patch to review for coreboot: 97678d2 Build warning fix for AMD Family 12
by Frank Vibrans III 15 Sep '11

15 Sep '11

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/218 -gerrit commit 97678d28e7833d98b9c1e40e0d5d579b66981136 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 11:24:29 2011 -0600 Build warning fix for AMD Family 12 This trivial change adds a prototype to an existing header file to fix a build warning for the AMD family 12 cpus. Change-Id: Ic666bfbef867d17607eaa0f59570aea987a31f93 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/include/cpu/amd/amdfam12.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h index 6c0a5ac..cabd532 100755 --- a/src/include/cpu/amd/amdfam12.h +++ b/src/include/cpu/amd/amdfam12.h @@ -48,6 +48,7 @@ void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); #endif +void get_bus_conf(void); u32 get_initial_apicid(void); #endif /* CPU_AMD_FAM12_H */

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Patch merged into coreboot/master: 1c83d12 AMD Inagua platform updates
by gerrit＠coreboot.org 15 Sep '11

15 Sep '11

the following patch was just integrated into master: commit 1c83d12c43d8dac6136b210b9dd789551b62189c Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 10:59:55 2011 -0600 AMD Inagua platform updates These changes update the Inagua platform. The changes include modifying the Kconfig to suggest video bios and ahci rom implementations, changing the dimm spd code to use the correct bus addresses, cleaning up the makefile a bit, and fixing a duplicate definition warning associated with the BIOS_SIZE value. Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/136 for details. -gerrit

1 0

Patch set updated for coreboot: 1c83d12 AMD Inagua platform updates
by Frank Vibrans III 15 Sep '11

15 Sep '11

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/136 -gerrit commit 1c83d12c43d8dac6136b210b9dd789551b62189c Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 10:59:55 2011 -0600 AMD Inagua platform updates These changes update the Inagua platform. The changes include modifying the Kconfig to suggest video bios and ahci rom implementations, changing the dimm spd code to use the correct bus addresses, cleaning up the makefile a bit, and fixing a duplicate definition warning associated with the BIOS_SIZE value. Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/mainboard/amd/inagua/Kconfig | 43 +++++++++++++++++---- src/mainboard/amd/inagua/Makefile.inc | 4 +- src/mainboard/amd/inagua/dimmSpd.c | 14 ++---- src/mainboard/amd/inagua/dimmSpd.h | 63 +++++++++++++++++++++++++++++++ src/mainboard/amd/inagua/platform_cfg.h | 2 + 5 files changed, 106 insertions(+), 20 deletions(-) diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index b494943..80bc621 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -123,17 +123,44 @@ config SIO_PORT default 0x2e config DRIVERS_PS2_KEYBOARD - bool - default y + bool + default y config WARNINGS_ARE_ERRORS - bool - default n + bool + default n + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +#config VGA_BIOS_FILE +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVBios.bin" + +config VGA_BIOS_ID + string "VGA device PCI IDs" + depends on VGA_BIOS + default "1002,9802" + +config AHCI_ROM + bool + default n + +#config AHCI_ROM_FILE +# string "AHCI ROM path and filename" +# depends on AHCI_ROM +# default "rom/ahci/sb800.bin" -config FALLBACK_VGA_BIOS_ID - string "VGA device PCI IDs" - depends on VGA_BIOS - default "1002,9802" +config AHCI_ROM_ID + string "AHCI device PCI IDs" + depends on AHCI_ROM + default "1002,4391" endif # BOARD_AMD_INAGUA diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc index 955ed80..531a736 100755 --- a/src/mainboard/amd/inagua/Makefile.inc +++ b/src/mainboard/amd/inagua/Makefile.inc @@ -31,6 +31,4 @@ ramstage-y += PlatformGnbPcie.c ramstage-y += reset.c -AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 -subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT) -#subdirs-$(CONFIG_AMD_SB_CIMX) += ../../../vendorcode/amd/cimx +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14 \ No newline at end of file diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c index 94e63e1..d6bf5b2 100644 --- a/src/mainboard/amd/inagua/dimmSpd.c +++ b/src/mainboard/amd/inagua/dimmSpd.c @@ -30,17 +30,13 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * SPD address table - porting required */ -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm +#define SMBUS_BASE_ADDR 0xB00 +static const UINT8 spdAddressLookup [1] [2] [1] = // socket, channel, dimm { // socket 0 { - {0xA0, 0xA2}, // channel 0 dimms - {0xA4, 0xA8}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms + {0xA0}, // channel 0 dimms + {0xA2}, // channel 1 dimms }, }; @@ -160,7 +156,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; - ioBase = 0xB00; + ioBase = SMBUS_BASE_ADDR; setupFch (ioBase); return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); } diff --git a/src/mainboard/amd/inagua/dimmSpd.h b/src/mainboard/amd/inagua/dimmSpd.h new file mode 100755 index 0000000..069c34a --- /dev/null +++ b/src/mainboard/amd/inagua/dimmSpd.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index d37c7e6..4a3f080 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -36,6 +36,7 @@ * bigger than 1M you have to set the ROM size outside CIMx module and * before AGESA module get call. */ +#ifndef BIOS_SIZE #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 @@ -45,6 +46,7 @@ #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 #define BIOS_SIZE BIOS_SIZE_8M #endif +#endif /** * @def SPREAD_SPECTRUM

1 0

Patch merged into coreboot/master: 8e7e2d8 AMD Torpedo platform updates
by gerrit＠coreboot.org 15 Sep '11

15 Sep '11

the following patch was just integrated into master: commit 8e7e2d8fdfde57cf130afd98aeba9535fe8cdad8 Author: efdesign98 <efdesign98(a)gmail.com> Date: Fri Aug 19 14:25:48 2011 -0600 AMD Torpedo platform updates This update fixes warnings and supports as necessary the Agesa infrastructure changes required to support the AMD Family 14 cpu update to rev C0. Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/138 for details. -gerrit

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Patch merged into coreboot/master: af4f6db AMD Agesa macro expansion fix
by gerrit＠coreboot.org 15 Sep '11

15 Sep '11

the following patch was just integrated into master: commit af4f6db8093112637d8b067b7323f118931cccfa Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 19:34:13 2011 -0600 AMD Agesa macro expansion fix This change fixes the use of a macro that was previously modified to fix a warning. The macro was used in a manner that doubly incremented a pointer. The pointer increment was removed from the macro call and moved elsewhere. In addition, an unused macro was removed from both Family 12 and Family 14 code. Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/217 for details. -gerrit

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Patch set updated for coreboot: 8e7e2d8 AMD Torpedo platform updates
by Frank Vibrans III 15 Sep '11

15 Sep '11

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/138 -gerrit commit 8e7e2d8fdfde57cf130afd98aeba9535fe8cdad8 Author: efdesign98 <efdesign98(a)gmail.com> Date: Fri Aug 19 14:25:48 2011 -0600 AMD Torpedo platform updates This update fixes warnings and supports as necessary the Agesa infrastructure changes required to support the AMD Family 14 cpu update to rev C0. Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/mainboard/amd/torpedo/BiosCallOuts.c | 21 +++++--- src/mainboard/amd/torpedo/Kconfig | 18 ++++---- src/mainboard/amd/torpedo/Oem.h | 72 +++++++---------------------- src/mainboard/amd/torpedo/agesawrapper.h | 1 - src/mainboard/amd/torpedo/get_bus_conf.c | 1 + 5 files changed, 41 insertions(+), 72 deletions(-) diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index bd6c633..355077f 100755 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -539,25 +539,30 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_5) { - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); - Data8 |= BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - } else if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_35) { + + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= BIT6; + Data8 |= (UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } else if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_25) { + break; + case VOLT1_25: Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } else {} + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + } return Status; } diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index e4bde59..6da53a0 100755 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2010 Advanced Micro Devices, Inc. +# Copyright (C) 2011 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -122,14 +122,6 @@ config SIO_PORT hex default 0x2e -config DRIVERS_PS2_KEYBOARD - bool - default y - -config WARNINGS_ARE_ERRORS - bool - default n - config ONBOARD_VGA_IS_PRIMARY bool default y @@ -176,6 +168,14 @@ config XHC_BIOS_ID depends on XHC_BIOS default "1022,7812" +config DRIVERS_PS2_KEYBOARD + bool + default y + +config WARNINGS_ARE_ERRORS + bool + default n + config CONSOLE_POST bool depends on !NO_POST diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 50bb506..a7109dc 100755 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -1,57 +1,21 @@ -/*;******************************************************************************** -; -; Copyright 2011 ADVANCED MICRO DEVICES, INC. All Rights Reserved. -; -; AMD is granting you permission to use this software (the Materials) -; pursuant to the terms and conditions of your Software License Agreement -; with AMD. This header does *NOT* give you permission to use the Materials -; or any rights under AMD's intellectual property. Your use of any portion -; of these Materials shall constitute your acceptance of those terms and -; conditions. If you do not agree to the terms and conditions of the Software -; License Agreement, please do not use any portion of these Materials. -; -; CONFIDENTIALITY: The Materials and all other information, identified as -; confidential and provided to you by AMD shall be kept confidential in -; accordance with the terms and conditions of the Software License Agreement. -; -; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION -; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED -; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, -; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. -; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER -; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS -; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, -; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER -; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF -; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE -; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, -; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. -; -; AMD does not assume any responsibility for any errors which may appear in -; the Materials or any other related information provided to you by AMD, or -; result from use of the Materials or any related information. -; -; You agree that you will not reverse engineer or decompile the Materials. -; -; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any -; further information, software, technical information, know-how, or show-how -; available to you. Additionally, AMD retains the right to modify the -; Materials at any time, without notice, and is not obligated to provide such -; modified Materials to you. -; -; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with -; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is -; subject to the restrictions as set forth in FAR 52.227-14 and -; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the -; Government constitutes acknowledgement of AMD's proprietary rights in them. -; -; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any -; direct product thereof will be exported directly or indirectly, into any -; country prohibited by the United States Export Administration Act and the -; regulations thereunder, without the required authorization from the U.S. -; government nor will be used for any purpose prohibited by the same. -;*********************************************************************************/ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #define BIOS_SIZE 0x04 //04 - 1MB #define LEGACY_FREE 0x00 diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h index 979f743..c3209f5 100755 --- a/src/mainboard/amd/torpedo/agesawrapper.h +++ b/src/mainboard/amd/torpedo/agesawrapper.h @@ -118,7 +118,6 @@ typedef struct { *--------------------------------------------------------------------------------------- */ -//void brazos_platform_stage(void); UINT32 agesawrapper_amdinitreset (void); UINT32 agesawrapper_amdinitearly (void); UINT32 agesawrapper_amdinitenv (void); diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 436f6a8..f9b4c84 100755 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -24,6 +24,7 @@ #include <stdint.h> #include <stdlib.h> #include <cpu/amd/amdfam12.h> +#include "SbEarly.h" #include "agesawrapper.h"

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New patch to review for coreboot: af4f6db AMD Agesa macro expansion fix
by Frank Vibrans III 15 Sep '11

15 Sep '11

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/217 -gerrit commit af4f6db8093112637d8b067b7323f118931cccfa Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 19:34:13 2011 -0600 AMD Agesa macro expansion fix This change fixes the use of a macro that was previously modified to fix a warning. The macro was used in a manner that doubly incremented a pointer. The pointer increment was removed from the macro call and moved elsewhere. In addition, an unused macro was removed from both Family 12 and Family 14 code. Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- .../amd/agesa/f12/Proc/GNB/Common/GnbPcie.h | 3 --- .../amd/agesa/f14/Proc/GNB/Common/GnbPcie.h | 3 +-- .../GNB/PCIe/Family/0x14/F14PcieWrapperServices.c | 6 ++++-- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h index b29afa6..c8a4c9b 100755 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h @@ -74,9 +74,6 @@ //#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) //#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) -#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1)) -#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) - // Get lowest PHY lane on engine #define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF) // Get highest PHY lane on engine diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h index 1d80410..9941608 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h @@ -66,8 +66,7 @@ #define UNUSED_LANE_ID 128 -#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1)) -#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) +#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==0)) // Get lowest PHY lane on engine #define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF) diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c index 330a02e..3821ac7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c @@ -263,12 +263,13 @@ PcieOnConfigureGppEnginesLaneAllocation ( CoreLaneIndex = 0; PortIdIndex = 0; do { + if (PortIdIndex > 0) EnginesList++; EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++]; EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - } while (IS_LAST_DESCRIPTOR (EnginesList++)); + } while (IS_LAST_DESCRIPTOR (EnginesList)); return AGESA_SUCCESS; } @@ -305,12 +306,13 @@ PcieOnConfigureDdiEnginesLaneAllocation ( } LaneIndex = 0; do { + if (LaneIndex > 0) EnginesList++; EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - } while (IS_LAST_DESCRIPTOR (EnginesList++)); + } while (IS_LAST_DESCRIPTOR (EnginesList)); return AGESA_SUCCESS; }

1 0

Patch merged into coreboot/master: f1776cd AMD SB800 early console use fix
by gerrit＠coreboot.org 14 Sep '11

14 Sep '11

the following patch was just integrated into master: commit f1776cd4f022aee49fad497dc0adcc6c224d62fb Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Sep 14 16:22:31 2011 -0600 AMD SB800 early console use fix This change removes printk's that occur before console init is called. In the best case, these would cause an extremely slow boot, and in the worst case would cause a complete post failure. Change-Id: I50388e71225e95db602aa45835c39126c1c920a3 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/216 for details. -gerrit

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coreboot September 2011