coreboot June 2011

coreboot@coreboot.org

55 participants
274 discussions

New patch to review: cd3d80c Libpayload needs to clear the bss region.
by Marc Jones 28 Jun '11

28 Jun '11

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/66 -gerrit commit cd3d80c3e6c6c4b3de63802ddab280da3c96e975 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jun 28 14:30:05 2011 -0600 Libpayload needs to clear the bss region. Libpayload shouldn't count on coreboot or other payloads to clear memory. This fixes problems with payloads being loaded after or on top of each other. Change-Id: I30303d47e465e8921f47acab667c7998ba79fca7 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- payloads/libpayload/arch/i386/head.S | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/arch/i386/head.S b/payloads/libpayload/arch/i386/head.S index db18a51..88db412 100644 --- a/payloads/libpayload/arch/i386/head.S +++ b/payloads/libpayload/arch/i386/head.S @@ -70,10 +70,17 @@ _init: movl %esp, %esi /* Store EAX and EBX */ - movl %eax,loader_eax movl %ebx,loader_ebx + /* Clear the bss */ + cld + movl $.bss, %edi + movl $_end, %ecx + subl %edi, %ecx + xor %ax, %ax + rep stosb + /* Setup new stack. */ movl $_stack, %ebx

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Patch merged into master: 284d358 SMM: add guard and include types.h in cpu/x86/smm.h
by gerrit＠coreboot.org 28 Jun '11

28 Jun '11

the following patch was just integrated into master: commit 284d35814a8b70c7bb995e00710fe7a61cf7f9e7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jun 28 08:06:18 2011 +0200 SMM: add guard and include types.h in cpu/x86/smm.h Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/64 for details. -gerrit

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Patch merged into master: 88f214e X60: remove pci config register save/restore
by gerrit＠coreboot.org 28 Jun '11

28 Jun '11

the following patch was just integrated into master: commit 88f214ec674aa77c05742b31553b671e566ce01a Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jun 28 08:05:26 2011 +0200 X60: remove pci config register save/restore SMM code already makes sure this register is saved and restored, so we don't have to do it. Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/65 for details. -gerrit

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New patch to review: 88f214e X60: remove pci config register save/restore
by Sven Schnelle 28 Jun '11

28 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/65 -gerrit commit 88f214ec674aa77c05742b31553b671e566ce01a Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jun 28 08:05:26 2011 +0200 X60: remove pci config register save/restore SMM code already makes sure this register is saved and restored, so we don't have to do it. Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/x60/mainboard_smi.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c index fd10c9a..a0df76a 100644 --- a/src/mainboard/lenovo/x60/mainboard_smi.c +++ b/src/mainboard/lenovo/x60/mainboard_smi.c @@ -46,11 +46,10 @@ static void mainboard_smm_init(void) static void mainboard_smi_save_cmos(void) { u8 val; - u8 tmp70, tmp72, tmpcf8; + u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - tmpcf8 = inl(0xcf8); val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); set_option("tft_brightness", &val); @@ -59,7 +58,6 @@ static void mainboard_smi_save_cmos(void) outb(tmp70, 0x70); outb(tmp72, 0x72); - outb(tmpcf8, 0xcf8); } int mainboard_io_trap_handler(int smif)

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New patch to review: 284d358 SMM: add guard and include types.h in cpu/x86/smm.h
by Sven Schnelle 28 Jun '11

28 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/64 -gerrit commit 284d35814a8b70c7bb995e00710fe7a61cf7f9e7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jun 28 08:06:18 2011 +0200 SMM: add guard and include types.h in cpu/x86/smm.h Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/include/cpu/x86/smm.h | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 07a9cae..49ee2be 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -20,6 +20,11 @@ /* AMD64 SMM State-Save Area * starts @ 0x7e00 */ + +#ifndef CPU_X86_SMM_H +#define CPU_X86_SMM_H + +#include <types.h> typedef struct { u16 es_selector; u16 es_attributes; @@ -273,3 +278,5 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); void smi_release_lock(void); + +#endif

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Trac reminder: list of new ticket(s)
by coreboot tracker 27 Jun '11

27 Jun '11

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Re: [coreboot] build failure: cannot move location counter backwards
by Patrick Georgi 24 Jun '11

24 Jun '11

On Thu, 23 Jun 2011 10:18:55 -0700, Stefan Reinauer wrote: >> >Is it integrated into the payload? Reading the >> > QEMU_Build_tutorial, http://www.coreboot.org/QEMU_Build_Tutorial, >> led me >> > to try: >> > >> > $ qemu -bios build/coreboot.rom -hda /dev/zero -serial stdio >> > >> > This resulted in something else entirely, the shell output >> terminating >> > in the following: >> > >> > coreboot memory table: >> > 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES >> > 1. 0000000000001000-000000000009ffff: RAM >> > 2. 00000000000c0000-0000000017feffff: RAM >> > 3. 0000000017ff0000-0000000017ffffff: CONFIGURATION TABLES >> > 4. 00000000ff800000-00000000ffffffff: RESERVED >> > Wrote coreboot table at: 17ff1400 - 17ff15c4 checksum 6c1c >> > coreboot table: 452 bytes. >> > Multiboot Information structure has been written. >> > 0. FREE SPACE 17ff3400 0000cc00 >> > 1. GDT 17ff0200 00000200 >> > 2. IRQ TABLE 17ff0400 00001000 >> > 3. COREBOOT 17ff1400 00002000 >> > Check CBFS header at fffcfc39 >> > magic is 386f92fa >> > ERROR: No valid CBFS header found! >> > CBFS: Could not find file fallback/payload >> > Boot failed. >> >> You're now running coreboot, but coreboot was unable to find your >> payload (eg, SeaBIOS). > > However, it seems the CBFS header is corrupted, so it is not even > checking for a payload file. > > Not sure why, on first sight. ramstage was found successfully, so this might be a matter of chip mapping (or rather its emulation) Patrick

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New patch to review: d7048ee amd southbirdge sb800 wrapper, pci bridge fix
by Kerry She 24 Jun '11

24 Jun '11

Kerry She (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/63 -gerrit commit d7048ee00e4b8cfe5849c384b957aee1bb407ffc Author: Kerry She <shekairui(a)gmail.com> Date: Fri Jun 24 22:52:15 2011 +0800 amd southbirdge sb800 wrapper, pci bridge fix sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/mainboard/advansus/a785e-i/devicetree.cb | 2 +- src/mainboard/amd/inagua/devicetree.cb | 2 +- src/mainboard/amd/persimmon/devicetree.cb | 2 +- src/mainboard/asrock/e350m1/devicetree.cb | 2 +- src/southbridge/amd/cimx/sb800/late.c | 17 ++++++++++++++++- 5 files changed, 20 insertions(+), 5 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index 25a1f64..79df8c9 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -98,7 +98,7 @@ chip northbridge/amd/amdfam10/root_complex end end #superio/winbond/w83627hf end # LPC 0x439d - device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 device pci 14.6 off end # Gec device pci 15.0 on end # PCIe 0 diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 67be34e..82658cf 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -65,7 +65,7 @@ chip northbridge/amd/agesa/family14/root_complex end end # kbc1100 end #LPC - device pci 14.4 on end # PCI 0x4384 + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 device pci 15.0 on end # PCIe PortA device pci 15.1 on end # PCIe PortB diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index a676388..3cb8d1e 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -81,7 +81,7 @@ chip northbridge/amd/agesa/family14/root_complex end end # f81865f end #LPC - device pci 14.4 on end # PCI 0x4384 + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 device pci 15.0 off end # PCIe PortA device pci 15.1 off end # PCIe PortB diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index 5983ed2..bff8151 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -97,7 +97,7 @@ chip northbridge/amd/agesa/family14/root_complex end end end #LPC - device pci 14.4 on end # PCI 0x4384 + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 device pci 15.0 on end # PCIe PortA device pci 15.1 on end # PCIe PortB: NIC diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 7367a18..b16bc50 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -248,6 +248,21 @@ static const struct pci_driver gec_driver __pci_driver = { .device = PCI_DEVICE_ID_ATI_SB800_GEC, }; +/** + * @brief Enable PCI Bridge + * + * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] + * 'PCIDisable' set to 0 to enable P2P bridge. + * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins + * to function as GPIO {GPIO 35:0}. + */ +static void pci_init(device_t dev) +{ + /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, + * but actually was disabled in some platform, so I have to enabled it. + */ + RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); +} static void pcie_init(device_t dev) { @@ -258,7 +273,7 @@ static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcie_init, + .init = pci_init, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci,

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Patch set updated: ee466b8 msrtool: added support for Intel CPUs
by Anton Kochkov 24 Jun '11

24 Jun '11

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/50 -gerrit commit ee466b8073bca2f5c5146cde7c967095c2e4ed90 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Mon Jun 20 23:14:22 2011 +0400 msrtool: added support for Intel CPUs Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- util/msrtool/Makefile.in | 4 +- util/msrtool/intel_core1.c | 221 ++++++++++++++ util/msrtool/intel_core2_early.c | 236 +++++++++++++++ util/msrtool/intel_core2_later.c | 536 +++++++++++++++++++++++++++++++++ util/msrtool/intel_pentium3.c | 182 +++++++++++ util/msrtool/intel_pentium3_early.c | 257 ++++++++++++++++ util/msrtool/intel_pentium4_early.c | 569 +++++++++++++++++++++++++++++++++++ util/msrtool/intel_pentium4_later.c | 342 +++++++++++++++++++++ util/msrtool/msrtool.c | 7 + util/msrtool/msrtool.h | 28 ++ 10 files changed, 2380 insertions(+), 2 deletions(-) diff --git a/util/msrtool/Makefile.in b/util/msrtool/Makefile.in index 94ab5fa..bf9012e 100644 --- a/util/msrtool/Makefile.in +++ b/util/msrtool/Makefile.in @@ -23,10 +23,10 @@ PROGRAM = msrtool CC = @CC@ INSTALL = @INSTALL@ PREFIX = @PREFIX@ -CFLAGS = @CFLAGS@ +CFLAGS = @CFLAGS@ -fno-pic LDFLAGS = @LDFLAGS@ -TARGETS = geodegx2.o geodelx.o cs5536.o k8.o +TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o SYSTEMS = linux.o darwin.o freebsd.o OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS) diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c new file mode 100644 index 0000000..c7837c6 --- /dev/null +++ b/util/msrtool/intel_core1.c @@ -0,0 +1,221 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_core1_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0x6 == id->family)&(0xe == id->model)); +} + +const struct msrdef intel_core1_msrs[] = { + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + { BITS_EOT } + }}, + {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", { + { BITS_EOT } + }}, + {0xce, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_VCC", "", { + { BITS_EOT } + }}, + {0xe2, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_CST_CONFIG_CONTROL", "", { + { BITS_EOT } + }}, + {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", { + { BITS_EOT } + }}, + {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", { + { BITS_EOT } + }}, + {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", { + { BITS_EOT } + }}, + {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + { BITS_EOT } + }}, + {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + { BITS_EOT } + }}, + {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + { BITS_EOT } + }}, + {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x15f, MSRTYPE_RDWR, MSR2(0,0), "DTS_CAL_CTRL", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "GV_THERM", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c new file mode 100644 index 0000000..0c6e15f --- /dev/null +++ b/util/msrtool/intel_core2_early.c @@ -0,0 +1,236 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_core2_early_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0x6 == id->family)&(0xf == id->model)); +} + +const struct msrdef intel_core2_early_msrs[] = { + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + { BITS_EOT } + }}, + {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", { + { BITS_EOT } + }}, + {0xa8, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE0", "", { + { BITS_EOT } + }}, + {0xa9, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE1", "", { + { BITS_EOT } + }}, + {0xaa, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE2", "", { + { BITS_EOT } + }}, + {0xab, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE3", "", { + { BITS_EOT } + }}, + {0xac, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE4", "", { + { BITS_EOT } + }}, + {0xad, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE5", "", { + { BITS_EOT } + }}, + {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", { + { BITS_EOT } + }}, + {0xe2, MSRTYPE_RDWR, MSR2(0,0), "PMG_CST_CONFIG_CONTROL", "", { + { BITS_EOT } + }}, + {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", { + { BITS_EOT } + }}, + {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", { + { BITS_EOT } + }}, + {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", { + { BITS_EOT } + }}, + {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + { BITS_EOT } + }}, + {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0xe1, MSRTYPE_RDWR, MSR2(0,0), "SMM_CST_MISC_INFO", "", { + { BITS_EOT } + }}, + {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + { BITS_EOT } + }}, + {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_CTL", "", { + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c new file mode 100644 index 0000000..1c06c43 --- /dev/null +++ b/util/msrtool/intel_core2_later.c @@ -0,0 +1,536 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_core2_later_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0x6 == id->family)&(0x17 == id->model)); +} + +const struct msrdef intel_core2_later_msrs[] = { + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", "Model Specific Platform ID", { + { 63, 11, RESERVED }, + { 52, 3, RESERVED }, + { 49, 37, RESERVED }, + { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 7, 8, RESERVED }, + { BITS_EOT } + }}, + { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", "Processor Hard Power-On Configuration", { + { 63, 41, RESERVED }, + { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 19, 1, RESERVED }, + { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, { + { MSR1(0), "Integer ratio" }, + { MSR1(1), "Non-integer ratio" }, + { BITVAL_EOT } + }}, + { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 15, 1, RESERVED }, + { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, { + { MSR1(0), "4 GBytes Power on Reset Vector" }, + { MSR1(1), "1 Mbyte Power on Reset Vector" }, + { BITVAL_EOT } + }}, + { 13, 1, RESERVED }, + { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, { + { MSR1(0), "BINIT# Observation disabled" }, + { MSR1(1), "BINIT# Observation enabled" }, + { BITVAL_EOT } + }}, + { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, { + { MSR1(0), "Intel TXT Capable Chipset not present" }, + { MSR1(1), "Intel TXT Capable Chipset present" }, + { BITVAL_EOT } + }}, + { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, { + { MSR1(0), "MCERR# Observation disabled" }, + { MSR1(1), "MCERR# Observation enabled" }, + { BITVAL_EOT } + }}, + { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, { + { MSR1(0), "Execute BIST disabled" }, + { MSR1(1), "Execute BIST enabled" }, + { BITVAL_EOT } + }}, + { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, { + { MSR1(0), "Output Tri-state disabled" }, + { MSR1(1), "Output Tri-state enabled" }, + { BITVAL_EOT } + }}, + { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, { + { MSR1(0), "BINIT# Driver disabled" }, + { MSR1(1), "BINIT# Driver enabled" }, + { BITVAL_EOT } + }}, + { 6, 2, RESERVED }, + { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Address parity disabled" }, + { MSR1(1), "Address parity enabled" }, + { BITVAL_EOT } + }}, + { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, { + { MSR1(0), "MCERR# Driver disabled" }, + { MSR1(1), "MCERR# Driver enabled" }, + { BITVAL_EOT } + }}, + { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Response Error Checking disabled" }, + { MSR1(1), "Response Error Checking enabled" }, + { BITVAL_EOT } + }}, + { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, { + { MSR1(0), "Data error checking disabled" }, + { MSR1(1), "Data error checking enabled" }, + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0xcd, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_FREQ", "", { + { BITS_EOT } + }}, + {0x11, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + + // Per core msrs + + {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + { BITS_EOT } + }}, + {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + { BITS_EOT } + }}, + {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + { BITS_EOT } + }}, + {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + { BITS_EOT } + }}, + {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { + { BITS_EOT } + }}, + {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + { BITS_EOT } + }}, + {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { + { BITS_EOT } + }}, + {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { + { BITS_EOT } + }}, + {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { + { BITS_EOT } + }}, + {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { + { BITS_EOT } + }}, + {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { + { BITS_EOT } + }}, + {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", { + { BITS_EOT } + }}, + {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", { + { BITS_EOT } + }}, + {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + { BITS_EOT } + }}, + {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + { BITS_EOT } + }}, + {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + { BITS_EOT } + }}, + {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", "", { + { BITS_EOT } + }}, + {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + {0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + { BITS_EOT } + }}, + {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { + { BITS_EOT } + }}, + {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "", { + { BITS_EOT } + }}, + {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "", { + { BITS_EOT } + }}, + {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "", { + { BITS_EOT } + }}, + {0x345, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { + { BITS_EOT } + }}, + {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", "", { + { BITS_EOT } + }}, + {0x38e, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", "", { + { BITS_EOT } + }}, + {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", "", { + { BITS_EOT } + }}, + {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", "", { + { BITS_EOT } + }}, + {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { + { BITS_EOT } + }}, + {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + { BITS_EOT } + }}, + {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + { BITS_EOT } + }}, + {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + { BITS_EOT } + }}, + {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + { BITS_EOT } + }}, + {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + { BITS_EOT } + }}, + {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + { BITS_EOT } + }}, + {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + { BITS_EOT } + }}, + {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + { BITS_EOT } + }}, + {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + { BITS_EOT } + }}, + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + { BITS_EOT } + }}, + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + { BITS_EOT } + }}, + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + { BITS_EOT } + }}, + {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + { BITS_EOT } + }}, + {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { + { BITS_EOT } + }}, + {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", { + { BITS_EOT } + }}, + {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", { + { BITS_EOT } + }}, + {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", { + { BITS_EOT } + }}, + {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", { + { BITS_EOT } + }}, + {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", { + { BITS_EOT } + }}, + {0x480, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_BASIC", "", { + { BITS_EOT } + }}, + {0x481, MSRTYPE_RDWR, MSR2(0,0), "IA32_PINBASED_CTLS", "", { + { BITS_EOT } + }}, + {0x482, MSRTYPE_RDWR, MSR2(0,0), "IA32_PROCBASED_CTLS", "", { + { BITS_EOT } + }}, + {0x483, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_EXIT_CTLS", "", { + { BITS_EOT } + }}, + {0x484, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", "", { + { BITS_EOT } + }}, + {0x485, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_MISC", "", { + { BITS_EOT } + }}, + {0x486, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED0", "", { + { BITS_EOT } + }}, + {0x487, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED1", "", { + { BITS_EOT } + }}, + {0x488, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED0", "", { + { BITS_EOT } + }}, + {0x489, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED1", "", { + { BITS_EOT } + }}, + {0x48a, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_VMCS_ENUM", "", { + { BITS_EOT } + }}, + {0x48b, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", "", { + { BITS_EOT } + }}, + {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", { + { BITS_EOT } + }}, + {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", { + { BITS_EOT } + }}, + {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", { + { BITS_EOT } + }}, + {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", { + { BITS_EOT } + }}, + {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", { + { BITS_EOT } + }}, + {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", { + { BITS_EOT } + }}, + {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", { + { BITS_EOT } + }}, + {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", { + { BITS_EOT } + }}, + {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", { + { BITS_EOT } + }}, + {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", { + { BITS_EOT } + }}, + {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", { + { BITS_EOT } + }}, + {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", { + { BITS_EOT } + }}, + {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", { + { BITS_EOT } + }}, + {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", { + { BITS_EOT } + }}, + {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", { + { BITS_EOT } + }}, + {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", { + { BITS_EOT } + }}, + {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; + + diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c new file mode 100644 index 0000000..a2b4225 --- /dev/null +++ b/util/msrtool/intel_pentium3.c @@ -0,0 +1,182 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_pentium3_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0x6 == id->family)&((0xa == id->model)|(0xb == id->model))); +} + +const struct msrdef intel_pentium3_msrs[] = { + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + { BITS_EOT } + }}, + {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", { + { BITS_EOT } + }}, + {0x3f, MSRTYPE_RDWR, MSR2(0,0), "THERM_DIODE_OFFSET", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { + { BITS_EOT } + }}, + {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c new file mode 100644 index 0000000..5de74c1 --- /dev/null +++ b/util/msrtool/intel_pentium3_early.c @@ -0,0 +1,257 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_pentium3_early_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0x6 == id->family)&((0x7 == id->model)|(0x8 == id->model))); +} + +const struct msrdef intel_pentium3_early_msrs[] = { + {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + { BITS_EOT } + }}, + {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + { BITS_EOT } + }}, + {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", { + { BITS_EOT } + }}, + {0x88, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D0", "", { + { BITS_EOT } + }}, + {0x89, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D1", "", { + { BITS_EOT } + }}, + {0x8a, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D2", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x116, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_ADDR", "", { + { BITS_EOT } + }}, + {0x118, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_DECC", "", { + { BITS_EOT } + }}, + {0x119, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL", "", { + { BITS_EOT } + }}, + {0x11b, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_BUSY", "", { + { BITS_EOT } + }}, + {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + { BITS_EOT } + }}, + {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + { BITS_EOT } + }}, + {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", { + { BITS_EOT } + }}, + {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL0", "", { + { BITS_EOT } + }}, + {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL1", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + { BITS_EOT } + }}, + {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHFROMIP", "", { + { BITS_EOT } + }}, + {0x1dc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHTOIP", "", { + { BITS_EOT } + }}, + {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTFROMIP", "", { + { BITS_EOT } + }}, + {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTTOIP", "", { + { BITS_EOT } + }}, + {0x1e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_ROB_CR_BKUPTMPDR6", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + { BITS_EOT } + }}, + {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + { BITS_EOT } + }}, + {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + { BITS_EOT } + }}, + {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + { BITS_EOT } + }}, + {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + { BITS_EOT } + }}, + {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + { BITS_EOT } + }}, + {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + { BITS_EOT } + }}, + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + { BITS_EOT } + }}, + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c new file mode 100644 index 0000000..d6703d2 --- /dev/null +++ b/util/msrtool/intel_pentium4_early.c @@ -0,0 +1,569 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_pentium4_early_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0xf == id->family)&(0x2 == id->model)); +} + +const struct msrdef intel_pentium4_early_msrs[] = { + {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + { BITS_EOT } + }}, + {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + { BITS_EOT } + }}, + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", { + { BITS_EOT } + }}, + {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", { + { BITS_EOT } + }}, + {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", { + { BITS_EOT } + }}, + {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", { + { BITS_EOT } + }}, + {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", { + { BITS_EOT } + }}, + {0x304, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER0", "", { + { BITS_EOT } + }}, + {0x305, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER1", "", { + { BITS_EOT } + }}, + {0x306, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER2", "", { + { BITS_EOT } + }}, + {0x307, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER3", "", { + { BITS_EOT } + }}, + {0x308, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER0", "", { + { BITS_EOT } + }}, + {0x309, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER1", "", { + { BITS_EOT } + }}, + {0x30a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER2", "", { + { BITS_EOT } + }}, + {0x30b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER3", "", { + { BITS_EOT } + }}, + {0x30c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER0", "", { + { BITS_EOT } + }}, + {0x30d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER1", "", { + { BITS_EOT } + }}, + {0x30e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER2", "", { + { BITS_EOT } + }}, + {0x30f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER3", "", { + { BITS_EOT } + }}, + {0x310, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER4", "", { + { BITS_EOT } + }}, + {0x311, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER5", "", { + { BITS_EOT } + }}, + {0x360, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR0", "", { + { BITS_EOT } + }}, + {0x361, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR1", "", { + { BITS_EOT } + }}, + {0x362, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR2", "", { + { BITS_EOT } + }}, + {0x363, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR3", "", { + { BITS_EOT } + }}, + {0x364, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR0", "", { + { BITS_EOT } + }}, + {0x365, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR1", "", { + { BITS_EOT } + }}, + {0x366, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR2", "", { + { BITS_EOT } + }}, + {0x367, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR3", "", { + { BITS_EOT } + }}, + {0x368, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR0", "", { + { BITS_EOT } + }}, + {0x369, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR1", "", { + { BITS_EOT } + }}, + {0x36a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR2", "", { + { BITS_EOT } + }}, + {0x36b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR3", "", { + { BITS_EOT } + }}, + {0x36c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR0", "", { + { BITS_EOT } + }}, + {0x36d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR1", "", { + { BITS_EOT } + }}, + {0x36e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR2", "", { + { BITS_EOT } + }}, + {0x36f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR3", "", { + { BITS_EOT } + }}, + {0x370, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR4", "", { + { BITS_EOT } + }}, + {0x371, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR5", "", { + { BITS_EOT } + }}, + {0x3a0, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR0", "", { + { BITS_EOT } + }}, + {0x3a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR1", "", { + { BITS_EOT } + }}, + {0x3a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR0", "", { + { BITS_EOT } + }}, + {0x3a3, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR1", "", { + { BITS_EOT } + }}, + {0x3a4, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR0", "", { + { BITS_EOT } + }}, + {0x3a5, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR1", "", { + { BITS_EOT } + }}, + {0x3a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR0", "", { + { BITS_EOT } + }}, + {0x3a7, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR1", "", { + { BITS_EOT } + }}, + {0x3a8, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR0", "", { + { BITS_EOT } + }}, + {0x3a9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR1", "", { + { BITS_EOT } + }}, + {0x3aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR0", "", { + { BITS_EOT } + }}, + {0x3ab, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR1", "", { + { BITS_EOT } + }}, + {0x3ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR0", "", { + { BITS_EOT } + }}, + {0x3ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR1", "", { + { BITS_EOT } + }}, + {0x3ae, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR0", "", { + { BITS_EOT } + }}, + {0x3af, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR1", "", { + { BITS_EOT } + }}, + {0x3b0, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR0", "", { + { BITS_EOT } + }}, + {0x3b1, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR1", "", { + { BITS_EOT } + }}, + {0x3b2, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR0", "", { + { BITS_EOT } + }}, + {0x3b3, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", { + { BITS_EOT } + }}, + {0x3b4, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR0", "", { + { BITS_EOT } + }}, + {0x3b5, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", { + { BITS_EOT } + }}, + {0x3b6, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR0", "", { + { BITS_EOT } + }}, + {0x3b7, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR1", "", { + { BITS_EOT } + }}, + {0x3b8, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR0", "", { + { BITS_EOT } + }}, + {0x3b9, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR1", "", { + { BITS_EOT } + }}, + {0x3ba, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR0", "", { + { BITS_EOT } + }}, + {0x3bb, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR1", "", { + { BITS_EOT } + }}, + {0x3bc, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR0", "", { + { BITS_EOT } + }}, + {0x3bd, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR1", "", { + { BITS_EOT } + }}, + {0x3be, MSRTYPE_RDWR, MSR2(0,0), "MSR_SSU_ESCR0", "", { + { BITS_EOT } + }}, + {0x3c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR0", "", { + { BITS_EOT } + }}, + {0x3c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR1", "", { + { BITS_EOT } + }}, + {0x3c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR0", "", { + { BITS_EOT } + }}, + {0x3c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR1", "", { + { BITS_EOT } + }}, + {0x3c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR0", "", { + { BITS_EOT } + }}, + {0x3c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR1", "", { + { BITS_EOT } + }}, + {0x3c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", { + { BITS_EOT } + }}, + {0x3c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR1", "", { + { BITS_EOT } + }}, + {0x3ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR0", "", { + { BITS_EOT } + }}, + {0x3cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR1", "", { + { BITS_EOT } + }}, + {0x3cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR2", "", { + { BITS_EOT } + }}, + {0x3cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR3", "", { + { BITS_EOT } + }}, + {0x3e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR4", "", { + { BITS_EOT } + }}, + {0x3e1, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR5", "", { + { BITS_EOT } + }}, + {0x3f0, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_PRECISE_EVENT", "", { + { BITS_EOT } + }}, + {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_ENABLE", "", { + { BITS_EOT } + }}, + {0x3f2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_MATRIX_VERT", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + { BITS_EOT } + }}, + {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + { BITS_EOT } + }}, + {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + { BITS_EOT } + }}, + {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + { BITS_EOT } + }}, + {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + { BITS_EOT } + }}, + {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + { BITS_EOT } + }}, + {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + { BITS_EOT } + }}, + {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + { BITS_EOT } + }}, + {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + { BITS_EOT } + }}, + {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + { BITS_EOT } + }}, + {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + { BITS_EOT } + }}, + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + { BITS_EOT } + }}, + {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + { BITS_EOT } + }}, + {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", { + { BITS_EOT } + }}, + {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", { + { BITS_EOT } + }}, + {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", { + { BITS_EOT } + }}, + {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", { + { BITS_EOT } + }}, + {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", { + { BITS_EOT } + }}, + {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", { + { BITS_EOT } + }}, + {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", { + { BITS_EOT } + }}, + {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", { + { BITS_EOT } + }}, + {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", { + { BITS_EOT } + }}, + {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", { + { BITS_EOT } + }}, + {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", { + { BITS_EOT } + }}, + {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", { + { BITS_EOT } + }}, + {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", { + { BITS_EOT } + }}, + {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", { + { BITS_EOT } + }}, + {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", { + { BITS_EOT } + }}, + {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", { + { BITS_EOT } + }}, + {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", { + { BITS_EOT } + }}, + {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", { + { BITS_EOT } + }}, + {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", { + { BITS_EOT } + }}, + {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { + { BITS_EOT } + }}, + {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", { + { BITS_EOT } + }}, + {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { + { BITS_EOT } + }}, + {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0", "", { + { BITS_EOT } + }}, + {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2", "", { + { BITS_EOT } + }}, + {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3", "", { + { BITS_EOT } + }}, + {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", { + { BITS_EOT } + }}, + {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c new file mode 100644 index 0000000..6bb6ebe --- /dev/null +++ b/util/msrtool/intel_pentium4_later.c @@ -0,0 +1,342 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2011 Anton Kochkov <anton.kochkov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_pentium4_later_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return ((0xf == id->family)&((0x3 == id->model)|(0x4 == id->model))); +} + +const struct msrdef intel_pentium4_later_msrs[] = { + {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + { BITS_EOT } + }}, + {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + { BITS_EOT } + }}, + {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", { + { BITS_EOT } + }}, + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", { + { BITS_EOT } + }}, + {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", { + { BITS_EOT } + }}, + {0x2c, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_FREQUENCY_ID", "", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + {0x1a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PLATFORM_BRV", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + { BITS_EOT } + }}, + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + { BITS_EOT } + }}, + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + { BITS_EOT } + }}, + {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", { + { BITS_EOT } + }}, + {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", { + { BITS_EOT } + }}, + {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", { + { BITS_EOT } + }}, + {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", { + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + { BITS_EOT } + }}, + {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + { BITS_EOT } + }}, + {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + { BITS_EOT } + }}, + {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + { BITS_EOT } + }}, + {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + { BITS_EOT } + }}, + {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + { BITS_EOT } + }}, + {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + { BITS_EOT } + }}, + {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + { BITS_EOT } + }}, + {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + { BITS_EOT } + }}, + {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + { BITS_EOT } + }}, + {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + { BITS_EOT } + }}, + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + { BITS_EOT } + }}, + {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + { BITS_EOT } + }}, + {0x9b, MSRTYPE_RDWR, MSR2(0,0), "IA32_SMM_MONITOR_CTL", "", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + { BITS_EOT } + }}, + {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + { BITS_EOT } + }}, + {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + { BITS_EOT } + }}, + {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { BITS_EOT } + }}, + {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", { + { BITS_EOT } + }}, + {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", { + { BITS_EOT } + }}, + {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", { + { BITS_EOT } + }}, + {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", { + { BITS_EOT } + }}, + {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", { + { BITS_EOT } + }}, + {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", { + { BITS_EOT } + }}, + {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", { + { BITS_EOT } + }}, + {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", { + { BITS_EOT } + }}, + {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", { + { BITS_EOT } + }}, + {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", { + { BITS_EOT } + }}, + {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", { + { BITS_EOT } + }}, + {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", { + { BITS_EOT } + }}, + {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", { + { BITS_EOT } + }}, + {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", { + { BITS_EOT } + }}, + {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", { + { BITS_EOT } + }}, + {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", { + { BITS_EOT } + }}, + {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", { + { BITS_EOT } + }}, + {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", { + { BITS_EOT } + }}, + {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + { BITS_EOT } + }}, + {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { + { BITS_EOT } + }}, + {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", { + { BITS_EOT } + }}, + {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { + { BITS_EOT } + }}, + {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", { + { BITS_EOT } + }}, + {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", { + { BITS_EOT } + }}, + { MSR_EOT } +}; + diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 86fc2f9..21f9c9d 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -44,6 +44,13 @@ static struct targetdef alltargets[] = { { "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs }, { "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs }, { "K8", "AMD K8 Family", k8_probe, k8_msrs }, + { "intel_pentium3_early", "Intel Pentium III family", intel_pentium3_early_probe, intel_pentium3_early_msrs }, + { "intel_pentium3", "Intel Pentium III Xeon Processor, Intel Pentium III Processor", intel_pentium3_probe, intel_pentium3_msrs }, + { "intel_core1", "Intel Core Duo, Intel Core Solo processors", intel_core1_probe, intel_core1_msrs }, + { "intel_core2_early", "Intel Xeon Processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series, Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel Pentium dual-core processors", intel_core2_early_probe, intel_core2_early_msrs }, + { "intel_core2_later", "Intel Xeon Processor 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000 series", intel_core2_later_probe, intel_core2_later_msrs }, + { "intel_pentium4_early", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4 processors", intel_pentium4_early_probe, intel_pentium4_early_msrs }, + { "intel_pentium4_later", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4, Pentium D processors", intel_pentium4_later_probe, intel_pentium4_later_msrs }, { TARGET_EOT } }; diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 0441e3f..e6cea46 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -214,4 +214,32 @@ extern const struct msrdef cs5536_msrs[]; extern int k8_probe(const struct targetdef *t); extern const struct msrdef k8_msrs[]; +/* intel_pentium3_early.c */ +extern int intel_pentium3_early_probe(const struct targetdef *t); +extern const struct msrdef intel_pentium3_early_msrs[]; + +/* intel_pentium3.c */ +extern int intel_pentium3_probe(const struct targetdef *t); +extern const struct msrdef intel_pentium3_msrs[]; + +/* intel_core1.c */ +extern int intel_core1_probe(const struct targetdef *t); +extern const struct msrdef intel_core1_msrs[]; + +/* intel_core2_early.c */ +extern int intel_core2_early_probe(const struct targetdef *t); +extern const struct msrdef intel_core2_early_msrs[]; + +/* intel_core2_later.c */ +extern int intel_core2_later_probe(const struct targetdef *t); +extern const struct msrdef intel_core2_later_msrs[]; + +/* intel_pentium4_early.c */ +extern int intel_pentium4_early_probe(const struct targetdef *t); +extern const struct msrdef intel_pentium4_early_msrs[]; + +/* intel_pentium4_later.c */ +extern int intel_pentium4_later_probe(const struct targetdef *t); +extern const struct msrdef intel_pentium4_later_msrs[]; + #endif /* MSRTOOL_H */

1 0

Re: [coreboot] build failure: cannot move location counter backwards
by Darren Hart 23 Jun '11

23 Jun '11

On 06/23/2011 10:18 AM, Stefan Reinauer wrote: > On Tue, Jun 21, 2011 at 8:34 PM, Kevin O'Connor <kevin(a)koconnor.net> wrote: >> >> On Mon, Jun 20, 2011 at 10:58:06PM -0700, Darren Hart wrote: >>> On 06/20/2011 04:09 PM, Cristian Măgherușan-Stanciu wrote: >>>> Hi, >>>> >>>> I documented the latest developments (git and crossgcc) at >>>> http://www.coreboot.org/Build_HOWTO. Please someone double-check. >>> >>> My build succeeded following these instructions. As a first-time user, >>> it would be helpful to have a quick-start guide which would be basically >>> this wiki page + the steps necessary to do boot what I built in qemu. >>> There are bits of that here: >>> >>> http://www.coreboot.org/QEMU >> >> Unfortunately, it looks like that page has old information on it. >> > > Which version of Qemu was that again? $ qemu --version QEMU PC emulator version 0.12.5 (qemu-kvm-0.12.5), Copyright (c) 2003-2008 Fabrice Bellard > >> >>> Is it integrated into the payload? Reading the >>> QEMU_Build_tutorial, http://www.coreboot.org/QEMU_Build_Tutorial, led me >>> to try: >>> >>> $ qemu -bios build/coreboot.rom -hda /dev/zero -serial stdio >>> >>> This resulted in something else entirely, the shell output terminating >>> in the following: >>> >>> coreboot memory table: >>> 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES >>> 1. 0000000000001000-000000000009ffff: RAM >>> 2. 00000000000c0000-0000000017feffff: RAM >>> 3. 0000000017ff0000-0000000017ffffff: CONFIGURATION TABLES >>> 4. 00000000ff800000-00000000ffffffff: RESERVED >>> Wrote coreboot table at: 17ff1400 - 17ff15c4 checksum 6c1c >>> coreboot table: 452 bytes. >>> Multiboot Information structure has been written. >>> 0. FREE SPACE 17ff3400 0000cc00 >>> 1. GDT 17ff0200 00000200 >>> 2. IRQ TABLE 17ff0400 00001000 >>> 3. COREBOOT 17ff1400 00002000 >>> Check CBFS header at fffcfc39 >>> magic is 386f92fa >>> ERROR: No valid CBFS header found! >>> CBFS: Could not find file fallback/payload >>> Boot failed. >> >> You're now running coreboot, but coreboot was unable to find your >> payload (eg, SeaBIOS). > > However, it seems the CBFS header is corrupted, so it is not even > checking for a payload file. > > Not sure why, on first sight. Alright. What I'm trying to do here is demonstrate a known working state and use-case of coreboot. Once I have that working I want to start looking at getting it working on my hardware. Is there a better known-working state of coreboot I can use? I'd prefer to stick with qemu for this part. -- Darren Hart Intel Open Source Technology Center Yocto Project - Linux Kernel

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coreboot June 2011