coreboot June 2011

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274 discussions

New patch to review: 6db59f0 PMH7: add missing License Header
by Sven Schnelle 22 Jun '11

22 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/55 -gerrit commit 6db59f0fd58a0305ee8382853363fbc6657e6260 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 22 16:08:20 2011 +0200 PMH7: add missing License Header Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/ec/lenovo/pmh7/chip.h | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h index 9867ba6..725a5d5 100644 --- a/src/ec/lenovo/pmh7/chip.h +++ b/src/ec/lenovo/pmh7/chip.h @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef EC_LENOVO_PMH7_CHIP_H #define EC_LENOVO_PMH7_CHIP_H

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Patch merged into master: 334ef9e Move SB800 clock init earlier
by gerrit＠coreboot.org 21 Jun '11

21 Jun '11

the following patch was just integrated into master: commit 334ef9eebc951aaee3c880231f29f1b7c681edd9 Author: Scott Duplichan <scott(a)notabs.org> Date: Tue Jun 21 20:05:19 2011 -0500 Move SB800 clock init earlier Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled. Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> See http://review.coreboot.org/32 for details. -gerrit

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Patch merged into master: 6f25945 Add the coreboot config to CBFS
by gerrit＠coreboot.org 21 Jun '11

21 Jun '11

the following patch was just integrated into master: commit 6f25945813eb935b31a6f7886abd3ada9af90232 Author: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Date: Sun Jun 19 03:03:28 2011 +0200 Add the coreboot config to CBFS The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build the current coreboot image. For space savings, all the comments and empty lines were removed from the original config, except for one that lists the coreboot git revision that's built into the image. This is done in order to easily reproduce the work of someone else when only having their ROM image. In theory the reproduce could even be automated by a new dedicated make target. This should work even with abuild now. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> See http://review.coreboot.org/46 for details. -gerrit

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Patch set updated: 334ef9e Move SB800 clock init earlier
by Marshall Buschman 21 Jun '11

21 Jun '11

Marshall Buschman (mbuschman(a)lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/32 -gerrit commit 334ef9eebc951aaee3c880231f29f1b7c681edd9 Author: Scott Duplichan <scott(a)notabs.org> Date: Tue Jun 21 20:05:19 2011 -0500 Move SB800 clock init earlier Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled. Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> --- src/mainboard/asrock/e350m1/romstage.c | 26 +++++++++++++++----------- 1 files changed, 15 insertions(+), 11 deletions(-) diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 61de9f6..29df530 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,6 +55,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr(0xc0010062, 0); + if (boot_cpu()) { + u8 reg8; + // SB800: Program AcpiMmioEn to enable MMIO access to MiscCntrl register + outb(0x24, 0xCD6); + reg8 = inb(0xCD7); + reg8 |= 1; + reg8 &= ~(1 << 1); + outb(0x24, 0xCD6); + outb(reg8, 0xCD7); + + // Program SB800 MiscCntrl + *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */ + } + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); @@ -63,17 +78,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } - //reg8 = pmio_read(0x24); - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - //pmio_write(0x24, reg8); - outb(0x24, 0xCD6); - outb(reg8, 0xCD7); - - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */ /* Halt if there was a built in self test failure */ post_code(0x34);

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hi every one...
by krishnateja kesineni 21 Jun '11

21 Jun '11

i krishna teja kesineni. working in a research institute in india.. i and my batch intended to develop a a BIOS over a coreboot for our own design boards.. we not interested to go for proprietary BIOS. plz say anyone is there in india to teach and support us.. plzz get me know.. thank Q -- *--* *Regards, Krishna Teja Kesineni, Mtech in Information Security, National Inistuite of Technology, Rourkela, India Phone: +91-9692598754 E-mail: tejakesineni(a)gmail.com; 210cs2265(a)nitrkl.ac.in Blog: http://teja4u.110mb.com/* * Please don’t print this e-mail unless it is necessary. Save<http://www.indiatogether.org> Trees. *

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Patch set updated: 6f25945 Add the coreboot config to CBFS
by Cristian Măgherușan-Stanciu 21 Jun '11

21 Jun '11

Cristian Măgherușan-Stanciu (cristi.magherusan(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/46 -gerrit commit 6f25945813eb935b31a6f7886abd3ada9af90232 Author: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Date: Sun Jun 19 03:03:28 2011 +0200 Add the coreboot config to CBFS The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build the current coreboot image. For space savings, all the comments and empty lines were removed from the original config, except for one that lists the coreboot git revision that's built into the image. This is done in order to easily reproduce the work of someone else when only having their ROM image. In theory the reproduce could even be automated by a new dedicated make target. This should work even with abuild now. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> --- src/Kconfig | 6 ++++++ src/arch/x86/Makefile.inc | 7 +++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 9abbc21..7e6214a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -106,6 +106,12 @@ config COMPRESS_RAMSTAGE that decompression might slow down booting if the boot flash is connected through a slow Link (i.e. SPI) +config INCLUDE_CONFIG_FILE + bool "Include the coreboot config file into the ROM image" + default y + help + Include in CBFS the coreboot config file that was used to compile the ROM image + endmenu source src/mainboard/Kconfig diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8c1a887..e9c00de 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -99,6 +99,13 @@ ifeq ($(CONFIG_GEODE_VSA_FILE),y) $(LD) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(obj)/vsa.o -o $(obj)/vsa.elf $(CBFSTOOL) $@.tmp add-stage $(obj)/vsa.elf vsa endif +ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) + @printf " CONFIG $(DOTCONFIG)\n" + if [ -f $(DOTCONFIG) ]; then \ + echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ + sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ + $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

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Patch merged into master: 2bea70b Move existing AMD Ffamily14 code to f14 folder
by gerrit＠coreboot.org 21 Jun '11

21 Jun '11

the following patch was just integrated into master: commit 2bea70b63e83700860e4f65407495605cab01b72 Author: efdesign98 <efdesign98(a)gmail.com> Date: Mon Jun 20 18:12:43 2011 -0700 Move existing AMD Ffamily14 code to f14 folder This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/52 for details. -gerrit

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Patch merged into master: d4eeb24 Rename {CPU|NB|SB}/amd/*_wrapper folders
by gerrit＠coreboot.org 21 Jun '11

21 Jun '11

the following patch was just integrated into master: commit d4eeb246f4d7215c7bd3df3fdf389cab1962972a Author: efdesign98 <efdesign98(a)gmail.com> Date: Mon Jun 20 17:38:49 2011 -0700 Rename {CPU|NB|SB}/amd/*_wrapper folders This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/51 for details. -gerrit

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Patch merged into master: 99c5339 Add AMD SB900 CIMx code
by gerrit＠coreboot.org 21 Jun '11

21 Jun '11

the following patch was just integrated into master: commit 99c533902f2a583b41597ebfcb2aa7cab6e8aee9 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Jun 16 16:39:30 2011 -0700 Add AMD SB900 CIMx code This code is added to support the AMD SB900 southbridge. Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/41 for details. -gerrit

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Patch merged into master: c23fab3 Add AMD Family 12 cpu Agesa code
by gerrit＠coreboot.org 21 Jun '11

21 Jun '11

the following patch was just integrated into master: commit c23fab3152a33ce09aec322a1cca6a3118d63118 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Jun 16 16:35:54 2011 -0700 Add AMD Family 12 cpu Agesa code This is the addition of the AMD Family 12 cpu code. Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c Signed-off-by: Frank Vibrans<frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/40 for details. -gerrit

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coreboot June 2011