coreboot June 2011

coreboot@coreboot.org

55 participants
274 discussions

Fwd: Fonts at the Bios
by dove - railing 19 Jun '11

19 Jun '11

---------- Forwarded message ---------- From: dove - railing <doverailing(a)gmail.com> Date: Sun, Jun 5, 2011 at 10:49 AM Subject: Re: [coreboot] Fonts at the Bios To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> On Sun, Jun 5, 2011 at 1:30 AM, Stefan Reinauer < stefan.reinauer(a)coreboot.org> wrote: > On 6/4/11 3:22 PM, dove - railing wrote: > >> I am not a techie. >> >> Would it be correct to say that fonts at the Bios level are decided by the >> Video card / VGA firmware? >> > The VGA BIOS loads the initial font. > > > Is there an opensource utility for them? >> >> I found this, it's not open source though: > > http://www.procon.com.au/HVVCBIOS.htm > <http://www.coreboot.org/mailman/listinfo/coreboot> Could not http://www.flashrom.org/Flashrom utility be an opensource utility for Video card / VGA Bios? Regards, Meeku

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OT: Asus M2V-MX SE (VIA K8T890): vendor BIOS: SATA-II disk only detected as UDMA/100
by Paul Menzel 19 Jun '11

19 Jun '11

Dear coreboot folks, this question is off-topic because the board is running the vendor BIOS. $ sudo dmidecode […] # dmidecode 2.9 SMBIOS 2.4 present. 49 structures occupying 1801 bytes. Table at 0x000F0740. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: American Megatrends Inc. Version: 0304 Release Date: 10/30/2007 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 512 kB […] I had to replace my hard drive and bought a new SATA-II disk. Unfortunately the full speed is not detected. Instead of UDMA/133 – as was used with the old SATA-I disk – it is reporting UDMA/100. $ uname -a Linux joe 2.6.32-5-amd64 #1 SMP Tue Mar 8 22:49:26 UTC 2011 x86_64 GNU/Linux $ dmesg # new SATA-II disk […] [ 0.792878] ata3: SATA max UDMA/133 cmd 0xec00 ctl 0xe880 bmdma 0xe400 irq 21 [ 0.792881] ata4: SATA max UDMA/133 cmd 0xe800 ctl 0xe480 bmdma 0xe408 irq 21 […] [ 1.384015] ata4: SATA link up 1.5 Gbps (SStatus 123 SControl 300) [ 1.392019] usb 2-1: new low speed USB device using uhci_hcd and address 2 [ 1.548219] ata4.00: ATA-8: WDC WD20EARS-60MVWB0, 51.0AB51, max UDMA/100 Here seems to be the problematic line, that somehow the drive is reporting the wrong maximum speed or the chipset does not detect it correctly. [ 1.548223] ata4.00: 3907029168 sectors, multi 16: LBA48 NCQ (depth 0/32) [ 1.556240] ata4.00: configured for UDMA/100 [ 1.556343] scsi 3:0:0:0: Direct-Access ATA WDC WD20EARS-60M 51.0 PQ: 0 ANSI: 5 […] $ dmesg # old SATA-I disk [ 0.779300] ata1: SATA max UDMA/133 cmd 0xec00 ctl 0xe880 bmdma 0xe400 irq 21 [ 0.779303] ata2: SATA max UDMA/133 cmd 0xe800 ctl 0xe480 bmdma 0xe408 irq 21 […] [ 0.980024] ata1: SATA link up 1.5 Gbps (SStatus 123 SControl 300) [ 0.980427] ata3.00: configured for UDMA/33 [ 1.144418] ata1.00: ATA-8: Hitachi HDP725050GLA360, GM4OA52A, max UDMA/133 [ 1.144421] ata1.00: 976773168 sectors, multi 16: LBA48 NCQ (depth 0/32) [ 1.160414] ata1.00: configured for UDMA/133 [ 1.160566] scsi 0:0:0:0: Direct-Access ATA Hitachi HDP72505 GM4O PQ: 0 ANSI: 5 [ 1.364012] ata2: SATA link down 1.5 Gbps (SStatus 0 SControl 300) […] So I am posting this question to the coreboot list since you guys having ported the Asus M2V-MX SE to coreboot probably know of some limitations of the VIA chipset and how to solve this. If not a pointer to the correct list would be nice. Thanks, Paul

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New patch to review: caa9edc Fix memory size reporting on AMD family 14h systems for >= 4GB
by Marshall Buschman 19 Jun '11

19 Jun '11

Marshall Buschman (mbuschman(a)lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/48 -gerrit commit caa9edc3e49be41dbcd48ae5e594c0bf8dcae34f Author: Scott Duplichan <scott(a)notabs.org> Date: Sun Jun 19 11:27:21 2011 -0500 Fix memory size reporting on AMD family 14h systems for >= 4GB Applying Scott Duplichan's fix for memory >=4GB Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> --- .../amd/agesa_wrapper/family14/northbridge.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa_wrapper/family14/northbridge.c b/src/northbridge/amd/agesa_wrapper/family14/northbridge.c index af7d130..4eb589d 100644 --- a/src/northbridge/amd/agesa_wrapper/family14/northbridge.c +++ b/src/northbridge/amd/agesa_wrapper/family14/northbridge.c @@ -652,8 +652,8 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); d = get_dram_base_mask(0); if (d.mask & 1) { - basek = ((resource_t)(d.base)) << 8; - limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); + basek = ((resource_t)((u64)d.base)) << 8; + limitk = (resource_t)(((u64)d.mask << 8) | 0xFFFFFF); printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); /* Convert these values to multiples of 1K for ease of math. */

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System management mode for Intel processors
by ali hagigat 19 Jun '11

19 Jun '11

I wonder if anybody can explain the system management mode RAM addresses for Intel Pentium III/815/ICH2. I know that SMBASE is 30000 after reset. But 815 can define TSEG (and HSEG ) and also AB segments some where else. Like TSEG can be 512k or 1M from the top of memory. Considering that SMBASE can not be any thing but 30000 as the Intel manual is saying , from what addresses CPU instructions are fetched after SMI# interrupt at last?

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New patch to review: 8cfdef3 Fix memory size reporting on AMD family 14h systems for >= 4GB
by Marshall Buschman 19 Jun '11

19 Jun '11

Marshall Buschman (mbuschman(a)lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/47 -gerrit commit 8cfdef386203ab8fdba72786e784689b6ea6fadf Author: Scott Duplichan <scott(a)notabs.org> Date: Sun Jun 19 02:02:04 2011 -0500 Fix memory size reporting on AMD family 14h systems for >= 4GB Applying Scott Duplichan's fix for memory >=4GB Change-Id: Id687e6412a6bd600b07cef23220b0b6ecfcb1870 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> --- .../amd/agesa_wrapper/family14/northbridge.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa_wrapper/family14/northbridge.c b/src/northbridge/amd/agesa_wrapper/family14/northbridge.c index af7d130..4eb589d 100644 --- a/src/northbridge/amd/agesa_wrapper/family14/northbridge.c +++ b/src/northbridge/amd/agesa_wrapper/family14/northbridge.c @@ -652,8 +652,8 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); d = get_dram_base_mask(0); if (d.mask & 1) { - basek = ((resource_t)(d.base)) << 8; - limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); + basek = ((resource_t)((u64)d.base)) << 8; + limitk = (resource_t)(((u64)d.mask << 8) | 0xFFFFFF); printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); /* Convert these values to multiples of 1K for ease of math. */

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Patch set updated: e8ea34f Add the coreboot config to CBFS
by Cristian Măgherușan-Stanciu 19 Jun '11

19 Jun '11

Cristian Măgherușan-Stanciu (cristi.magherusan(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/46 -gerrit commit e8ea34f0553edb7144536fa0f514e70daf0e7065 Author: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Date: Sun Jun 19 03:03:28 2011 +0200 Add the coreboot config to CBFS The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build coreboot. For space savings, all the comments and empty lines were removed from the original config. This is done in order to easily reproduce the process of creating an image made by someone else when only having the original binary image. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> --- src/Kconfig | 6 ++++++ src/arch/x86/Makefile.inc | 6 ++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 9abbc21..7e6214a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -106,6 +106,12 @@ config COMPRESS_RAMSTAGE that decompression might slow down booting if the boot flash is connected through a slow Link (i.e. SPI) +config INCLUDE_CONFIG_FILE + bool "Include the coreboot config file into the ROM image" + default y + help + Include in CBFS the coreboot config file that was used to compile the ROM image + endmenu source src/mainboard/Kconfig diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8c1a887..2c25227 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -99,6 +99,12 @@ ifeq ($(CONFIG_GEODE_VSA_FILE),y) $(LD) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(obj)/vsa.o -o $(obj)/vsa.elf $(CBFSTOOL) $@.tmp add-stage $(obj)/vsa.elf vsa endif +ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) + @printf "config $(CONFIG_INCLUDE_CONFIG_FILE)\n" + sed -e '/^#/d' -e '/^ *$$/d' $(top)/.config > $(obj)/config.tmp + $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw + rm -f $(obj)/config.tmp +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

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New patch to review: 9ed4b8f Add the coreboot config to CBFS
by Cristian Măgherușan-Stanciu 19 Jun '11

19 Jun '11

Cristian Măgherușan-Stanciu (cristi.magherusan(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/46 -gerrit commit 9ed4b8f3aef177e556c0e16cd1da27ba3bca2f4d Author: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Date: Sun Jun 19 03:03:28 2011 +0200 Add the coreboot config to CBFS The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build coreboot. For space savings, all the comments and empty lines were removed from the original config. This is done in order to easily reproduce the process of creating an image made by someone else when only having the original binary image. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> --- src/Kconfig | 6 ++++++ src/arch/x86/Makefile.inc | 6 ++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 9abbc21..7e6214a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -106,6 +106,12 @@ config COMPRESS_RAMSTAGE that decompression might slow down booting if the boot flash is connected through a slow Link (i.e. SPI) +config INCLUDE_CONFIG_FILE + bool "Include the coreboot config file into the ROM image" + default y + help + Include in CBFS the coreboot config file that was used to compile the ROM image + endmenu source src/mainboard/Kconfig diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8c1a887..9a586ac 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -99,6 +99,12 @@ ifeq ($(CONFIG_GEODE_VSA_FILE),y) $(LD) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(obj)/vsa.o -o $(obj)/vsa.elf $(CBFSTOOL) $@.tmp add-stage $(obj)/vsa.elf vsa endif +ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) + @printf "config $(CONFIG_INCLUDE_CONFIG_FILE)\n" + sed -e '/^#/d' -e '/^ *$$/d' .config > $(obj)/config.tmp + $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw + rm -f $(obj)/config.tmp +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print

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Patch merged into master: d22355c ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
by gerrit＠coreboot.org 19 Jun '11

19 Jun '11

the following patch was just integrated into master: commit d22355cefabca65598a37ef8e0438d89c382174d Author: Scott Duplichan <scott(a)notabs.org> Date: Sat Jun 18 10:46:45 2011 -0500 ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> See http://review.coreboot.org/44 for details. -gerrit

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New patch to review: e50646e ASRock E350M1: Enable USB3 support
by Marshall Buschman 18 Jun '11

18 Jun '11

Marshall Buschman (mbuschman(a)lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/45 -gerrit commit e50646e88e64af4305517ea8ded3c52bdf9f5bcc Author: Marshall Buschman <mbuschman(a)lucidmachines.com> Date: Sat Jun 18 12:04:41 2011 -0500 ASRock E350M1: Enable USB3 support Requires Scott Duplichan's patch for NIC support. Enables required PCIe port for USB3 - does not interfere with normal operations on non-USB3 model. Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9 Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> --- src/mainboard/asrock/e350m1/devicetree.cb | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index bc3bd18..43607eb 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -100,8 +100,8 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 off end # PCIe PortC + device pci 15.1 on end # PCIe PortB: NIC + device pci 15.2 on end # PCIe PortC: USB3 device pci 15.3 off end # PCIe PortD # gpp_configuration options

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New patch to review: d22355c ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
by Marshall Buschman 18 Jun '11

18 Jun '11

Marshall Buschman (mbuschman(a)lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/44 -gerrit commit d22355cefabca65598a37ef8e0438d89c382174d Author: Scott Duplichan <scott(a)notabs.org> Date: Sat Jun 18 10:46:45 2011 -0500 ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> --- src/mainboard/asrock/e350m1/devicetree.cb | 14 +++++++++-- src/southbridge/amd/cimx_wrapper/sb800/late.c | 31 +++++++++---------------- 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index d1e4a8b..bc3bd18 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -99,11 +99,19 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + + # gpp_configuration options + #0000: PortA lanes[3:0] + #0001: N/A + #0010: PortA lanes[1:0], PortB lanes[3:2] + #0011: PortA lanes[1:0], PortB lane2, PortC lane3 + #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. + register "gpp_configuration" = "4" + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c index 50eeb48..6926443 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/late.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c @@ -413,16 +413,13 @@ static void sb800_enable(device_t dev) break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ - sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled; - return; - case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ - sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled; - return; - case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ - sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled; - return; - case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ - sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled; + { + device_t device; + for (device = dev; device; device = device->next) { + if (dev->path.type != DEVICE_PATH_PCI) continue; + if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; + sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; + } /* * GPP_CFGMODE_X4000: PortA Lanes[3:0] @@ -430,22 +427,16 @@ static void sb800_enable(device_t dev) * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 */ - if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { - sb_config->GppLinkConfig = sb_chip->gpp_configuration; - } - - sbPcieGppEarlyInit(sb_config); + sb_config->GppLinkConfig = sb_chip->gpp_configuration; + sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + AmdSbDispatcher(sb_config); break; + } default: break; } - /* Special setting ABCFG registers before PCI emulation. */ - abSpecialSetBeforePciEnum(sb_config); - usbDesertPll(sb_config); - //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - //AmdSbDispatcher(sb_config); } struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {

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coreboot June 2011