coreboot June 2011

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Patch set updated: eaded8a i945 GMA: restore tft brightness from cmos
by Sven Schnelle 15 Jun '11

15 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/24 -gerrit commit eaded8a99aaf430d28b0ae3e01858a3d38fb8427 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 12 14:30:10 2011 +0200 i945 GMA: restore tft brightness from cmos Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/devicetree.cb | 1 - src/mainboard/lenovo/t60/romstage.c | 2 -- src/mainboard/lenovo/x60/devicetree.cb | 1 - src/mainboard/lenovo/x60/romstage.c | 2 -- src/northbridge/intel/i945/gma.c | 7 +++++++ 5 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 5419d71..4de1be3 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -21,7 +21,6 @@ ## chip northbridge/intel/i945 - device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index aa92765..252ae40 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -336,6 +336,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 42a45d1..1647f7a 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -21,7 +21,6 @@ ## chip northbridge/intel/i945 - device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index c993a35..2aa506f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -338,6 +338,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index a43ef25..340ddcd 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> static void gma_func0_init(struct device *dev) { @@ -36,11 +37,17 @@ static void gma_func0_init(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; + u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + if (!get_option(&val, "tft_brightness")) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch merged into master: 09d29a9 Remove old ACPI code
by gerrit＠coreboot.org 15 Jun '11

15 Jun '11

the following patch was just integrated into master: commit 09d29a9a8cff248ff3eb64b532ab61ee978511e7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 15 17:13:27 2011 +0200 Remove old ACPI code it isn't used anywhere, and could be fetched from git/svn history if needed. Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/35 for details. -gerrit

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New patch to review: 09d29a9 Remove old ACPI code
by Sven Schnelle 15 Jun '11

15 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/35 -gerrit commit 09d29a9a8cff248ff3eb64b532ab61ee978511e7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 15 17:13:27 2011 +0200 Remove old ACPI code it isn't used anywhere, and could be fetched from git/svn history if needed. Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/intel/d945gclf/acpi_tables.c | 93 ---------------------------- src/mainboard/lenovo/t60/acpi_tables.c | 55 ---------------- src/mainboard/lenovo/x60/acpi_tables.c | 55 ---------------- src/mainboard/roda/rk886ex/acpi_tables.c | 55 ---------------- 4 files changed, 0 insertions(+), 258 deletions(-) diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index 1e8ea29..bc0a790 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -30,84 +30,13 @@ #include <arch/ioapic.h> #include "dmi.h" -#define OLD_ACPI 0 - extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif -#if OLD_ACPI -typedef struct acpi_oemb { - acpi_header_t header; - u8 ss; - u16 iost; - u32 topm; - u32 roms; - u32 mg1b; - u32 mg1l; - u32 mg2b; - u32 mg2l; - u8 rsvd; - u8 dmax; - u32 hpta; - u32 cpb0; - u32 cpb1; - u32 cpb2; - u32 cpb3; - u8 assb; - u8 aotb; - u32 aaxb; - u8 smif; - u8 dtse; - u8 dts1; - u8 dts2; - u8 mpen; -} __attribute__((packed)) acpi_oemb_t; -#endif - #include "southbridge/intel/i82801gx/nvs.h" -#if OLD_ACPI -static void acpi_create_oemb(acpi_oemb_t *oemb) -{ - acpi_header_t *header = &(oemb->header); - unsigned long tolud; - - memset (oemb, 0, sizeof(*oemb)); - - /* fill out header fields */ - memcpy(header->signature, "OEMB", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_oemb_t); - header->revision = 1; - - oemb->ss = 0x09; // ss1 + ss 4 - oemb->iost = 0x0403; // ?? - - tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); - oemb->topm = tolud; - - oemb->roms = 0xfff00000; // 1M hardcoded - - oemb->mg1b = 0x000d0000; - oemb->mg1l = 0x00010000; - - oemb->mg2b = tolud; - oemb->mg2l = 0-tolud; - - oemb->dmax = 0x87; - oemb->hpta = 0x000e36c0; - - header->checksum = - acpi_checksum((void *) oemb, sizeof(acpi_oemb_t)); - -}; -#endif - static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); @@ -202,9 +131,6 @@ unsigned long write_acpi_tables(unsigned long start) #if CONFIG_HAVE_ACPI_SLIC acpi_header_t *slic; #endif -#if OLD_ACPI - acpi_oemb_t *oemb; -#endif acpi_header_t *ssdt; acpi_header_t *dsdt; @@ -256,15 +182,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; acpi_add_table(rsdp, mcfg); -#if OLD_ACPI - printk(BIOS_DEBUG, "ACPI: * OEMB\n"); - oemb=(acpi_oemb_t *)current; - current += sizeof(acpi_oemb_t); - ALIGN_CURRENT; - acpi_create_oemb(oemb); - acpi_add_table(rsdp, oemb); -#endif - printk(BIOS_DEBUG, "ACPI: * FACS\n"); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); @@ -276,16 +193,6 @@ unsigned long write_acpi_tables(unsigned long start) current += dsdt->length; memcpy(dsdt, &AmlCode, dsdt->length); -#if OLD_ACPI - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBEEF) { - printk(BIOS_DEBUG, "ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb); - *(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb; - break; - } - } -#endif - ALIGN_CURRENT; /* Pack GNVS into the ACPI table area */ diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index d9275b5..3742c20 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -36,61 +36,6 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#define OLD_ACPI 0 -#if OLD_ACPI -static void acpi_create_gnvs(global_nvs_t *gnvs) -{ - memset (gnvs, 0, sizeof(global_nvs_t)); - - gnvs->LIDS = 1; - gnvs->PWRS = 1; - - gnvs->ACTT = 0x37; - gnvs->PSVT = 0x4f; - - gnvs->TC1V = 0x00; - gnvs->TC2V = 0x0a; - gnvs->TSPV = 0x02; - - gnvs->CRTT = 0x77; - - gnvs->B0SC = 0x54; - gnvs->APIC = 0x01; - gnvs->MPEN = 0x01; - - gnvs->PPCM = 0x02; - gnvs->PCP0 = 0xbf; - gnvs->PCP1 = 0xbf; - - gnvs->CMAP = 0x01; - gnvs->CMBP = 0x01; - gnvs->LT0 = 0x01; - gnvs->FDCP = 0x01; - gnvs->CMCP = 0x01; - gnvs->CMDP = 0x01; - gnvs->P2M = 0x02; - - gnvs->IGDS = 0x01; - - gnvs->CADL = 0x09; - gnvs->PADL = 0x09; - - gnvs->NDID = 3; - gnvs->DID1 = 0x80000100; - gnvs->DID2 = 0x80000240; - gnvs->DID3 = 0x80000410; - gnvs->DID4 = 0x80000410; - gnvs->DID5 = 0x00000005; - - gnvs->ALAF = 0x64; - gnvs->LLOW = 0x2c; - gnvs->LHIH = 0x01; - - // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); - // oemb->topm = tolud; -} -#endif - #include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index d9275b5..3742c20 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -36,61 +36,6 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#define OLD_ACPI 0 -#if OLD_ACPI -static void acpi_create_gnvs(global_nvs_t *gnvs) -{ - memset (gnvs, 0, sizeof(global_nvs_t)); - - gnvs->LIDS = 1; - gnvs->PWRS = 1; - - gnvs->ACTT = 0x37; - gnvs->PSVT = 0x4f; - - gnvs->TC1V = 0x00; - gnvs->TC2V = 0x0a; - gnvs->TSPV = 0x02; - - gnvs->CRTT = 0x77; - - gnvs->B0SC = 0x54; - gnvs->APIC = 0x01; - gnvs->MPEN = 0x01; - - gnvs->PPCM = 0x02; - gnvs->PCP0 = 0xbf; - gnvs->PCP1 = 0xbf; - - gnvs->CMAP = 0x01; - gnvs->CMBP = 0x01; - gnvs->LT0 = 0x01; - gnvs->FDCP = 0x01; - gnvs->CMCP = 0x01; - gnvs->CMDP = 0x01; - gnvs->P2M = 0x02; - - gnvs->IGDS = 0x01; - - gnvs->CADL = 0x09; - gnvs->PADL = 0x09; - - gnvs->NDID = 3; - gnvs->DID1 = 0x80000100; - gnvs->DID2 = 0x80000240; - gnvs->DID3 = 0x80000410; - gnvs->DID4 = 0x80000410; - gnvs->DID5 = 0x00000005; - - gnvs->ALAF = 0x64; - gnvs->LLOW = 0x2c; - gnvs->LHIH = 0x01; - - // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); - // oemb->topm = tolud; -} -#endif - #include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index d9275b5..3742c20 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -36,61 +36,6 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#define OLD_ACPI 0 -#if OLD_ACPI -static void acpi_create_gnvs(global_nvs_t *gnvs) -{ - memset (gnvs, 0, sizeof(global_nvs_t)); - - gnvs->LIDS = 1; - gnvs->PWRS = 1; - - gnvs->ACTT = 0x37; - gnvs->PSVT = 0x4f; - - gnvs->TC1V = 0x00; - gnvs->TC2V = 0x0a; - gnvs->TSPV = 0x02; - - gnvs->CRTT = 0x77; - - gnvs->B0SC = 0x54; - gnvs->APIC = 0x01; - gnvs->MPEN = 0x01; - - gnvs->PPCM = 0x02; - gnvs->PCP0 = 0xbf; - gnvs->PCP1 = 0xbf; - - gnvs->CMAP = 0x01; - gnvs->CMBP = 0x01; - gnvs->LT0 = 0x01; - gnvs->FDCP = 0x01; - gnvs->CMCP = 0x01; - gnvs->CMDP = 0x01; - gnvs->P2M = 0x02; - - gnvs->IGDS = 0x01; - - gnvs->CADL = 0x09; - gnvs->PADL = 0x09; - - gnvs->NDID = 3; - gnvs->DID1 = 0x80000100; - gnvs->DID2 = 0x80000240; - gnvs->DID3 = 0x80000410; - gnvs->DID4 = 0x80000410; - gnvs->DID5 = 0x00000005; - - gnvs->ALAF = 0x64; - gnvs->LLOW = 0x2c; - gnvs->LHIH = 0x01; - - // tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); - // oemb->topm = tolud; -} -#endif - #include "southbridge/intel/i82801gx/nvs.h" static void acpi_create_gnvs(global_nvs_t *gnvs) {

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Patch set updated: f8059c6 i945 GMA: restore tft brightness from cmos
by Sven Schnelle 15 Jun '11

15 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/24 -gerrit commit f8059c6546bfbed2f122c90c5a33096afedd6a02 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 12 14:30:10 2011 +0200 i945 GMA: restore tft brightness from cmos Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/devicetree.cb | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 -- src/mainboard/lenovo/x60/devicetree.cb | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 -- src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/gma.c | 13 ++++++++++++- 6 files changed, 15 insertions(+), 7 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 5419d71..73b9a9f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -21,7 +21,7 @@ ## chip northbridge/intel/i945 - + register "tft_present" = "1" device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index aa92765..252ae40 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -336,6 +336,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 42a45d1..887a6db 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -21,7 +21,7 @@ ## chip northbridge/intel/i945 - + register "tft_present" = "1" device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index c993a35..2aa506f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -338,6 +338,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 6c51394..80b4202 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -18,6 +18,7 @@ */ struct northbridge_intel_i945_config { + int tft_present; }; extern struct chip_operations northbridge_intel_i945_ops; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index a43ef25..30f8340 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -21,6 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" static void gma_func0_init(struct device *dev) { @@ -35,13 +37,22 @@ static void gma_func0_init(struct device *dev) static void gma_func1_init(struct device *dev) { + struct northbridge_intel_i945_config *config = dev->chip_info; u32 reg32; + u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); -} + + if (config && config->tft_present) { + if (!get_option(&val, "tft_brightness")) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); + } + } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) {

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Patch set updated: 686382c i945 GMA: restore tft brightness from cmos
by Sven Schnelle 15 Jun '11

15 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/24 -gerrit commit 686382c6e10ed8d78ce92e87c6496ccb55b3cc2b Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 12 14:30:10 2011 +0200 i945 GMA: restore tft brightness from cmos Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/devicetree.cb | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 -- src/mainboard/lenovo/x60/devicetree.cb | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 -- src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/gma.c | 13 ++++++++++++- 6 files changed, 15 insertions(+), 7 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 5419d71..73b9a9f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -21,7 +21,7 @@ ## chip northbridge/intel/i945 - + register "tft_present" = "1" device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index aa92765..252ae40 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -336,6 +336,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 42a45d1..887a6db 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -21,7 +21,7 @@ ## chip northbridge/intel/i945 - + register "tft_present" = "1" device lapic_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index c993a35..2aa506f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -338,6 +338,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 6c51394..80b4202 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -18,6 +18,7 @@ */ struct northbridge_intel_i945_config { + int tft_present; }; extern struct chip_operations northbridge_intel_i945_ops; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index a43ef25..9c79cda 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -21,6 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" static void gma_func0_init(struct device *dev) { @@ -35,13 +37,22 @@ static void gma_func0_init(struct device *dev) static void gma_func1_init(struct device *dev) { + struct northbridge_intel_i945_config *config = dev->chip_info; u32 reg32; + u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); -} + + if (config->tft_present) { + if (!get_option(&val, "tft_brightness")) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); + } + } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) {

1 0

Patch set updated: 412e186 i945 GMA: restore tft brightness from cmos
by Sven Schnelle 15 Jun '11

15 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/24 -gerrit commit 412e18612707f6251f933a67b31dedb0cfe7933f Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 12 14:30:10 2011 +0200 i945 GMA: restore tft brightness from cmos Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/romstage.c | 2 -- src/mainboard/lenovo/x60/romstage.c | 2 -- src/northbridge/intel/i945/gma.c | 7 +++++++ 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index aa92765..252ae40 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -336,6 +336,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index c993a35..2aa506f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -338,6 +338,4 @@ void main(unsigned long bist) pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } #endif - /* Set legacy Brightness control to full brightness */ - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index a43ef25..340ddcd 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> static void gma_func0_init(struct device *dev) { @@ -36,11 +37,17 @@ static void gma_func0_init(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; + u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + if (!get_option(&val, "tft_brightness")) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

1 0

New patch to review: bcfeb89 SMM: don't overwrite SMM memory on resume
by Sven Schnelle 15 Jun '11

15 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/34 -gerrit commit bcfeb894551d4858d301ce5a51eded851d57629e Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jun 14 20:55:54 2011 +0200 SMM: don't overwrite SMM memory on resume Overwriting the SMM Area on resume leaves us with all variables cleared out, i.e., the GNVS pointer is no longer available, which makes SMIF function calls impossible. Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/cpu/x86/smm/smihandler.c | 2 +- src/include/cpu/x86/smm.h | 1 + src/southbridge/intel/i82801gx/smi.c | 28 +++++++++++++++++++++----- src/southbridge/intel/i82801gx/smihandler.c | 7 ++++++ 4 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bdaedf8..d44a3ea 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -46,7 +46,7 @@ static int smi_obtain_lock(void) return (ret == SMI_UNLOCKED); } -static void smi_release_lock(void) +void smi_release_lock(void) { asm volatile ( "movb %1, %%al\n" diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 5605453..07a9cae 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -272,3 +272,4 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); +void smi_release_lock(void); diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 95ec112..5be2404 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -320,6 +320,16 @@ static void smm_relocate(void) static int smm_handler_copied = 0; +static int is_wakeup(void) +{ + device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); + + if (!dev0) + return 0; + + return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; +} + static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -329,13 +339,19 @@ static void smm_install(void) return; smm_handler_copied = 1; - /* enable the SMM memory window */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); - /* copy the real SMM handler */ - memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size); - wbinvd(); + /* if we're resuming from S3, the SMM code is already in place, + * so don't copy it again to keep the current SMM state */ + + if (!is_wakeup()) { + /* enable the SMM memory window */ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_OPEN | G_SMRAME | C_BASE_SEG); + + /* copy the real SMM handler */ + memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size); + wbinvd(); + } /* close the SMM memory window and enable normal SMM */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 9befbf9..434bfeb 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -328,6 +328,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } + /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore + * will never be unlocked because the next outl will switch off the CPU. + * This might open a small race between the smi_release_lock() and the outl() + * for other SMI handlers. Not sure if this could cause trouble. */ + if (slp_typ == 5) + smi_release_lock(); + /* Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen.

1 0

Patch merged into master: cb82c6b i82801gx: replace cafed00d/cafebabe by defines
by gerrit＠coreboot.org 15 Jun '11

15 Jun '11

the following patch was just integrated into master: commit cb82c6bf099b09706d88bb4b7bc9e1363bafd05e Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 15 09:26:34 2011 +0200 i82801gx: replace cafed00d/cafebabe by defines We're using '0xcafed00d' all over the code as magic for ACPI S3 resume. Let's add a define for that. Also replace 0xcafebabe by a define. Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/33 for details. -gerrit

1 0

Patch set updated: b9b5f06 sb800: move spi prefetch and fast read mode to sb bootblock.
by Patrick Georgi 15 Jun '11

15 Jun '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9 -gerrit commit b9b5f06edeabec7fe0ac60d436e507ff555f9b50 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jun 4 10:37:35 2011 -0700 sb800: move spi prefetch and fast read mode to sb bootblock. So we don't waste time on the first cbfs scan. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> [adapt persimmon with the same change, and work around romcc bug in bootblock code: it doesn't like MEMACCESS[idx] |= value;] Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997 --- src/mainboard/amd/persimmon/romstage.c | 20 ----------- src/mainboard/asrock/e350m1/romstage.c | 17 --------- src/southbridge/amd/cimx_wrapper/sb800/bootblock.c | 37 ++++++++++++++++++-- 3 files changed, 34 insertions(+), 40 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 3f2aa10..5ef5557 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -70,26 +70,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ } - // early enable of PrefetchEnSPIFromHost - if (boot_cpu()) - { - __outdword (0xcf8, 0x8000a3b8); - __outdword (0xcfc, __indword (0xcfc) | 1 << 24); - } - - // early enable of SPI 33 MHz fast mode read - if (boot_cpu()) - { - volatile u32 *spiBase = (void *) 0xa0000000; - u32 save; - __outdword (0xcf8, 0x8000a3a0); - save = __indword (0xcfc); - __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base - spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14); - spiBase [0] |= 1 << 18; // fast read enable - __outdword (0xcfc, save); // clear temp base - } - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 7d25ec1..61de9f6 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,23 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr(0xc0010062, 0); - // early enable of PrefetchEnSPIFromHost - if (boot_cpu()) { - __outdword(0xcf8, 0x8000a3b8); - __outdword(0xcfc, __indword(0xcfc) | 1 << 24); - } - // early enable of SPI 33 MHz fast mode read - if (boot_cpu()) { - volatile u32 *spiBase = (void *)0xa0000000; - u32 save; - __outdword(0xcf8, 0x8000a3a0); - save = __indword(0xcfc); - __outdword(0xcfc, (u32) spiBase | 2); // set temp MMIO base - spiBase[3] = (spiBase[3] & ~(3 << 14)) | (1 << 14); - spiBase[0] |= 1 << 18; // fast read enable - __outdword(0xcfc, save); // clear temp base - } - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c index 9d8a349..aaec03c 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c @@ -20,9 +20,9 @@ #include <arch/io.h> #include <arch/romcc_io.h> -static void sb800_enable_rom(void) +static void enable_rom(void) { - u32 word; + u16 word; u32 dword; device_t dev; @@ -56,8 +56,39 @@ static void sb800_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); } +static void enable_prefetch(void) +{ + u32 dword; + device_t dev = PCI_DEV(0, 0x14, 0x03); + + /* Enable PrefetchEnSPIFromHost */ + dword = pci_io_read_config32(dev, 0xb8); + pci_io_write_config32(dev, 0xb8, dword | (1 << 24)); +} + +static void enable_spi_fast_mode(void) +{ + u8 byte; + u32 dword; + device_t dev = PCI_DEV(0, 0x14, 0x03); + + // set temp MMIO base + volatile u32 *spi_base = (void *)0xa0000000; + u32 save = pci_io_read_config32(dev, 0xa0); + pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); + + // early enable of SPI 33 MHz fast mode read + byte = spi_base[3]; + spi_base[3] = (byte & ~(3 << 14)) | (1 << 14); + spi_base[0] = spi_base[0] | (1 << 18); // fast read enable + + pci_io_write_config32(dev, 0xa0, save); +} + static void bootblock_southbridge_init(void) { /* Setup the rom access for 2M */ - sb800_enable_rom(); + enable_rom(); + enable_prefetch(); + enable_spi_fast_mode(); }

1 0

New patch to review: 0a22fb3 i82801gx: replace cafed00d/cafebabe by defines
by Sven Schnelle 15 Jun '11

15 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/33 -gerrit

1 0

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coreboot June 2011