coreboot June 2011

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274 discussions

Patch merged into master: 69f0b38 Add SMSC SCH3114 superio register descriptions to superiotool.
by gerrit＠coreboot.org 23 Jun '11

23 Jun '11

the following patch was just integrated into master: commit 69f0b386a0ffc9a5d78818626e7ebf500a1db012 Author: Mark Norman <mpnorman(a)gmail.com> Date: Sat Jun 18 10:24:36 2011 +0930 Add SMSC SCH3114 superio register descriptions to superiotool. This has been tested on a Aaeon PFM-540I RevB PC104 SBC. Change-Id: Ie02875a1fa2d90d7cc843ce745f727312f7b7aec Signed-off-by: Mark Norman <mpnorman(a)gmail.com> See http://review.coreboot.org/43 for details. -gerrit

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Wiki update/wiki access request: E350M1 sound support verified
by Marshall Buschman 23 Jun '11

23 Jun '11

Hello: The built-in sound on the ASRock E350M1 works properly. Could someone please update the wiki page accordingly? Also, a wiki account would be nice if possible. Thank you! -Marshall Buschman

7 9

build failure: cannot move location counter backwards
by Darren Hart 23 Jun '11

23 Jun '11

I'm new to coreboot and just trying to get it to boot into qemu. I've tried using SeaBios as well as just copying "yes" to payload.elf. I updated the Makefile to use gcc 4.5 instead of the 4.4 that ships with my distribution (Ubuntu 10.10): dvhart@doubt:~/source/coreboot.svn $ gcc --version gcc (Ubuntu/Linaro 4.4.4-14ubuntu5) 4.4.5 Copyright (C) 2010 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. dvhart@doubt:~/source/coreboot.svn $ gcc-4.5 --version gcc-4.5 (Ubuntu/Linaro 4.5.1-7ubuntu2) 4.5.1 Copyright (C) 2010 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Index: Makefile =================================================================== --- Makefile (revision 6637) +++ Makefile (working copy) @@ -64,7 +64,7 @@ endif endif -HOSTCC = gcc +HOSTCC = gcc-4.5 HOSTCXX = g++ HOSTCFLAGS := -I$(srck) -I$(objk) -g HOSTCXXFLAGS := -I$(srck) -I$(objk) I followed the instructions here: http://www.coreboot.org/Build_HOWTO to configure for qemux86 with a 256K ROM. The build output and resulting failure follow. Am I doing something dumb or have I hit a legitimate bug? $ make GEN bootblock/ldscript.ld LINK bootblock.elf OBJCOPY coreboot.bootblock CC lib/memset.romstage.o CC lib/memcpy.romstage.o CC lib/memcmp.romstage.o CC lib/cbfs.romstage.o CC lib/lzma.romstage.o CC lib/uart8250.romstage.o CC console/vtxprintf.romstage.o CC console/post.romstage.o CC console/die.romstage.o GEN build.h ROMCC romstage.inc GEN romstage/crt0.S CC mainboard/emulation/qemu-x86/crt0.s CC mainboard/emulation/qemu-x86/crt0.romstage.o CC arch/x86/lib/romstage_console.romstage.o CC arch/x86/lib/cbfs_and_run.romstage.o CC southbridge/intel/i82371eb/early_pm.romstage.o CC southbridge/intel/i82371eb/early_smbus.romstage.o GEN romstage/ldscript.ld LINK coreboot.romstage CBFS coreboot.pre CC arch/x86/lib/c_start.ramstage.o CC console/uart8250_console.driver.o CC southbridge/intel/i82371eb/i82371eb.driver.o CC southbridge/intel/i82371eb/isa.driver.o CC southbridge/intel/i82371eb/ide.driver.o CC southbridge/intel/i82371eb/usb.driver.o CC southbridge/intel/i82371eb/smbus.driver.o CC southbridge/intel/i82371eb/reset.driver.o CC mainboard/emulation/qemu-x86/static.ramstage.o CC lib/memset.ramstage.o CC lib/memcpy.ramstage.o CC lib/memcmp.ramstage.o CC lib/memmove.ramstage.o CC lib/malloc.ramstage.o CC lib/delay.ramstage.o CC lib/fallback_boot.ramstage.o CC lib/compute_ip_checksum.ramstage.o CC lib/version.ramstage.o CC lib/cbfs.ramstage.o CC lib/lzma.ramstage.o CC lib/gcc.ramstage.o CC lib/clog2.ramstage.o CC lib/cbmem.ramstage.o CC lib/uart8250.ramstage.o CC boot/hardwaremain.ramstage.o CC boot/selfboot.ramstage.o CC console/printk.ramstage.o CC console/console.ramstage.o CC console/vtxprintf.ramstage.o CC console/vsprintf.ramstage.o CC console/post.ramstage.o CC console/die.ramstage.o CC devices/device.ramstage.o CC devices/root_device.ramstage.o CC devices/device_util.ramstage.o CC devices/pci_device.ramstage.o CC devices/pcix_device.ramstage.o CC devices/pciexp_device.ramstage.o CC devices/agp_device.ramstage.o CC devices/cardbus_device.ramstage.o CC devices/pnp_device.ramstage.o CC devices/pci_ops.ramstage.o CC devices/smbus_ops.ramstage.o CC devices/pci_rom.ramstage.o CC mainboard/emulation/qemu-x86/mainboard.ramstage.o CC mainboard/emulation/qemu-x86/irq_tables.ramstage.o CC mainboard/emulation/qemu-x86/northbridge.ramstage.o CC pc80/mc146818rtc.ramstage.o CC pc80/isa-dma.ramstage.o CC pc80/i8259.ramstage.o CC pc80/udelay_io.ramstage.o CC pc80/keyboard.ramstage.o CC devices/oprom/x86.ramstage.o CC devices/oprom/x86_asm.ramstage.o CC devices/oprom/x86_interrupts.ramstage.o CC arch/x86/boot/boot.ramstage.o CC arch/x86/boot/coreboot_table.ramstage.o CC arch/x86/boot/multiboot.ramstage.o CC arch/x86/boot/gdt.ramstage.o CC arch/x86/boot/tables.ramstage.o CC arch/x86/boot/pirq_routing.ramstage.o CC arch/x86/lib/cpu.ramstage.o CC arch/x86/lib/pci_ops_conf1.ramstage.o CC arch/x86/lib/pci_ops_conf2.ramstage.o CC arch/x86/lib/pci_ops_mmconf.ramstage.o CC arch/x86/lib/pci_ops_auto.ramstage.o CC arch/x86/lib/exception.ramstage.o CC pc80/vga/vga_io.ramstage.o AR coreboot.a CC coreboot_ram.o CC coreboot_ram src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards (from 0000000000118000 to 0000000000004000) collect2: ld returned 1 exit status make: *** [build/coreboot_ram] Error 1 Thanks, -- Darren Hart Intel Open Source Technology Center Yocto Project - Linux Kernel

6 9

[ANN] New code repository and development workflow
by Patrick Georgi 23 Jun '11

23 Jun '11

Dear coreboot developers, stakeholders, and enthusiasts, I'm glad to be able to announce that we moved the repository infrastructure to git and gerrit, with jenkins as supporting facility. This was done with the goal of improving the development workflow, meaning less overhead for developers when managing the patch queue. This should lead to losing fewer patch submissions. So far we used patchwork[1], but it's more maintenance work than practical given that it requires manual handling of patches that don't match the commit diff, and of patches that went through multiple iterations. While it improved the visibility of patches (and I'm thankful for that), it still posed a higher than necessary barrier to patch review. Gerrit[2] is a code review utility developed by Google which uses the distributed properties of git to provide a seamless path for patches from submission to commit. For this, git[3] is used: Gerrit uses its ability to create and tear down branches as necessary to push every contribution into its own branch. This way it's already "tracked" by the version control system without influencing the master branch. The use of git also plays well into the desire of several coreboot contributors to switch from svn to git. In addition to these changes, we also moved the build bot from our own custom build variant to a more standard Jenkins[4] installation. In addition to building commits after they are integrated on the master branch ("trunk" in SVN terminology), it's also configured to build patch submissions on gerrit as they come in. That way there's automated feedback on a patch before spending time on it. All this means that the coreboot development workflow changes considerably: 1. New SCM You will need git, so install it from your usual software distribution channels. For patch submission a gerrit account is necessary. You can register it on http://review.coreboot.org. With the account you can also review patches. The ability to merge patches to mainline will be granted by admins. ssh public keys are used for authentication. You can register them with gerrit in your user preferences at http://review.coreboot.org/#settings when logged in. Gerrit requires that the commit message contains Change-Id: lines. "make gitconfig" inside a coreboot checkout installs a commit message handler which takes care of this. The committer address must match an email address that is registered with your gerrit acccount. Again these can be configured in gerrit user preferences. Fetching anonymously: git clone http://review.coreboot.org/p/coreboot Fetching authenticated: git clone ssh://<username>@review.coreboot.org:29418/coreboot 2. New patch submission process Develop "as usual" in git, and commit freely. When you're ready to submit patches, push them with git push origin HEAD:refs/for/master This will tell gerrit which branch your commits are for (master) and it will create internal branches for each commit you pushed, making them separate changesets. If you push a number of commits at once, they're properly linked as "dependencies", so people (and tools like gerrit and jenkins) are aware about prerequisites. For automating some aspects of patch submission, see the last paragraph of http://review.coreboot.org/Documentation/user-upload.html#push_create We will also document more of making live easier at http://www.coreboot.org/Git as best practices are established. 3. New patch review process The main interface to do patch reviews is the gerrit webapp at http://review.coreboot.org. For those who tend to avoid web apps, there's the option of controlling gerrit via ssh. Detailed information on that will be posted at http://www.coreboot.org/Git. There's no real workflow defined around this interface yet because it seems to be an unpopular choice as _User_ Interface. This means, we'll have to develop our own. 4. Mail notification Mail notification to the mailing list is implemented from scratch. Right now it only reports on new patch submissions and on patches merged into the master branch. More events might/will follow in future, and we will certainly tweak the ad-hoc messages and formatting some more. Questions? Comments? Praise? Flames? Patrick [1] http://ozlabs.org/~jk/projects/patchwork [2] http://gerrit.googlecode.com [3] http://git-scm.com/ [4] http://jenkins-ci.org/

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Patch merged into master: 5d1306f T60: undock on external power loss
by gerrit＠coreboot.org 23 Jun '11

23 Jun '11

the following patch was just integrated into master: commit 5d1306f891ee5932e5526c736d888f272fe700be Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 13:43:52 2011 +0200 T60: undock on external power loss If power is unplugged/lost, we should undock the docking station. The power loss can also be caused by the fact that the user removed the thinkpad from the docking station without pressing the Undock button/hotkey first. Without undocking it on this event, the thinkpad LPC switch will still connect the Docking connector, which causes crashes when docking it again. Change-Id: I9ed783e491827bde20264868eab2b3a79c232922 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/62 for details. -gerrit

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Patch merged into master: 281d380 T60: enable userspace EC events
by gerrit＠coreboot.org 23 Jun '11

23 Jun '11

the following patch was just integrated into master: commit 281d380deb1892e682fbffc77089e505311149d1 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 13:41:55 2011 +0200 T60: enable userspace EC events EC events 0x50-0x5f are never triggered by the EC. Instead they can be generated by writing the wanted events to register 0x2a. Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/61 for details. -gerrit

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New patch to review: 5d1306f T60: undock on external power loss
by Sven Schnelle 23 Jun '11

23 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/62 -gerrit commit 5d1306f891ee5932e5526c736d888f272fe700be Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 13:43:52 2011 +0200 T60: undock on external power loss If power is unplugged/lost, we should undock the docking station. The power loss can also be caused by the fact that the user removed the thinkpad from the docking station without pressing the Undock button/hotkey first. Without undocking it on this event, the thinkpad LPC switch will still connect the Docking connector, which causes crashes when docking it again. Change-Id: I9ed783e491827bde20264868eab2b3a79c232922 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/ec/lenovo/h8/acpi/ec.asl | 3 +++ src/mainboard/lenovo/t60/acpi/dock.asl | 7 +++++++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 3ba4aa9..368afa8 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -35,6 +35,8 @@ Device(EC) HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ + Offset (0x2a), + EVNT, 8, /* write will trigger EC event */ Offset (0x3a), AMUT, 1, /* Audio Mute */ Offset (0x3B), @@ -109,6 +111,7 @@ Device(EC) Method(_Q27, 0, NotSerialized) { Notify (AC, 0x80) + Store(0x50, EVNT) } Method(_Q2A, 0, NotSerialized) diff --git a/src/mainboard/lenovo/t60/acpi/dock.asl b/src/mainboard/lenovo/t60/acpi/dock.asl index ae9d19e..ba50609 100644 --- a/src/mainboard/lenovo/t60/acpi/dock.asl +++ b/src/mainboard/lenovo/t60/acpi/dock.asl @@ -88,4 +88,11 @@ Scope(\_SB.PCI0.LPCB.EC) Notify(\_SB.DOCK, 3) } } + + Method(_Q50, 0, NotSerialized) + { + if (\_SB.DOCK._STA()) { + Notify(\_SB.DOCK, 1) + } + } }

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New patch to review: 281d380 T60: enable userspace EC events
by Sven Schnelle 23 Jun '11

23 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/61 -gerrit commit 281d380deb1892e682fbffc77089e505311149d1 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 13:41:55 2011 +0200 T60: enable userspace EC events EC events 0x50-0x5f are never triggered by the EC. Instead they can be generated by writing the wanted events to register 0x2a. Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/devicetree.cb | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 3d2d471..9d7a414 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -133,6 +133,8 @@ chip northbridge/intel/i945 register "event7_enable" = "0x01" register "event8_enable" = "0x01" register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" register "eventc_enable" = "0x3c"

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Patch merged into master: be71ad0 T60: add additional EC events
by gerrit＠coreboot.org 23 Jun '11

23 Jun '11

the following patch was just integrated into master: commit be71ad0007d8ac65b44aa8c1d544b2b95aa2fa9c Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 11:59:48 2011 +0200 T60: add additional EC events We missed a few bits, i.e the battery and some hotkey events. Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/60 for details. -gerrit

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New patch to review: be71ad0 T60: add additional EC events
by Sven Schnelle 23 Jun '11

23 Jun '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/60 -gerrit commit be71ad0007d8ac65b44aa8c1d544b2b95aa2fa9c Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 11:59:48 2011 +0200 T60: add additional EC events We missed a few bits, i.e the battery and some hotkey events. Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/devicetree.cb | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 5419d71..3d2d471 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -128,8 +128,13 @@ chip northbridge/intel/i945 register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xf4" - register "event5_enable" = "0x3c" + register "event5_enable" = "0x3f" register "event6_enable" = "0x80" + register "event7_enable" = "0x01" + register "event8_enable" = "0x01" + register "event9_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" register "eventc_enable" = "0x3c" register "wlan_enable" = "0x01"

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coreboot June 2011