June 2011 - coreboot - mail.coreboot.org

by m.vkanenburg

Hello, I have a lot of brand new commodore in-home units developed as a mediaserver under ce. The hardware is based on the intel 830M4/854 with: P3 celeron-M 600 mHz System bus 400 Mhz VGA Chipset NB: Intel 854, SB: ICH4 I would like to give these units a second live under linux but need help. Anyone interested in taking this challenge? M

8 years, 9 months

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Patch merged into master: f2674cc i82801gx: read RTC status register to prevent IRQ storm

by gerrit＠coreboot.org

the following patch was just integrated into master: commit f2674cc3d7e90ed01af8449f8786aa7f42cb84b8 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 29 15:05:28 2011 +0200 i82801gx: read RTC status register to prevent IRQ storm My Thinkpad appeared dead. After investigation, it turned out that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI handler didn't read the status register, so it was triggered again. This is a really nasty situation, as it means you have to dissemble your Notebook just to unplug the RTC battery. Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/67 for details. -gerrit

8 years, 9 months

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Patch set updated: f2674cc i82801gx: read RTC status register to prevent IRQ storm

by Sven Schnelle

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/67 -gerrit commit f2674cc3d7e90ed01af8449f8786aa7f42cb84b8 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 29 15:05:28 2011 +0200 i82801gx: read RTC status register to prevent IRQ storm My Thinkpad appeared dead. After investigation, it turned out that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI handler didn't read the status register, so it was triggered again. This is a really nasty situation, as it means you have to dissemble your Notebook just to unplug the RTC battery. Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/smihandler.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 434bfeb..48375e4 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -26,6 +26,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> +#include <pc80/mc146818rtc.h> #include "i82801gx.h" /* I945 */ @@ -410,6 +411,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) { u16 pm1_sts; + volatile u8 cmos_status; pm1_sts = reset_pm1_status(); dump_pm1_status(pm1_sts); @@ -423,6 +425,12 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ reg32 = (7 << 10) | (1 << 13); outl(reg32, pmbase + PM1_CNT); } + + if (pm1_sts & RTC_STS) { + /* read RTC status register to disable the interrupt */ + cmos_status = cmos_read(RTC_REG_C); + printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status); + } } static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)

8 years, 9 months

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New patch to review: 1b30ff6 i82801gx: read RTC status register to prevent IRQ storm

by Sven Schnelle

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/67 -gerrit commit 1b30ff69f083f2416abfa0f0977ea315368d28e6 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 29 15:05:28 2011 +0200 i82801gx: read RTC status register to prevent IRQ storm My Thinkpad appeared dead. After investigation, it turned out that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI handler didn't read the status register, so it was triggered again. This is a really nasty situation, as it means you have to dissemble your Notebook just to unplug the RTC battery. Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/smihandler.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 434bfeb..81a88d8 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -26,6 +26,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> +#include <pc80/mc146818rtc.h> #include "i82801gx.h" /* I945 */ @@ -423,6 +424,11 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ reg32 = (7 << 10) | (1 << 13); outl(reg32, pmbase + PM1_CNT); } + + if (pm1_sts & RTC_STS) { + /* read RTC status register to disable the interrupt */ + printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_read(RTC_REG_C)); + } } static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)

8 years, 9 months

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New Birthday Calendar

by Teja Kesineni

Hello Click on the link below and please enter your birthday for me. It will take less than one minute. http://www.birthdayalarm.com/bd2/85415695a423799569b1539024408c576625487d13… Thank You, Teja

8 years, 9 months

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Patch merged into master: cd3d80c Libpayload needs to clear the bss region.

by gerrit＠coreboot.org

the following patch was just integrated into master: commit cd3d80c3e6c6c4b3de63802ddab280da3c96e975 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jun 28 14:30:05 2011 -0600 Libpayload needs to clear the bss region. Libpayload shouldn't count on coreboot or other payloads to clear memory. This fixes problems with payloads being loaded after or on top of each other. Change-Id: I30303d47e465e8921f47acab667c7998ba79fca7 Signed-off-by: Marc Jones <marcj303(a)gmail.com> See http://review.coreboot.org/66 for details. -gerrit

8 years, 9 months

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Patch merged into master: d7048ee amd southbirdge sb800 wrapper, pci bridge fix

by gerrit＠coreboot.org

the following patch was just integrated into master: commit d7048ee00e4b8cfe5849c384b957aee1bb407ffc Author: Kerry She <shekairui(a)gmail.com> Date: Fri Jun 24 22:52:15 2011 +0800 amd southbirdge sb800 wrapper, pci bridge fix sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui(a)gmail.com> See http://review.coreboot.org/63 for details. -gerrit

8 years, 9 months

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Patch merged into master: 04477eb Add the AMD Torpedo mainboard

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 04477eb2537415ad18c0e28f5085204b52319bc9 Author: efdesign98 <efdesign98(a)gmail.com> Date: Mon Jun 20 21:48:37 2011 -0700 Add the AMD Torpedo mainboard The Torpedo mainboard is the reference platform for the AMD Family 12 cpus and the AMD Hudson-2 (SB900) southbridge. Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/54 for details. -gerrit

8 years, 9 months

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Patch merged into master: 024acab Addition of Family12/SB900 wrapper code

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 024acab4f0da859d05fc39ee73048dcdd10b4416 Author: efdesign98 <efdesign98(a)gmail.com> Date: Mon Jun 20 19:56:06 2011 -0700 Addition of Family12/SB900 wrapper code This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/53 for details. -gerrit

8 years, 9 months

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Patch merged into master: ee466b8 msrtool: added support for Intel CPUs

by gerrit＠coreboot.org

the following patch was just integrated into master: commit ee466b8073bca2f5c5146cde7c967095c2e4ed90 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Mon Jun 20 23:14:22 2011 +0400 msrtool: added support for Intel CPUs Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> See http://review.coreboot.org/50 for details. -gerrit

8 years, 9 months

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coreboot June 2011