New patch to review: d7048ee amd southbirdge sb800 wrapper, pci bridge fix

[Kerry She]

Kerry She ([e-mail]) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/63

-gerrit

commit d7048ee00e4b8cfe5849c384b957aee1bb407ffc
Author: Kerry She <[e-mail]>
Date:   Fri Jun 24 22:52:15 2011 +0800

    amd southbirdge sb800 wrapper, pci bridge fix
    
    sb800 pci bridge SHOULD enabled by default according to the chipset document,
    but actually not enabled on some mainboard.
    enable sb800 pci bridge when told to enable in devicetree.cb.
    tested on ibase persimmon mainboard.
    
    Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
    Signed-off-by: Kerry She <[e-mail]>
---
 src/mainboard/advansus/a785e-i/devicetree.cb |    2 +-
 src/mainboard/amd/inagua/devicetree.cb       |    2 +-
 src/mainboard/amd/persimmon/devicetree.cb    |    2 +-
 src/mainboard/asrock/e350m1/devicetree.cb    |    2 +-
 src/southbridge/amd/cimx/sb800/late.c        |   17 ++++++++++++++++-
 5 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb
index 25a1f64..79df8c9 100644
--- a/src/mainboard/advansus/a785e-i/devicetree.cb
+++ b/src/mainboard/advansus/a785e-i/devicetree.cb
@@ -98,7 +98,7 @@ chip northbridge/amd/amdfam10/root_complex
                                                         end
                                                 end     #superio/winbond/w83627hf
 					end # LPC	0x439d
-					device pci 14.4 off end # PCI	0x4384 # PCI-b conflict with GPIO.
+					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 					device pci 14.5 on end # USB 2
 					device pci 14.6 off end # Gec
 					device pci 15.0 on end # PCIe 0
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 67be34e..82658cf 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -65,7 +65,7 @@ chip northbridge/amd/agesa/family14/root_complex
                                                         end
                                                 end # kbc1100
 					end #LPC
-  					device pci 14.4 on end # PCI 0x4384
+					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 	  				device pci 14.5 on end # USB 2
 					device pci 15.0 on end # PCIe PortA
 					device pci 15.1 on end # PCIe PortB
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index a676388..3cb8d1e 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -81,7 +81,7 @@ chip northbridge/amd/agesa/family14/root_complex
 							end
                                                 end # f81865f
 					end #LPC
-  					device pci 14.4 on  end # PCI 0x4384
+					device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 	  				device pci 14.5 on  end # USB 2
 					device pci 15.0 off end # PCIe PortA
 					device pci 15.1 off end # PCIe PortB
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 5983ed2..bff8151 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -97,7 +97,7 @@ chip northbridge/amd/agesa/family14/root_complex
 							end
 						end
 					end #LPC
-  					device pci 14.4 on end # PCI 0x4384
+					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 	  				device pci 14.5 on end # USB 2
 					device pci 15.0 on  end # PCIe PortA
 					device pci 15.1 on  end # PCIe PortB: NIC
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 7367a18..b16bc50 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -248,6 +248,21 @@ static const struct pci_driver gec_driver __pci_driver = {
         .device = PCI_DEVICE_ID_ATI_SB800_GEC,
 };
 
+/**
+ * @brief Enable PCI Bridge
+ *
+ * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
+ * 'PCIDisable' set to 0 to enable P2P bridge.
+ * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
+ *              to function as GPIO {GPIO 35:0}.
+ */
+static void pci_init(device_t dev)
+{
+	/* PCI Bridge SHOULD be enabled by default according to SB800 rrg,
+	 * but actually was disabled in some platform, so I have to enabled it.
+	 */
+	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
+}
 
 static void pcie_init(device_t dev)
 {
@@ -258,7 +273,7 @@ static struct device_operations pci_ops = {
         .read_resources = pci_bus_read_resources,
         .set_resources = pci_dev_set_resources,
         .enable_resources = pci_bus_enable_resources,
-        .init = pcie_init,
+        .init = pci_init,
         .scan_bus = pci_scan_bridge,
         .reset_bus = pci_bus_reset,
         .ops_pci = &lops_pci,