coreboot December 2011

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Patch set updated for coreboot: c56b7fb Sconfig: parse Kconfig options from devicetree.cb
by Kyösti Mälkki 05 Dec '11

05 Dec '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/472 -gerrit commit c56b7fb47a0088292046d5cc2b6f4941273fb675 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 5 20:33:55 2011 +0200 Sconfig: parse Kconfig options from devicetree.cb Mainboard and chip Kconfig files have several build options that are redundant with information in devicetree.cb. This patch enables sconfig to auto-generate equivalent configuration. sconfig -s Generates mainboard's static.c file, as before. sconfig -b This operation creates mainboard's bootblock init code. By default, for every chip listed in mainboard/devicetree.cb, if there is a chip/bootblock.c file, the init function is called. A mainboard/bootblock.c file can be added to override default behaviour. sconfig -k This operation generates select -options for component paths. Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/sconfig/main.c | 173 ++++++++++++++++++++++++++++++++++++++++----------- 1 files changed, 136 insertions(+), 37 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index dab04db..181be38 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -29,6 +29,14 @@ struct header headers; static int devcount = 0; +typedef enum { + STATIC_MODE, + BOOTBLOCK_MODE, + KCONFIG_MODE +} scan_t; + +static scan_t scan_mode = STATIC_MODE; + static struct device root; static struct device mainboard = { .name = "mainboard", @@ -116,21 +124,28 @@ void postprocess_devtree(void) { } } +void translate_name(char *str, int uppercase) +{ + char *c; + for (c = str; *c; c++) { + if (*c == '/') *c = '_'; + if (*c == '-') *c = '_'; + if (uppercase) + *c = toupper(*c); + } +} + struct device *new_chip(struct device *parent, struct device *bus, char *path) { struct device *new_chip = new_dev(parent, bus); new_chip->chiph_exists = 1; new_chip->name = path; new_chip->name_underscore = strdup(new_chip->name); - char *c; - for (c = new_chip->name_underscore; *c; c++) { - if (*c == '/') *c = '_'; - if (*c == '-') *c = '_'; - } + translate_name(new_chip->name_underscore, 0); new_chip->type = chip; new_chip->chip = new_chip; struct stat st; - char *chip_h = malloc(strlen(path)+12); + char *chip_h = malloc(strlen(path)+18); sprintf(chip_h, "src/%s", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) { fprintf(stderr, "ERROR: Chip component %s does not exist.\n", @@ -138,9 +153,15 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { exit(1); } - sprintf(chip_h, "src/%s/chip.h", path); - if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) - new_chip->chiph_exists = 0; + if (scan_mode == STATIC_MODE) + sprintf(chip_h, "src/%s/chip.h", path); + else if (scan_mode == BOOTBLOCK_MODE) + sprintf(chip_h, "src/%s/bootblock.c", path); + + if ((scan_mode == STATIC_MODE) || (scan_mode == BOOTBLOCK_MODE)) { + if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) + new_chip->chiph_exists = 0; + } if (parent->latestchild) { parent->latestchild->next_sibling = new_chip; @@ -153,7 +174,7 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { } void add_header(struct device *dev) { - if (dev->chiph_exists) { + if ((dev->chiph_exists) || (scan_mode == KCONFIG_MODE)){ int include_exists = 0; struct header *h = &headers; while (h->next) { @@ -399,7 +420,8 @@ static void pass1(FILE *fil, struct device *ptr) { } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "struct %s_config %s_info_%d\t= {\n", + ptr->name_underscore, ptr->name_underscore, ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -407,7 +429,8 @@ static void pass1(FILE *fil, struct device *ptr) { } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "struct %s_config %s_info_%d;\n", + ptr->name_underscore, ptr->name_underscore, ptr->id); } } } @@ -441,22 +464,60 @@ static void inherit_subsystem_ids(FILE *file, struct device *dev) } } +static void usage(void) +{ + printf("usage: sconfig vendor/mainboard outputdir [-{s|b|k} outputfile]\n"); + printf("\t-s file\tcreate ramstage static device map\n"); + printf("\t-b file\tcreate bootblock init_mainboard()\n"); + printf("\t-k file\tcreate Kconfig devicetree section\n"); + printf("Defaults to \"-s static.c\" if no {s|b|k} specified.\n"); + exit (1); +} + + int main(int argc, char** argv) { - if (argc != 3) { - printf("usage: sconfig vendor/mainboard outputdir\n"); - return 1; - } + if (argc < 3) + usage(); + char *mainboard=argv[1]; char *outputdir=argv[2]; char *devtree=malloc(strlen(mainboard)+30); - char *outputc=malloc(strlen(outputdir)+10); sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard); - sprintf(outputc, "%s/static.c", outputdir); + char *outputc; - headers.next = malloc(sizeof(struct header)); - headers.next->name = malloc(strlen(mainboard)+12); - headers.next->next = 0; - sprintf(headers.next->name, "mainboard/%s", mainboard); + if (argc == 3) { + scan_mode = STATIC_MODE; + outputc=malloc(strlen(outputdir)+20); + sprintf(outputc, "%s/static.c", outputdir); + } else if ((argc == 5) && (argv[3][0] == '-') && (argv[3][2] == 0)) { + + switch (argv[3][1]) { + case 's': + scan_mode = STATIC_MODE; + break; + case 'b': + scan_mode = BOOTBLOCK_MODE; + break; + case 'k': + scan_mode = KCONFIG_MODE; + break; + default: + usage(); + break; + } + char *outputfile=argv[4]; + + outputc=malloc(strlen(outputdir)+strlen(outputfile)+2); + sprintf(outputc, "%s/%s", outputdir, outputfile); + } + + headers.next = 0; + if (scan_mode == STATIC_MODE) { + headers.next = malloc(sizeof(struct header)); + headers.next->name = malloc(strlen(mainboard)+12); + headers.next->next = 0; + sprintf(headers.next->name, "mainboard/%s", mainboard); + } FILE *filec = fopen(devtree, "r"); if (!filec) { @@ -479,29 +540,67 @@ int main(int argc, char** argv) { while (head->next != tmp) head = head->next; } - FILE *staticc = fopen(outputc, "w"); - if (!staticc) { + FILE *autogen = fopen(outputc, "w"); + if (!autogen) { fprintf(stderr, "Could not open file '%s' for writing: ", outputc); perror(NULL); exit(1); } - fprintf(staticc, "#include <device/device.h>\n"); - fprintf(staticc, "#include <device/pci.h>\n"); - struct header *h = &headers; - while (h->next) { - h = h->next; - fprintf(staticc, "#include \"%s/chip.h\"\n", h->name); - } + struct header *h; + if (scan_mode == STATIC_MODE) { - walk_device_tree(staticc, &root, inherit_subsystem_ids, NULL); + fprintf(autogen, "#include <device/device.h>\n"); + fprintf(autogen, "#include <device/pci.h>\n"); + h = &headers; + while (h->next) { + h = h->next; + fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); + } - fprintf(staticc, "\n/* pass 0 */\n"); - walk_device_tree(staticc, &root, pass0, NULL); - fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device *last_dev = &%s;\n", lastdev->name); - walk_device_tree(staticc, &root, pass1, NULL); + walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL); + fprintf(autogen, "\n/* pass 0 */\n"); + walk_device_tree(autogen, &root, pass0, NULL); + fprintf(autogen, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\n" + "struct device *last_dev = &%s;\n", lastdev->name); + walk_device_tree(autogen, &root, pass1, NULL); + + } else if (scan_mode == BOOTBLOCK_MODE) { + h = &headers; + while (h->next) { + h = h->next; + fprintf(autogen, "#include \"%s/bootblock.c\"\n", h->name); + } + + fprintf(autogen, "\n#if CONFIG_HAS_MAINBOARD_BOOTBLOCK\n"); + fprintf(autogen, "#include \"mainboard/%s/bootblock.c\"\n", mainboard); + fprintf(autogen, "#else\n"); + fprintf(autogen, "static unsigned long init_mainboard(int bsp_cpu)\n{\n"); + fprintf(autogen, "\tif (! bsp_cpu) return 0;\n"); + h = &headers; + while (h->next) { + h = h->next; + translate_name(h->name, 0); + fprintf(autogen, "\tinit_%s();\n", h->name); + } + + fprintf(autogen, "\treturn 0;\n}\n"); + fprintf(autogen, "#endif\n"); + + } else if (scan_mode == KCONFIG_MODE) { + fprintf(autogen, "\nconfig MAINBOARD_DIR\n\tstring\n"); + fprintf(autogen, "\tdefault %s\n", mainboard); + + fprintf(autogen, "\nconfig MAINBOARD_DEVTREE\n\tdef_bool y\n"); + h = &headers; + while (h->next) { + h = h->next; + translate_name(h->name, 1); + fprintf(autogen, "\tselect %s\n", h->name); + } + } - fclose(staticc); + fclose(autogen); return 0; }

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#182: superiotool installs man page with +x perms
by coreboot 05 Dec '11

05 Dec '11

#182: superiotool installs man page with +x perms ----------------------------+---------------------------------- Reporter: anonymous | Owner: uwe@… Type: defect | Status: new Priority: minor | Milestone: Going mainstream Component: superiotool | Keywords: Dependencies: | Patch Status: there is no patch ----------------------------+---------------------------------- simple fix: {{{ --- Makefile (revision 6637) +++ Makefile (working copy) @@ -71,7 +71,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) -m 644 $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 clean: rm -f $(PROGRAM) *.o }}} -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/182> coreboot <http://www.coreboot.org/>

1 0

Trac reminder: list of new ticket(s)
by coreboot tracker 05 Dec '11

05 Dec '11

1 0

Patch merged into coreboot/master: 1395308 Bootblock does not need a unique boot_cpu()
by gerrit＠coreboot.org 05 Dec '11

05 Dec '11

the following patch was just integrated into master: commit 13953087baa0032722a55216e02ddb568e3821a0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 19:44:45 2011 +0200 Bootblock does not need a unique boot_cpu() Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Dec 5 12:20:43 2011, giving +2 See http://review.coreboot.org/447 for details. -gerrit

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Patch merged into coreboot/master: 5c8526e RS780: print the vgainfo
by gerrit＠coreboot.org 05 Dec '11

05 Dec '11

the following patch was just integrated into master: commit 5c8526e3d32afb22644a92aa5abeb1b3a54eab1b Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Nov 27 13:43:16 2011 +0100 RS780: print the vgainfo With this commit the vgainfo is printed and looks like that on the serial console: vgainfo: ulBootUpEngineClock:50000 ulBootUpUMAClock:66700 ulBootUpSidePortClock:0 ulMinSidePortClock:0 ulSystemConfig:0 ulBootUpReqDisplayVector:0 ulOtherDisplayMisc:0 ulDDISlot1Config:0 ulDDISlot2Config:0 ucMemoryType:0 ucUMAChannelNumber:1 ucDockingPinBit:0 ucDockingPinPolarity:0 ulDockingPinCFGInfo:0 ulCPUCapInfo: 2 usNumberOfCyclesInPeriod:0 usMaxNBVoltage:0 usMinNBVoltage:0 usBootUpNBVoltage:0 ulHTLinkFreq:20000 usMinHTLinkWidth:8 usMaxHTLinkWidth:8 usUMASyncStartDelay:100 usUMADataReturnTime:300 usLinkStatusZeroTime:600 ulHighVoltageHTLinkFreq:20000 ulLowVoltageHTLinkFreq:20000 usMaxUpStreamHTLinkWidth:8 usMaxDownStreamHTLinkWidth:8 usMinUpStreamHTLinkWidth:8 usMinDownStreamHTLinkWidth:8 Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Dec 5 08:58:42 2011, giving +2 See http://review.coreboot.org/456 for details. -gerrit

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Patch set updated for coreboot: fe83213 Only BSP CPU writes CMOS in bootblock code
by Kyösti Mälkki 04 Dec '11

04 Dec '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/446 -gerrit commit fe832132024c6f48b5c0ee4c71f13eb0996c228c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 19:20:22 2011 +0200 Only BSP CPU writes CMOS in bootblock code CMOS accesses are not safe for multi-processor and only the BSP CPU should count reboots and test CMOS sanity. A questionable single byte CMOS read access from AP CPUs remains. Change-Id: I29118e33c07c0080c94abb90f703e38312c72432 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/bootblock_normal.c | 18 ++++++++++++++---- src/arch/x86/init/bootblock_simple.c | 4 ++-- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index db9d0f9..a0b7b37 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -3,18 +3,28 @@ static void main(unsigned long bist) { + unsigned long entry; + int boot_mode; + if (boot_cpu()) { bootblock_northbridge_init(); bootblock_southbridge_init(); bootblock_cpu_init(); - } #if CONFIG_USE_OPTION_TABLE - sanitize_cmos(); + sanitize_cmos(); #endif + boot_mode = do_normal_boot(); + } else { + + /* Questionable single byte read from CMOS. + * Do not add any other CMOS access in the + * bootblock for AP CPUs. + */ + boot_mode = last_boot_normal(); + } - unsigned long entry; - if (do_normal_boot()) + if (boot_mode) entry = findstage("normal/romstage"); else entry = findstage("fallback/romstage"); diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 5d7c611..41f73b4 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -6,11 +6,11 @@ static void main(unsigned long bist) bootblock_northbridge_init(); bootblock_southbridge_init(); bootblock_cpu_init(); - } #if CONFIG_USE_OPTION_TABLE - sanitize_cmos(); + sanitize_cmos(); #endif + } const char* target1 = "fallback/romstage"; unsigned long entry;

1 0

Patch set updated for coreboot: 1395308 Bootblock does not need a unique boot_cpu()
by Kyösti Mälkki 04 Dec '11

04 Dec '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/447 -gerrit commit 13953087baa0032722a55216e02ddb568e3821a0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 19:44:45 2011 +0200 Bootblock does not need a unique boot_cpu() Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/bootblock_common.h | 5 ----- src/cpu/x86/lapic/boot_cpu.c | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index 4c4a092..bd19682 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -1,9 +1,4 @@ -#if CONFIG_LOGICAL_CPUS && \ - (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) #include <cpu/x86/lapic/boot_cpu.c> -#else -#define boot_cpu(x) 1 -#endif #ifdef CONFIG_BOOTBLOCK_CPU_INIT #include CONFIG_BOOTBLOCK_CPU_INIT diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index bca73e1..87418d0 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,5 +1,6 @@ #include <cpu/x86/msr.h> +#if CONFIG_SMP static int boot_cpu(void) { int bsp; @@ -8,3 +9,7 @@ static int boot_cpu(void) bsp = !!(msr.lo & (1 << 8)); return bsp; } +#else +#define boot_cpu(x) 1 +#endif +

1 0

New patch to review for coreboot: 72e5c9e Sconfig: parse Kconfig options from devicetree.cb
by Kyösti Mälkki 04 Dec '11

04 Dec '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/472 -gerrit commit 72e5c9ebb5c55dc44b54d7382a47d0fb60b25263 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 12:46:46 2011 +0200 Sconfig: parse Kconfig options from devicetree.cb Mainboard and chip Kconfig files have several build options that are redundant with information in devicetree.cb. This patch enables sconfig to auto-generate equivalent configuration. sconfig -s Generates mainboard's static.c file, as before. sconfig -b This operation creates mainboard's bootblock init code. By default, for every chip listed in mainboard/devicetree.cb, if there is a chip/bootblock.c file, the init function is called. A mainboard/bootblock.c file can be added to override default behaviour. sconfig -k This operation generates select -options for component paths. Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/sconfig/main.c | 166 +++++++++++++++++++++++++++++++++++++++----------- 1 files changed, 129 insertions(+), 37 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index dab04db..960e6b2 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -28,6 +28,7 @@ struct device *head, *lastdev; struct header headers; static int devcount = 0; +static int scan_mode = 0; static struct device root; static struct device mainboard = { @@ -116,21 +117,28 @@ void postprocess_devtree(void) { } } +void translate_name(char *str, int uppercase) +{ + char *c; + for (c = str; *c; c++) { + if (*c == '/') *c = '_'; + if (*c == '-') *c = '_'; + if (uppercase) + *c = toupper(*c); + } +} + struct device *new_chip(struct device *parent, struct device *bus, char *path) { struct device *new_chip = new_dev(parent, bus); new_chip->chiph_exists = 1; new_chip->name = path; new_chip->name_underscore = strdup(new_chip->name); - char *c; - for (c = new_chip->name_underscore; *c; c++) { - if (*c == '/') *c = '_'; - if (*c == '-') *c = '_'; - } + translate_name(new_chip->name_underscore, 0); new_chip->type = chip; new_chip->chip = new_chip; struct stat st; - char *chip_h = malloc(strlen(path)+12); + char *chip_h = malloc(strlen(path)+18); sprintf(chip_h, "src/%s", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) { fprintf(stderr, "ERROR: Chip component %s does not exist.\n", @@ -138,10 +146,16 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { exit(1); } - sprintf(chip_h, "src/%s/chip.h", path); - if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) - new_chip->chiph_exists = 0; + if (scan_mode == 0) + sprintf(chip_h, "src/%s/chip.h", path); + else if (scan_mode == 1) + sprintf(chip_h, "src/%s/bootblock.c", path); + if ((scan_mode == 0) || (scan_mode == 1)) { + if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) + new_chip->chiph_exists = 0; + } + if (parent->latestchild) { parent->latestchild->next_sibling = new_chip; parent->latestchild->sibling = new_chip; @@ -153,7 +167,7 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { } void add_header(struct device *dev) { - if (dev->chiph_exists) { + if ((dev->chiph_exists) || (scan_mode==2)){ int include_exists = 0; struct header *h = &headers; while (h->next) { @@ -399,7 +413,8 @@ static void pass1(FILE *fil, struct device *ptr) { } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { - fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "struct %s_config %s_info_%d\t= {\n", + ptr->name_underscore, ptr->name_underscore, ptr->id); struct reg *r = ptr->reg; while (r) { fprintf(fil, "\t.%s = %s,\n", r->key, r->value); @@ -407,7 +422,8 @@ static void pass1(FILE *fil, struct device *ptr) { } fprintf(fil, "};\n\n"); } else { - fprintf(fil, "struct %s_config %s_info_%d;\n", ptr->name_underscore, ptr->name_underscore, ptr->id); + fprintf(fil, "struct %s_config %s_info_%d;\n", + ptr->name_underscore, ptr->name_underscore, ptr->id); } } } @@ -441,23 +457,61 @@ static void inherit_subsystem_ids(FILE *file, struct device *dev) } } +static void usage(void) +{ + printf("usage: sconfig vendor/mainboard outputdir [-{s|b|k} outputfile]\n"); + printf("\t-s file\tcreate ramstage static device map\n"); + printf("\t-b file\tcreate bootblock init_mainboard()\n"); + printf("\t-k file\tcreate Kconfig devicetree section\n"); + printf("\nDefaults to \"-s static.c\" if no {s|b|k} specified.\n"); + exit (1); +} + + int main(int argc, char** argv) { - if (argc != 3) { - printf("usage: sconfig vendor/mainboard outputdir\n"); - return 1; - } + if (argc < 3) + usage(); + char *mainboard=argv[1]; char *outputdir=argv[2]; char *devtree=malloc(strlen(mainboard)+30); - char *outputc=malloc(strlen(outputdir)+10); sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard); - sprintf(outputc, "%s/static.c", outputdir); + char *outputc; + + if (argc == 3) { + scan_mode = 0; + outputc=malloc(strlen(outputdir)+20); + sprintf(outputc, "%s/static.c", outputdir); + } else if ((argc == 5) && (argv[3][0] == '-') && (argv[3][2] == 0)) { + + switch (argv[3][1]) { + case 's': + scan_mode = 0; + break; + case 'b': + scan_mode = 1; + break; + case 'k': + scan_mode = 2; + break; + default: + usage(); + break; + } + char *outputfile=argv[4]; - headers.next = malloc(sizeof(struct header)); - headers.next->name = malloc(strlen(mainboard)+12); - headers.next->next = 0; - sprintf(headers.next->name, "mainboard/%s", mainboard); + outputc=malloc(strlen(outputdir)+strlen(outputfile)+2); + sprintf(outputc, "%s/%s", outputdir, outputfile); + } + headers.next = 0; + if (scan_mode == 0) { + headers.next = malloc(sizeof(struct header)); + headers.next->name = malloc(strlen(mainboard)+12); + headers.next->next = 0; + sprintf(headers.next->name, "mainboard/%s", mainboard); + } + FILE *filec = fopen(devtree, "r"); if (!filec) { fprintf(stderr, "Could not open file '%s' for reading: ", devtree); @@ -479,29 +533,67 @@ int main(int argc, char** argv) { while (head->next != tmp) head = head->next; } - FILE *staticc = fopen(outputc, "w"); - if (!staticc) { + FILE *autogen = fopen(outputc, "w"); + if (!autogen) { fprintf(stderr, "Could not open file '%s' for writing: ", outputc); perror(NULL); exit(1); } - fprintf(staticc, "#include <device/device.h>\n"); - fprintf(staticc, "#include <device/pci.h>\n"); - struct header *h = &headers; - while (h->next) { - h = h->next; - fprintf(staticc, "#include \"%s/chip.h\"\n", h->name); - } + struct header *h; + if (scan_mode == 0) { + + fprintf(autogen, "#include <device/device.h>\n"); + fprintf(autogen, "#include <device/pci.h>\n"); + h = &headers; + while (h->next) { + h = h->next; + fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); + } + + walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL); + fprintf(autogen, "\n/* pass 0 */\n"); + walk_device_tree(autogen, &root, pass0, NULL); + fprintf(autogen, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\n" + "struct device *last_dev = &%s;\n", lastdev->name); + walk_device_tree(autogen, &root, pass1, NULL); + + } else if (scan_mode == 1) { + h = &headers; + while (h->next) { + h = h->next; + fprintf(autogen, "#include \"%s/bootblock.c\"\n", h->name); + } - walk_device_tree(staticc, &root, inherit_subsystem_ids, NULL); + fprintf(autogen, "\n#if CONFIG_HAS_MAINBOARD_BOOTBLOCK\n"); + fprintf(autogen, "#include \"mainboard/%s/bootblock.c\"\n", mainboard); + fprintf(autogen, "#else\n"); + fprintf(autogen, "static unsigned long init_mainboard(int bsp_cpu)\n{\n"); + fprintf(autogen, "\tif (! bsp_cpu) return 0;\n"); + h = &headers; + while (h->next) { + h = h->next; + translate_name(h->name, 0); + fprintf(autogen, "\tinit_%s();\n", h->name); + } + + fprintf(autogen, "\treturn 0;\n}\n"); + fprintf(autogen, "#endif\n"); - fprintf(staticc, "\n/* pass 0 */\n"); - walk_device_tree(staticc, &root, pass0, NULL); - fprintf(staticc, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\nstruct device *last_dev = &%s;\n", lastdev->name); - walk_device_tree(staticc, &root, pass1, NULL); + } else if (scan_mode == 2) { + fprintf(autogen, "\nconfig MAINBOARD_DIR\n\tstring\n"); + fprintf(autogen, "\tdefault %s\n", mainboard); + + fprintf(autogen, "\nconfig MAINBOARD_DEVTREE\n\tdef_bool y\n"); + h = &headers; + while (h->next) { + h = h->next; + translate_name(h->name, 1); + fprintf(autogen, "\tselect %s\n", h->name); + } + } - fclose(staticc); + fclose(autogen); return 0; }

1 0

New patch to review for coreboot: 5500248 Auto-generate bootblock initialisation
by Kyösti Mälkki 04 Dec '11

04 Dec '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473 -gerrit commit 5500248a5ce26e616a77e9632e469413604a382c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 21:35:38 2011 +0200 Auto-generate bootblock initialisation The following chip-specific functions were renamed to include chip name in the function: - bootblock_northbridge_init - bootblock_southbridge_init The following no-operation bootblock.c files were removed: - northbridge/amd/agesa/family10/bootblock.c - northbridge/amd/agesa/family12/bootblock.c - northbridge/amd/agesa/family14/bootblock.c A new init function called from bootblock is declared as: - unsigned long init_mainboard(int bsp_cpu) For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock calls init_mainboard(false). Usually AP CPU has nothing to do here. By default, build toolchain creates and includes an init_mainboard() function in file build/mainboard/x/x/bootblock_autogen.h that executes init functions from any bootblock.c files for all chips listed in mainboard/devtree.cb. Alternatively a mainboard/x/x/bootblock.c file is added in the bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set. One should copy the auto-generated init_mainboard() to this file, and optionally read various bootstrap signals or status bits from super-io and southbridge component to gain some control over the selection of romstage to boot via the return value. Samples of such (yet not implemented) controls for boot behaviour: - Reset CMOS to defaults on user request (jumper). - Use fallback prefix after power-button 4s override. - Refuse boot after intruder detection. - On remote wakeup, request network boot. Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Kconfig | 7 +---- src/arch/x86/Makefile.inc | 9 +++++- src/arch/x86/include/bootblock_common.h | 17 +------------- src/arch/x86/init/bootblock_normal.c | 12 +++++----- src/arch/x86/init/bootblock_simple.c | 10 ++++---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +--- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 10 +++++++- src/northbridge/amd/agesa/family10/Kconfig | 3 -- src/northbridge/amd/agesa/family10/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family12/Kconfig | 4 --- src/northbridge/amd/agesa/family12/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family14/Kconfig | 4 --- src/northbridge/amd/agesa/family14/bootblock.c | 29 ------------------------ src/northbridge/amd/amdfam10/Kconfig | 4 --- src/northbridge/amd/amdfam10/bootblock.c | 2 +- src/northbridge/amd/amdk8/Kconfig | 4 --- src/northbridge/amd/amdk8/bootblock.c | 2 +- src/southbridge/amd/amd8111/Kconfig | 4 --- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 3 -- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb900/Kconfig | 3 -- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/Kconfig | 3 -- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/Kconfig | 5 ---- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/Kconfig | 5 ---- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/Kconfig | 4 --- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/i82371eb/Kconfig | 5 ---- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/Kconfig | 5 ---- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/nvidia/ck804/Kconfig | 4 --- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/Kconfig | 4 --- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/Kconfig | 5 +--- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/Kconfig | 4 --- src/southbridge/via/vt8237r/bootblock.c | 2 +- 43 files changed, 47 insertions(+), 213 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..07ad95f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -67,8 +67,8 @@ config PC80_SYSTEM bool default y -config BOOTBLOCK_NORTHBRIDGE_INIT - string +config HAS_MAINBOARD_BOOTBLOCK + def_bool n config HAVE_CMOS_DEFAULT def_bool n @@ -77,9 +77,6 @@ config CMOS_DEFAULT_FILE string depends on HAVE_CMOS_DEFAULT -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - config BIG_ENDIAN bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7bba44e..2595595 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -331,11 +331,16 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ + $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) -I$(@D) $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig + @printf " SCONFIG $(subst $(src)/,,$(<)) (bootblock)\n" + mkdir -p $(@D) + $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(@D) -b $(@F) $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index bd19682..69ab22c 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -1,22 +1,7 @@ #include <cpu/x86/lapic/boot_cpu.c> -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#else -static void bootblock_cpu_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif - #include <arch/cbfs.h> +#include "bootblock_autogen.h" #if CONFIG_USE_OPTION_TABLE #include <pc80/mc146818rtc.h> diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index a0b7b37..48b4131 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -4,19 +4,19 @@ static void main(unsigned long bist) { unsigned long entry; + int bsp_cpu = boot_cpu(); int boot_mode; - - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); + + if (bsp_cpu) { #if CONFIG_USE_OPTION_TABLE sanitize_cmos(); #endif boot_mode = do_normal_boot(); } else { - + /* Questionable single byte read from CMOS. * Do not add any other CMOS access in the * bootblock for AP CPUs. diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 41f73b4..f4e4bbf 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -2,15 +2,15 @@ static void main(unsigned long bist) { - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + int bsp_cpu = boot_cpu(); + + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); #if CONFIG_USE_OPTION_TABLE + if (bsp_cpu) sanitize_cmos(); #endif - } const char* target1 = "fallback/romstage"; unsigned long entry; diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index e3dbf6b..b8a25d8 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_HARD_RESET + select HAS_MAINBOARD_BOOTBLOCK select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO @@ -91,10 +92,6 @@ config HEAP_SIZE hex default 0xc0000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "mainboard/hp/dl165_g6_fam10/bootblock.c" - config MMCONF_SUPPORT_DEFAULT bool default y diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 2c56c4c..e7c0680 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev) #define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) +/* FIXME: This appears to be a super-io initialisation, + * placed in the mainboard directory. + */ void shc4307_init(void) { shc4307_enter_ext_func_mode(CMOS_DEV); @@ -43,6 +46,11 @@ void shc4307_init(void) shc4307_exit_ext_func_mode(CMOS_DEV); } -static void bootblock_southbridge_init(void) { +static unsigned long init_mainboard(int bsp_cpu) +{ + if (!bsp_cpu) return 0; + init_northbridge_amd_amdfam10(); + //init_southbridge_broadcom_bcm5785(); shc4307_init(); + return 0; } diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig index 62a6cd4..0bb16d9 100755 --- a/src/northbridge/amd/agesa/family10/Kconfig +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family10/bootblock.c" endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 source "src/northbridge/amd/agesa/family10/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family10/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index fc3c436..8ab5de8 100755 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -73,7 +73,3 @@ if DIMM_DDR3 endif endif -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family12/bootblock.c" - depends on NORTHBRIDGE_AMD_AGESA_FAMILY12 diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family12/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 44f93c1..e462153 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -39,8 +39,4 @@ config MMCONF_BUS_NUMBER int default 16 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family14/bootblock.c" - endif diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family14/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 74e0ff4..a1594ad 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -59,10 +59,6 @@ config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 612004a..328e9ad 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -3,7 +3,7 @@ #include <device/pci_def.h> #include "northbridge/amd/amdfam10/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdfam10(void) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..418c734 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,10 +45,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdk8/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c index b5395bb..8afd507 100644 --- a/src/northbridge/amd/amdk8/bootblock.c +++ b/src/northbridge/amd/amdk8/bootblock.c @@ -3,6 +3,6 @@ #include <device/pci_def.h> #include "northbridge/amd/amdk8/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdk8(void) { enumerate_ht_chain(); } diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index 83fb8fc..4367017 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -21,7 +21,3 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/amd8111/bootblock.c" - depends on SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 3009c0b..d4660de 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -41,7 +41,7 @@ static void amd8111_enable_rom(void) pci_io_write_config8(dev, 0x43, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_amd8111(void) { amd8111_enable_rom(); } diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 79624e0..fc15c42 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB800 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb800/bootblock.c" config ENABLE_IDE_COMBINED_MODE bool "Enable SATA IDE combined mode" diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..9e00219 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -104,7 +104,7 @@ static void enable_clocks(void) *acpi_mmio = reg32; } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb800(void) { /* Setup the rom access for 2M */ enable_rom(); diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 253d73f..09edd1b 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -49,8 +49,5 @@ config ACPI_SCI_IRQ help Set SCI IRQ to 9. -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" endif #SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index e84743b..f3b53d0 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -90,7 +90,7 @@ static void sb900_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb900(void) { /* Setup the rom access for 2M */ sb900_enable_rom(); diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 07028a0..79715d7 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -23,9 +23,6 @@ config SOUTHBRIDGE_AMD_SB600 select HAVE_USBDEBUG if SOUTHBRIDGE_AMD_SB600 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb600/bootblock.c" config EHCI_BAR hex diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index 7007622..db9052e 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -64,7 +64,7 @@ static void sb600_enable_rom(void) pci_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb600(void) { sb600_enable_rom(); } diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 98b8e2a..02ffdca 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -27,11 +27,6 @@ config SOUTHBRIDGE_AMD_SP5100 select IOAPIC select HAVE_USBDEBUG -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb700/bootblock.c" - depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) - config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 377bffc..a2a2653 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -64,7 +64,7 @@ static void sb700_enable_rom(void) pci_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb700(void) { sb700_enable_rom(); } diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 67cb8ef..075e454 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -22,11 +22,6 @@ config SOUTHBRIDGE_AMD_SB800 select IOAPIC select HAVE_USBDEBUG -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb800/bootblock.c" - depends on SOUTHBRIDGE_AMD_SB800 - config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 18eae24..9f7c2c2 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -62,7 +62,7 @@ static void sb800_enable_rom(void) pci_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb800(void) { sb800_enable_rom(); } diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig index d72afd8..286c19b 100644 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ b/src/southbridge/broadcom/bcm5785/Kconfig @@ -2,7 +2,3 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/broadcom/bcm5785/bootblock.c" - depends on SOUTHBRIDGE_BROADCOM_BCM5785 diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index cadda53..e1e5f31 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void) pci_write_config8(dev, 0x41, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_broadcom_bcm5785(void) { bcm5785_enable_rom(); } diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 7e5109a..a5c5eb8 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -2,8 +2,3 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82371eb/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82371EB - diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 07fa0bc..a875723 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void) pci_write_config16(dev, XBCS, reg16); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82371eb(void) { i82371eb_enable_rom(); } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a6bd202..f63c12f 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -38,10 +38,5 @@ config USBDEBUG_DEFAULT_PORT int default 1 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801gx/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82801GX - endif diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 39b0bd4..a0f73b3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -33,7 +33,7 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82801gx(void) { enable_spi_prefetch(); } diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 88ab7ff..01cff02 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -6,10 +6,6 @@ config SOUTHBRIDGE_NVIDIA_CK804 if SOUTHBRIDGE_NVIDIA_CK804 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/ck804/bootblock.c" - config ID_SECTION_OFFSET hex default 0x80 diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 29c10c8..3175606 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -42,7 +42,7 @@ static void ck804_enable_rom(void) pci_write_config8(addr, 0x88, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_ck804(void) { ck804_enable_rom(); } diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index adca4bd..78a1f25 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -5,10 +5,6 @@ config SOUTHBRIDGE_NVIDIA_MCP55 if SOUTHBRIDGE_NVIDIA_MCP55 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/mcp55/bootblock.c" - config ID_SECTION_OFFSET hex default 0x80 diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index affb025..6fb6dbb 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -53,7 +53,7 @@ static void mcp55_enable_rom(void) pci_write_config16(addr, 0x90, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_mcp55(void) { mcp55_enable_rom(); } diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 909a741..da089d3 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -3,10 +3,6 @@ config SOUTHBRIDGE_SIS_SIS966 select IOAPIC select HAVE_USBDEBUG -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 - config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_SIS_SIS966 @@ -18,3 +14,4 @@ config EHCI_BAR config EHCI_DEBUG_OFFSET hex default 0x98 if SOUTHBRIDGE_SIS_SIS966 + diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index 1ff3cda..45ab81b 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -41,7 +41,7 @@ static void sis966_enable_rom(void) pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11); } -static void bootblock_southbridge_init(void) +static void init_southbridge_sis_sis966(void) { sis966_enable_rom(); } diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..9aa1b97 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -27,7 +27,3 @@ config EPIA_VT8237R_INIT default n depends on SOUTHBRIDGE_VIA_VT8237R -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/via/vt8237r/bootblock.c" - depends on SOUTHBRIDGE_VIA_VT8237R diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 8df37aa..0ca0533 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include <device/pci_ids.h> -static void bootblock_southbridge_init(void) +static void init_southbridge_via_vt8237r(void) { device_t dev; /* don't walk other busses, HT is not enabled */

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Patch set updated for coreboot: cfcf2d3 i82801gx: Support power-on-after-power-fail better
by Patrick Georgi 03 Dec '11

03 Dec '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/444 -gerrit commit cfcf2d38858078e74ff6d0e34323f1da71a0fe1f Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 22 10:52:43 2011 +0100 i82801gx: Support power-on-after-power-fail better Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/southbridge/intel/i82801gx/smihandler.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 5cc25e7..401c9ad 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -316,16 +316,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outl(0, pmbase + GPE0_EN); - /* Should we keep the power state after a power loss? - * In case the setting is "ON" or "OFF" we don't have - * to do anything. But if it's "KEEP" we have to switch - * to "OFF" before entering S5. + /* Always set the flag in case CMOS was changed on runtime. For + * "KEEP", switch to "OFF" - KEEP is software emulated */ - if (s5pwr == MAINBOARD_POWER_KEEP) { - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if (s5pwr == MAINBOARD_POWER_ON) { + reg8 &= ~1; + } else { reg8 |= 1; - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); } + pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0);

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coreboot December 2011