coreboot December 2011

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Patch merged into coreboot/master: 2797390 implement usb2 termination and dpll delay setting for vt8237r
by gerrit＠coreboot.org 02 Dec '11

02 Dec '11

the following patch was just integrated into master: commit 2797390a25514005e59daa6a79b7acaf123f5946 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> Build-Tested: build bot (Jenkins) at Wed Nov 23 19:56:27 2011, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Fri Dec 2 23:06:19 2011, giving +2 See http://review.coreboot.org/385 for details. -gerrit

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Patch merged into coreboot/master: ed0ebd2 i3100: Add HAVE_HARD_RESET
by gerrit＠coreboot.org 02 Dec '11

02 Dec '11

the following patch was just integrated into master: commit ed0ebd28ba3fcda086dad49b21cf34e97caba310 Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Dec 2 16:33:30 2011 +0100 i3100: Add HAVE_HARD_RESET and remove it from mainboard/intel/mtarvon, as this function is implemented in the southbridge code. Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Dec 2 18:10:51 2011, giving +2 See http://review.coreboot.org/469 for details. -gerrit

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Patch merged into coreboot/master: 8bb1751 Mirror Fix coreinfo usage of cb_info
by gerrit＠coreboot.org 02 Dec '11

02 Dec '11

the following patch was just integrated into master: commit 8bb17510476ea1abaf941d443771fc95a2e849e3 Author: QingPei Wang <wangqingpei(a)gmail.com> Date: Tue Nov 22 15:24:12 2011 +0800 Mirror Fix coreinfo usage of cb_info fix cb_info.serial.ioport to cb_info.serial.baseaddr Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47 Signed-off-by: QingPei Wang <wangqingpei(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Dec 2 17:29:13 2011, giving +2 See http://review.coreboot.org/441 for details. -gerrit

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Patch merged into coreboot/master: 4211f0c M4A785T-M: fix ACPI's P-States Table
by gerrit＠coreboot.org 02 Dec '11

02 Dec '11

the following patch was just integrated into master: commit 4211f0c5542743e251dbd022b023d0d34d8877c2 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Nov 27 22:04:02 2011 +0100 M4A785T-M: fix ACPI's P-States Table Without that fix the linux kernel cannot change the frequency of the CPUs with cpufreq. Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Dec 2 17:27:13 2011, giving +2 See http://review.coreboot.org/458 for details. -gerrit

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Patch merged into coreboot/master: 47e054a Add ASUS M4A785T-M mainboard support
by gerrit＠coreboot.org 02 Dec '11

02 Dec '11

the following patch was just integrated into master: commit 47e054a1c4090e4a5a404de427634b260e4c4d13 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Nov 27 15:58:38 2011 +0100 Add ASUS M4A785T-M mainboard support This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init This change was tested with the Trisquel 5.0 GNU/Linux distribution which uses the linux-libre version 2.6.38-12-generic The mainboard boots fine, however some special care is required for the onboard sound CODEC, and the onboard video chip: * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue is the same than the ASUS M4A785-M mainboard: It causes a flood of interupts which prevents booting * The internal video chip currently requires pci=nocrs, else the graphics are frozen as soon as the radeon module loads, and dmesg would print the following(the card only has 256M, and the mainboard was equiped with 2G of RAM): [ 3.674762] [drm] radeon: 3584M of VRAM memory ready [ 3.679863] [drm] radeon: 512M of GTT memory ready. instead of : [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. * The screen(both VGA and HDMI) flickers at high resolution * Sometimes the computer freeze while changing the resolution (even the serial console stops responding) The following peripherals were tested: * The ath9k PCI wireless card was tested * The SATA hard disk works fine * the USB keyboard and mouse work fine * htop see 2 cores * serial port works under coreboot and GNU/Linux * power off and reboot works CPU frequency cannot be changed yet, this is addressed in a new commit. More detail are available here: http://www.coreboot.org/ASUS_M4A785T-M dmesg is available here: http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html The mailing list thread on the graphic problem is here: http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Dec 2 17:27:51 2011, giving +2 See http://review.coreboot.org/457 for details. -gerrit

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Patch merged into coreboot/master: 41d6529 Remove obsolete TINY_BOOTBLOCK
by gerrit＠coreboot.org 02 Dec '11

02 Dec '11

the following patch was just integrated into master: commit 41d65299b1359caddcf8944adc009cf33989febc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 18:05:46 2011 +0200 Remove obsolete TINY_BOOTBLOCK Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Dec 2 17:26:18 2011, giving +2 See http://review.coreboot.org/470 for details. -gerrit

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New patch to review for coreboot: 41d6529 Remove obsolete TINY_BOOTBLOCK
by Kyösti Mälkki 02 Dec '11

02 Dec '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/470 -gerrit commit 41d65299b1359caddcf8944adc009cf33989febc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 18:05:46 2011 +0200 Remove obsolete TINY_BOOTBLOCK Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/asus/m5a88-v/Kconfig | 1 - 3 files changed, 0 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 3828054..fb41cec 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -40,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - select TINY_BOOTBLOCK select GFXUMA select UDELAY_LAPIC diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index db0d1e4..194a39d 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -40,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - select TINY_BOOTBLOCK select GFXUMA select UDELAY_LAPIC diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index fdf2ba6..9cadcde 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select HAVE_DEBUG_CAR select SET_FIDVID

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New patch to review for coreboot: ed0ebd2 i3100: Add HAVE_HARD_RESET
by Sven Schnelle 02 Dec '11

02 Dec '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/469 -gerrit commit ed0ebd28ba3fcda086dad49b21cf34e97caba310 Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Dec 2 16:33:30 2011 +0100 i3100: Add HAVE_HARD_RESET and remove it from mainboard/intel/mtarvon, as this function is implemented in the southbridge code. Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/intel/mtarvon/Kconfig | 1 - src/southbridge/intel/i3100/Kconfig | 1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig index 76477b0..af40cad 100644 --- a/src/mainboard/intel/mtarvon/Kconfig +++ b/src/mainboard/intel/mtarvon/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 select SUPERIO_INTEL_I3100 - select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select UDELAY_TSC diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig index bcb282d..f2b7923 100644 --- a/src/southbridge/intel/i3100/Kconfig +++ b/src/southbridge/intel/i3100/Kconfig @@ -1,3 +1,4 @@ config SOUTHBRIDGE_INTEL_I3100 bool select IOAPIC + select HAVE_HARD_RESET

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Patch merged into coreboot/master: 6a8d16b Change AMD vendorcode build
by gerrit＠coreboot.org 02 Dec '11

02 Dec '11

the following patch was just integrated into master: commit 6a8d16bdd456c70329cf46d03daf2a99bbff1e81 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 17:49:43 2011 +0200 Change AMD vendorcode build Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Dec 2 08:59:26 2011, giving +2 See http://review.coreboot.org/468 for details. -gerrit

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Re: [coreboot] Add password protection
by Niklas Cholmkvist 01 Dec '11

01 Dec '11

Hi Fred, > Add password protection so you need password for boot the system. > Add it to SeaBIOS too. I don't know if it is already implemented. Will you help us implement it? -- Niklas Cholmkvist Public GPG/PGP key block ID: 1024D/C09E670B Fingerprint: 8487 ECE3 8ED9 870B BB56 95E7 9AD2 946A C09E 670B Key download: https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc [For authenticity and privacy on the internet with prime number based mathematics]

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coreboot December 2011