coreboot October 2011

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New patch to review for coreboot: f8c69e7 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/249 -gerrit commit f8c69e73c88ac79b88c204d19544e08fef3fd80f Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 18:20:35 2011 +0800 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION SB800 RAID ROM require to put the misc ROM to specific position, this patch enable user to put the RAID misc ROM to the right place in the coreboot image. Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 9 +++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 1 + 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 17ff3f9..41a167a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -111,6 +111,15 @@ config RAID_MISC_ROM_FILE default "site-local/sb800/misc.bin" depends on SB800_SATA_RAID +config RAID_MISC_ROM_POSITION + hex "RAID Misc ROM Position" + default 0xFFF00000 + depends on SB800_SATA_RAID + help + RAID ROM require to put the misc ROM at range from 0xFFF0_0000 to + 0xFFF0_FFFF, and must 1K bytes aligned. + So CONFIG_ROM_SIZE must larger than 0x100000. + endif endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30c0d39..48b198d 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -48,5 +48,6 @@ ifeq ($(CONFIG_SB800_SATA_RAID), y) cbfs-files-y += raid/misc.bin raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE)) + raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION) raid/misc.bin-type := raw endif

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New patch to review for coreboot: 96e55ec SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/248 -gerrit commit 96e55eccb38c6e70a5543a4b7610fa3588168655 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 18:20:33 2011 +0800 SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode In order to make sure AHCI/RAID ROM works correctly For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should enable bus master and the ahci also should be enabled. Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/include/device/pci_ids.h | 1 + src/southbridge/amd/cimx/sb800/late.c | 56 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 2 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 390a42a..d16f85e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -15,6 +15,7 @@ #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_SATA 0x0106 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_BASE_CLASS_NETWORK 0x02 diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b78f1ce..7811c25 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -74,6 +74,47 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config) return ret; } +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ + +#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ +void ahci_raid_init(struct device *dev) +{ + u8 irq = 0; + u32 bar5, caps, ports, val; + + val = pci_read_config16(dev, PCI_CLASS_DEVICE); + if (val == PCI_CLASS_STORAGE_SATA) { + printk(BIOS_DEBUG, "AHCI controller "); + } else if (val == PCI_CLASS_STORAGE_RAID) { + printk(BIOS_DEBUG, "RAID controller "); + } else { + printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); + return; + } + + irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); + bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); + + caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = (caps & 0x1F) + 1; + ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); + + //dev->command = pci_read_config8(dev, PCI_COMMAND); + dev->command |= PCI_COMMAND_MASTER; + pci_write_config8(dev, PCI_COMMAND, dev->command); + + /* make sure ahci is enabled */ + val = *(volatile u32 *)(bar5 + HOST_CTL); + if (!(val & HOST_CTL_AHCI_EN)) { + *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + } + printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); +} static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, @@ -98,17 +139,28 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = ahci_raid_init, .scan_bus = 0, .ops_pci = &lops_pci, }; -static const struct pci_driver sata_driver __pci_driver = { +static const struct pci_driver ahci_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, }; +static const struct pci_driver raid_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, +}; +static const struct pci_driver raid5_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, +}; + #if CONFIG_USBDEBUG == 1 static void usb_set_resources(struct device *dev) {

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Patch merged into coreboot/master: 9a43592 Don't do a call as the first instruction in libpayload.
by gerrit＠coreboot.org 11 Oct '11

11 Oct '11

the following patch was just integrated into master: commit 9a4359203d961e591e8f3dfe32045608117c918a Author: Marc Jones <marcj303(a)gmail.com> Date: Thu Oct 6 16:38:35 2011 -0600 Don't do a call as the first instruction in libpayload. Doing a call before the payload has set up its stack is risky. The stack may not be in a favorable location. Normally this is not an issue with coreboot or other well behaved callers. Change-Id: Ie6f6748a471324b29ebad045c807dfc9f4b92034 Signed-off-by: Marc Jones <marcj303(a)gmail.com> See http://review.coreboot.org/240 for details. -gerrit

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Re: [coreboot] [RFC] Tracking run tested coreboot revisions for boards
by Cristian Măgherușan-Stanciu 11 Oct '11

11 Oct '11

Hi, I also advocate a wiki but created automatically, like by a new script from utils. I think flashrom's supported hardware wiki page is a good example on how that could be done. This script could open up a file in a text editor where one could check everything that works or not for this particular build, then the script would generate a table similar to those we have in most motherboard wikis, also including further details such as current Git tag, upload the current content of the config file, and so on. The text file would be stored in the current motherboard's directory, so it would be persistent. Further on, the script could be enhanced to use mediawiki APIs to upload/update the wiki page of that motherboard and maybe even to add it to the mainboard support wiki. What do you guys think? Cristi On Tue, Oct 11, 2011 at 8:27 AM, Marc Jones <marcj303(a)gmail.com> wrote: > On Sat, Oct 8, 2011 at 2:50 AM, Paul Menzel > <paulepanter(a)users.sourceforge.net> wrote: >> Dear coreboot folks, >> >> >> on IRC Rudolf mentioned that the A8V SE [1] works with the latest >> revision of coreboot and he asked if there is a way to tag that in the >> repository. >> >> There are several ways to accomplish that but all seem to have down >> sides. >> >> 1. Git tags. We could use `git tag <board name> <commit>` and interested >> folks could then do `git tag | grep <board name>` to find tested >> revisions. Peter wrote, that Git tags could slow down the repository and >> that only finitely many tags can be used. Would the last point be a >> problem for us? >> >> 2. Git notes. Peter suggested also to use Git notes. But Rudolf wrote he >> finds it difficult to handle. >> >> 3. Wiki. We could use the Wiki by either adding tested revisions to the >> corresponding board pages or by creating a new page with a table. The >> first solution is not feasible because not all boards have their own >> page. Patrick wrote that using the Wiki often it gets out of date pretty >> quickly. Although in this case I think that would not be a huge problem >> considering that the noted revision actually was tested. Additionally >> not a lot of developers are comfortable using the Wiki. OpenEmbedded >> once did something like that [2]. >> >> 4. Provide tested images. In addition to specifying the revision such >> tested images could be uploaded somewhere so users would not have to >> build it themselves. This would not work though, since the >> infrastructure is not in place and we have to be careful with images >> containing option roms(?). >> >> 5. ROM-o-matic.net [3]. Idwer suggested a service similar to >> ROM-o-matic.net where know revisions get build by this server and users >> can configure an image to be built. That is an interesting idea although >> it is probably the most difficult to realize. Could this be a GSoC >> project? >> >> 6. File in repository. An other suggestion by Patrick and myself is to >> put a file in for example `Documentation/working-revisions.mdtext` and >> note the tested revision and board there or to put a file in each board >> directory and note tested revisions there. The downside is that people >> would have to register with Gerrit to submit changes. >> >> If we would manage our Wiki in our repository [4] options 3 and 6 could >> be combined. >> >> 7. Messages to the list. Thinking about it the easiest solution would be >> to create something like the script `alsa-info.sh`. This script collects >> the necessary information – in our case for example revision, boards, >> cbfs output, used build tools. Even better would be to run that script >> on the tested machine so also something like the tested distribution >> could be tested. >> >> Then a mbox or text file with an appropriate name/subject line is >> created >> >> [Tested] ASUS M2V-MX SE works with revision <commit> >> >> which gets send to the list by the user or automatically. >> >> People then can search the archive. The only downside is that a nice >> table is missing. >> >> All in all I am quite surprised that no nice solutions seem to exist >> especially since I would imagine quality assurance (QA) folks in >> companies need to maintain similar data. >> >> Please comment and add your ideas. >> >> >> Thanks, >> >> Paul >> >> >> [1] http://www.coreboot.org/Supported_Motherboards >> [2] http://www.openembedded.org/wiki/Testing >> [3] http://rom-o-matic.net/ >> [4] http://www.coreboot.org/pipermail/coreboot/2011-June/065706.html >> [5] http://alsa-project.org/main/index.php/Help_To_Debug >> > > Hi Paul, > > Thanks for the writeup. I prefer option #3 and that this was > information kept in the wiki somehow. It is searchable by the public > at large. I would like to see us do a better job at the wiki as it is > the public face of the project and the best place for new developers > and users to get information. I like the idea of the maillist script. > I think that would be great. With that, a wiki page or other html page > could be easily generated. New users may not join the maillist but it > is searchable by the public. Personally, I really don't like > non-source files in the source repository. It is the most difficult > place to find information and has a high bar to enter to get some > simple information. > > Regards, > Marc > > > > > -- > http://se-eng.com > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Patch merged into coreboot/master: feb5cbb Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
by gerrit＠coreboot.org 11 Oct '11

11 Oct '11

the following patch was just integrated into master: commit feb5cbb72fc0424f9aecf0db122d2344b4fb9512 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Thu Oct 6 18:21:19 2011 +0200 Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to mark dram memory above 4GB as WB. However, AMD K8 rev E and earlier don't implement this bit and therefore need MTRR spanning dram memory above 4GB. The current implementation of amd_setup_mtrrs never generate MTRR above 4GB. This caused memory > 4GB not to be recognized in e.g. Linux on those rev E or older platforms. This commit should fix that bug. Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1 See http://review.coreboot.org/238 for details. -gerrit

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Patch set updated for coreboot: 42acf3c mainboard: complete the sb800 devicetree even device is off
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/230 -gerrit commit 42acf3ccf042ecf596df8d149ad66512e81a8fc8 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Mon Oct 10 19:19:46 2011 +0800 mainboard: complete the sb800 devicetree even device is off sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/inagua/devicetree.cb | 2 ++ src/mainboard/asrock/e350m1/devicetree.cb | 2 ++ src/southbridge/amd/cimx/sb800/late.c | 4 +++- 3 files changed, 7 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 82658cf..32d9a26 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -71,6 +71,8 @@ chip northbridge/amd/agesa/family14/root_complex device pci 15.1 on end # PCIe PortB device pci 15.2 on end # PCIe PortC device pci 15.3 on end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 register "gpp_configuration" = "4" #1:1:1:1 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index bff8151..ca5cf2b 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -103,6 +103,8 @@ chip northbridge/amd/agesa/family14/root_complex device pci 15.1 on end # PCIe PortB: NIC device pci 15.2 on end # PCIe PortC: USB3 device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 # gpp_configuration options #0000: PortA lanes[3:0] diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b581212..c36ee03 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -419,7 +419,9 @@ static void sb800_enable(device_t dev) case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; - /* the last sb800 device */ + /* call the CIMX entry at the last sb800 device, + * so make sure the mainboard devicetree is complete + */ sb_Before_Pci_Init(); break;

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Patch merged into coreboot/master: 42acf3c mainboard: complete the sb800 devicetree even device is off
by gerrit＠coreboot.org 11 Oct '11

11 Oct '11

the following patch was just integrated into master: commit 42acf3ccf042ecf596df8d149ad66512e81a8fc8 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Mon Oct 10 19:19:46 2011 +0800 mainboard: complete the sb800 devicetree even device is off sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/230 for details. -gerrit

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Patch merged into coreboot/master: eb0e452 sb800: sata combine mode configure fix
by gerrit＠coreboot.org 11 Oct '11

11 Oct '11

the following patch was just integrated into master: commit eb0e4526ffeb1330d9c2b9f2c69cac6a4f3a41ec Author: Kerry Sheh <shekairui(a)gmail.com> Date: Mon Oct 10 18:23:49 2011 +0800 sb800: sata combine mode configure fix Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to configure SataIdeCombinedMode is wrong. sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller 0: IDE controller is exposed and Combined Mode is enabled. SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5 1: IDE controller is hidden and Combined Mode is disabled, SATA controller has full control of all 6 Ports when operating in non-IDE mode Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/229 for details. -gerrit

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Patch merged into coreboot/master: 429729d persimmon: sb800 sata mode configure update
by gerrit＠coreboot.org 11 Oct '11

11 Oct '11

the following patch was just integrated into master: commit 429729d93d3562ccca5f2f13f407ae7a8a971212 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Mon Oct 10 18:13:51 2011 +0800 persimmon: sb800 sata mode configure update persimmon configure sb800 sata mode according to the southbridge kconfig selection. Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/227 for details. -gerrit

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Patch merged into coreboot/master: eb837a7 sb800: Add sata ahci/raid mode kconfig option
by gerrit＠coreboot.org 11 Oct '11

11 Oct '11

the following patch was just integrated into master: commit eb837a74ad78ed6d98ba0799f7ed2ed8475b1fd5 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Mon Oct 10 17:17:39 2011 +0800 sb800: Add sata ahci/raid mode kconfig option If sb800 sata was configured as ahci or raid mode, give the option to add ROM files. Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/225 for details. -gerrit

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coreboot October 2011