Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/231
-gerrit
commit 6060f7630470c14ad60ac885a2103c7286034779
Author: Kerry Sheh <shekairui(a)gmail.com>
Date: Sun Oct 9 14:26:21 2011 +0800
sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
Add this option to enable/disable SATA IDE Combined Mode feature
Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
Signed-off-by: Kerry Sheh <kerry.she(a)amd.com>
Signed-off-by: Kerry Sheh <shekairui(a)gmail.com>
---
src/southbridge/amd/cimx/sb800/Kconfig | 16 ++++++++++++++++
src/southbridge/amd/cimx/sb800/cfg.c | 2 +-
src/southbridge/amd/cimx/sb800/late.c | 5 -----
3 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index dc4dd7a..1370e7e 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/cimx/sb800/bootblock.c"
+config ENABLE_IDE_COMBINED_MODE
+ bool "Enable SATA IDE combined mode"
+ default n
+ help
+ If Combined Mode is enabled. IDE controller is exposed and
+ SATA controller has control over Port0 through Port3,
+ IDE controller has control over Port4 and Port5.
+
+ If Combined Mode is disabled, IDE controller is hidden and
+ SATA controller has full control of all 6 Ports when operating in non-IDE mode.
+
+config IDE_COMBINED_MODE
+ hex
+ default "0x0" if ENABLE_IDE_COMBINED_MODE
+ default "0x1" if !ENABLE_IDE_COMBINED_MODE
+
choice
prompt "SATA Mode"
default SB800_SATA_IDE
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index a7801a8..a34dd14 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
//TODO: set to secondary not take effect.
- sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
/* Azalia HDA */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index d0e752f..74f952a 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -343,11 +343,6 @@ static void sb800_enable(device_t dev)
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
- if (dev->enabled) {
- sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED;
- } else {
- sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
- }
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
Hello, Thomas
> -----Original Message-----
> From: coreboot-bounces+kerry.she=amd.com(a)coreboot.org [mailto:coreboot-
> bounces+kerry.she=amd.com(a)coreboot.org] On Behalf Of Marc Jones
> Sent: Saturday, October 08, 2011 3:45 AM
> To: Thomas Gstädtner
> Cc: coreboot
> Subject: Re: [coreboot] Issues with Supermicro H8SCM
>
> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gstädtner <thomas(a)gstaedtner.net>
> wrote:
> > On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303(a)gmail.com> wrote:
> >> On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gstädtner
> <thomas(a)gstaedtner.net> wrote:
> >>> Hi everyone,
> >>>
> >>> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
> >>> the boards AMD as of recently claims to officially support.
> >>> So I decided to try coreboot, but (as expected) it is not really an
> >>> out-of-the-box experience.
> >>>
> >>> First of all, flashrom does not support flashing out-of-the-box, but
> >>> Frederic Temporelli's patches (
> >>> http://patchwork.coreboot.org/patch/3326/ and
> >>> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I
> tested
> >>> multiple reads and multiple writes, always worked), I can report that
> >>> to the flashrom list separately if you want.
> >>>
> >>> I built coreboot from the gerrit-branch (also tried a "stable"
> >>> revision), coreboot-4.0-1714-gf8adf7a, using the "default"
> >>> board-config incl. seabios (stable) as payload.
> >>> After powering on nothing happens (apart from the fans running and
> the
> >>> power led flashing) and it stays that way, it is silent on VGA as
> well
> >>> as serial.
> >>> After manually triggering a reset I immediately get the following
> >>> output on serial:
> >>>
> >>> coreboot-4.0-1714-gf8adf7a Wed Oct 5 00:31:05 CEST 2011 starting...
> >>> BSP Family_Model:
> >>>
> >>> Here it hangs, and I don't quite know how to move on and debug the
> issue.
> >>>
> >>> Can you give me any hints where to go on from here? I have external
> >>> flashing equipment at hand (which also works fine btw.), but no fancy
> >>> bios-debugging hardware.
> >>>
> >>> Regards,
> >>>
> >>> thomasg
> >>>
> >>> P.S. In case anyone else stumbles upon it: the board has 2 separate
> >>> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
> >>> package on the left of the board) as well as a SST25VF016B, 16 Mbit,
> >>> as the SOIC8W on the right. The first one holds the IPMI firmware,
> the
> >>> second one the AMI BIOS.
> >>> Flashing requires a testclip or some really serious soldering skills.
> >>> Attaching a SO8 socket can only be done with hot air soldering.
> >>
> >> Hi Thomas,
> >>
> >> Thanks for the report. While many people overlap with the flashrom
> >> list, please post about those patches on that list. Seems that you
> >> should be able to ack them.
> >>
> >> It looks like maybe the platform build doesn't support your CPU.
> >> There have been a number of recent contributions from AMD, but they
> >> don't all align with the platform contributions. So, the H8SCM should
> >> support all fam10 revD, but may have issue with Fam10 rev E. To get
> >> more information, you can turn the console debug output to SPEW in
> >> menuconfig.
> >>
> >> Marc
> >>
> >>
> >>
> >> --
> >> http://se-eng.com
> >>
> >
> > Thanks for the advice Marc,
> >
> > I already had the loglevel set to spew (8). I additionally tried the
> > other "Verbose output" debugging options, unfortunately I don't get
> > any output at all when they are built in.
> > Also, while it is hard to find and AMD doesn't have any official
> > document confirming this, according to some google hits the processor
> > should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ).
I also found the latest code not boot on my H8SCM-F mainboard with Rev D1 processor.
So I have made some update to using the AGESA wrapper framework, the attachment is some of my update, with this series of patches applied, we can boot to Debian Linux Destop or Windows Server 2008 R2 standard edition.
Thanks
Kerry
> > (Sry for sending the mail twice, hit the wrong button)
> >
>
> Oh, I just recalled something about the H8SCM. There is jumper to
> disable the bmc which might have a watchdog that coreboot can't deal
> with. Did you disable that?
>
> Marc
>
>
> --
> http://se-eng.com
>
> --
> coreboot mailing list: coreboot(a)coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gstädtner <thomas(a)gstaedtner.net> wrote:
> On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303(a)gmail.com> wrote:
>> On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gstädtner <thomas(a)gstaedtner.net> wrote:
>>> Hi everyone,
>>>
>>> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of
>>> the boards AMD as of recently claims to officially support.
>>> So I decided to try coreboot, but (as expected) it is not really an
>>> out-of-the-box experience.
>>>
>>> First of all, flashrom does not support flashing out-of-the-box, but
>>> Frederic Temporelli's patches (
>>> http://patchwork.coreboot.org/patch/3326/ and
>>> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I tested
>>> multiple reads and multiple writes, always worked), I can report that
>>> to the flashrom list separately if you want.
>>>
>>> I built coreboot from the gerrit-branch (also tried a "stable"
>>> revision), coreboot-4.0-1714-gf8adf7a, using the "default"
>>> board-config incl. seabios (stable) as payload.
>>> After powering on nothing happens (apart from the fans running and the
>>> power led flashing) and it stays that way, it is silent on VGA as well
>>> as serial.
>>> After manually triggering a reset I immediately get the following
>>> output on serial:
>>>
>>> coreboot-4.0-1714-gf8adf7a Wed Oct 5 00:31:05 CEST 2011 starting...
>>> BSP Family_Model:
>>>
>>> Here it hangs, and I don't quite know how to move on and debug the issue.
>>>
>>> Can you give me any hints where to go on from here? I have external
>>> flashing equipment at hand (which also works fine btw.), but no fancy
>>> bios-debugging hardware.
>>>
>>> Regards,
>>>
>>> thomasg
>>>
>>> P.S. In case anyone else stumbles upon it: the board has 2 separate
>>> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W
>>> package on the left of the board) as well as a SST25VF016B, 16 Mbit,
>>> as the SOIC8W on the right. The first one holds the IPMI firmware, the
>>> second one the AMI BIOS.
>>> Flashing requires a testclip or some really serious soldering skills.
>>> Attaching a SO8 socket can only be done with hot air soldering.
>>
>> Hi Thomas,
>>
>> Thanks for the report. While many people overlap with the flashrom
>> list, please post about those patches on that list. Seems that you
>> should be able to ack them.
>>
>> It looks like maybe the platform build doesn't support your CPU.
>> There have been a number of recent contributions from AMD, but they
>> don't all align with the platform contributions. So, the H8SCM should
>> support all fam10 revD, but may have issue with Fam10 rev E. To get
>> more information, you can turn the console debug output to SPEW in
>> menuconfig.
>>
>> Marc
>>
>>
>>
>> --
>> http://se-eng.com
>>
>
> Thanks for the advice Marc,
>
> I already had the loglevel set to spew (8). I additionally tried the
> other "Verbose output" debugging options, unfortunately I don't get
> any output at all when they are built in.
> Also, while it is hard to find and AMD doesn't have any official
> document confirming this, according to some google hits the processor
> should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ).
>
> (Sry for sending the mail twice, hit the wrong button)
>
Oh, I just recalled something about the H8SCM. There is jumper to
disable the bmc which might have a watchdog that coreboot can't deal
with. Did you disable that?
Marc
--
http://se-eng.com