coreboot October 2011

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Patch set updated for coreboot: 00bff57 Fixes several issues with amd k8 SSDT P-state generation
by Oskar Enoksson 07 Oct '11

07 Oct '11

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/239 -gerrit commit 00bff5758e8104153ff9668fe739026ab977ab9a Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Thu Oct 6 18:43:43 2011 +0200 Fixes several issues with amd k8 SSDT P-state generation For multi-socket CPU the current implementation emitted Processor objects for cores in the first CPU only. This commit fixes the bug. One caveat though: the unlikely case of mixed CPU models is still not handled correctly. Second issue fixed: One loop was wrong in case a processor in the table declares no P-states at all. The rewritten loop is safe. Some possibly dangerous array lengths were also fixed. Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV according to the BKDG. The current implementation always set it to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS. Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417 --- src/cpu/amd/model_fxx/powernow_acpi.c | 81 +++++++++++++++++++++++++-------- 1 files changed, 61 insertions(+), 20 deletions(-) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index bbcf013..c49322f 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -586,15 +586,17 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) u8 cmp_cap; struct cpuentry *data = NULL; uint32_t control; - int i = 0, index, len = 0, Pstate_num = 0; + int i = 0, index = 0, len = 0, Pstate_num = 0, dev = 0; msr_t msr; - u8 Pstate_fid[10]; - u16 Pstate_feq[10]; - u8 Pstate_vid[10]; - u32 Pstate_power[10]; + u8 Pstate_fid[MAXP+1]; + u16 Pstate_feq[MAXP+1]; + u8 Pstate_vid[MAXP+1]; + u32 Pstate_power[MAXP+1]; u8 Max_fid, Start_fid, Start_vid, Max_vid; struct cpuid_result cpuid1 = cpuid(0x80000001); + // Because I don't know how to read msr registers from + // other CPU's I assume they all have the same SYSCONF values msr = rdmsr(0xc0010042); Max_fid = (msr.lo & 0x3F0000) >> 16; Max_vid = (msr.hi & 0x3F0000) >> 16; @@ -619,25 +621,57 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n"); return 0; } + /* See if the CPUID(0x80000007) returned EDX[2:1]==11b */ + cpuid1 = cpuid(0x80000007); + if((cpuid1.edx & 0x6)!=0x6) { + printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n"); + return 0; + } + +#if CONFIG_MAX_PHYSICAL_CPUS==1 + // IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us + control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11); +#else + // MP-systems should default to RVO=0mV (no ramp voltage) + // IRT 80us RVO = 0mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us + control = (3 << 30) | (0 << 28) | (2 << 20) | (0 << 18) | (5 << 11); +#endif + // RVO (Ramp Voltage Offset) + // 00 0mV (default for MP-systems) + // 01 25mV + // 10 50mV (default) + // 11 75mV + // IRT (Isochronous Release Time) + // 00 10uS + // 01 20uS + // 10 40uS + // 11 80uS (default) + // MVS (Maximum Voltage Step) + // 00 25mV (default) + // 01 50mV (reserved) + // 10 100mV (reserved) + // 11 200mV (reserved) + // VST (Voltage Stabilization Time) + // time = value*20uS (default value: 5 => 100uS) + // PLL_LOCK_TIME + // time is value*1uS (often seen value: 2uS) + // - /* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */ - control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29); len = 0; - Pstate_num = 0; - Pstate_fid[Pstate_num] = Max_fid; - Pstate_feq[Pstate_num] = fid_to_freq(Max_fid); - Pstate_vid[Pstate_num] = Max_vid; - Pstate_power[Pstate_num] = data->pwr * 100; - Pstate_num++; + Pstate_fid[0] = Max_fid; + Pstate_feq[0] = fid_to_freq(Max_fid); + Pstate_vid[0] = Max_vid; + Pstate_power[0] = data->pwr * 100; - do { + for(Pstate_num = 1; + (Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0); + Pstate_num++) { Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f; Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz; Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage); Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100; - Pstate_num++; - } while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0)); + } for (i=0;i<Pstate_num;i++) printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i, @@ -645,11 +679,18 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) vid_from_reg(Pstate_vid[i]), Pstate_power[i]); - for (index = 0; index < (cmp_cap + 1); index++) { - len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, - Pstate_fid, Pstate_power, index, - pcontrol_blk, plen, onlyBSP, control); + for (dev = 0x18; dev < 0x1c; dev++) { + if(dev_find_slot(0, PCI_DEVFN(dev, 0))==NULL) + continue; + + for (i = 0; i < (cmp_cap + 1); i++) { + len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, + Pstate_fid, Pstate_power, index+i, + pcontrol_blk, plen, onlyBSP, control); + } + index += i; } + printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index); return len; }

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Re: [coreboot] Issues with Supermicro H8SCM
by Thomas Gstädtner 07 Oct '11

07 Oct '11

On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303(a)gmail.com> wrote: > On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gstädtner <thomas(a)gstaedtner.net> wrote: >> Hi everyone, >> >> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of >> the boards AMD as of recently claims to officially support. >> So I decided to try coreboot, but (as expected) it is not really an >> out-of-the-box experience. >> >> First of all, flashrom does not support flashing out-of-the-box, but >> Frederic Temporelli's patches ( >> http://patchwork.coreboot.org/patch/3326/ and >> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I tested >> multiple reads and multiple writes, always worked), I can report that >> to the flashrom list separately if you want. >> >> I built coreboot from the gerrit-branch (also tried a "stable" >> revision), coreboot-4.0-1714-gf8adf7a, using the "default" >> board-config incl. seabios (stable) as payload. >> After powering on nothing happens (apart from the fans running and the >> power led flashing) and it stays that way, it is silent on VGA as well >> as serial. >> After manually triggering a reset I immediately get the following >> output on serial: >> >> coreboot-4.0-1714-gf8adf7a Wed Oct 5 00:31:05 CEST 2011 starting... >> BSP Family_Model: >> >> Here it hangs, and I don't quite know how to move on and debug the issue. >> >> Can you give me any hints where to go on from here? I have external >> flashing equipment at hand (which also works fine btw.), but no fancy >> bios-debugging hardware. >> >> Regards, >> >> thomasg >> >> P.S. In case anyone else stumbles upon it: the board has 2 separate >> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W >> package on the left of the board) as well as a SST25VF016B, 16 Mbit, >> as the SOIC8W on the right. The first one holds the IPMI firmware, the >> second one the AMI BIOS. >> Flashing requires a testclip or some really serious soldering skills. >> Attaching a SO8 socket can only be done with hot air soldering. > > Hi Thomas, > > Thanks for the report. While many people overlap with the flashrom > list, please post about those patches on that list. Seems that you > should be able to ack them. > > It looks like maybe the platform build doesn't support your CPU. > There have been a number of recent contributions from AMD, but they > don't all align with the platform contributions. So, the H8SCM should > support all fam10 revD, but may have issue with Fam10 rev E. To get > more information, you can turn the console debug output to SPEW in > menuconfig. > > Marc > > > > -- > http://se-eng.com > Thanks for the advice Marc, I already had the loglevel set to spew (8). I additionally tried the other "Verbose output" debugging options, unfortunately I don't get any output at all when they are built in. Also, while it is hard to find and AMD doesn't have any official document confirming this, according to some google hits the processor should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ). (Sry for sending the mail twice, hit the wrong button)

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Re: [coreboot] crossgcc/buildgcc gdb7.2 version name change
by Marc Jones 07 Oct '11

07 Oct '11

2011/10/7 Alp Eren Köse <alperenkose(a)buyutech.com.tr>: > gdb7.2 is renamed to gdb7.2a in > http://ftp.gnu.org/gnu/gdb/ > > so 'make crosgcc' fails with: > Failed to download gdb-7.2.tar.bz2. > make[1]: *** [build] Error 1 > make: *** [crossgcc] Error 2 > > It seems, the gdb version in util/crossgcc/buildgcc needs to be updated? That has been overcome by events. Please update your tree. http://review.coreboot.org/#change,214 -- http://se-eng.com

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crossgcc/buildgcc gdb7.2 version name change
by Alp Eren Köse 07 Oct '11

07 Oct '11

gdb7.2 is renamed to gdb7.2a in http://ftp.gnu.org/gnu/gdb/ so 'make crosgcc' fails with: Failed to download gdb-7.2.tar.bz2. make[1]: *** [build] Error 1 make: *** [crossgcc] Error 2 It seems, the gdb version in util/crossgcc/buildgcc needs to be updated?

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New patch to review for coreboot: ae3a08a amd/sb600: Enable COM2 at all times in early setup
by Patrick Georgi 07 Oct '11

07 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/241 -gerrit commit ae3a08acb2fb105e35f218f810619b48f4501f76 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Oct 7 14:43:27 2011 +0200 amd/sb600: Enable COM2 at all times in early setup Otherwise with a coreboot log on COM2 (which doesn't work) the boot process takes eons. Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/southbridge/amd/sb600/early_setup.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 838ea31..5ffd3d8 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -53,11 +53,11 @@ static u8 get_sb600_revision(void) /*************************************** * Legacy devices are mapped to LPC space. -* Serial port 0 +* Serial port 0, 1 * KBC Port * ACPI Micro-controller port * This function does not change port 0x80 decoding. -* Console output through any port besides 0x3f8 is unsupported. +* Console output through any port besides 0x2f8/0x3f8 is unsupported. * If you use FWH ROMs, you have to setup IDSEL. * Reviewed-by: Carl-Daniel Hailfinger * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1 @@ -84,10 +84,9 @@ static void sb600_lpc_init(void) pci_write_config32(dev, 0x64, reg32); dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */ - /* Decode port 0x3f8-0x3ff (Serial 0) */ - // XXX Serial port decode on LPC is hardcoded to 0x3f8 + /* Decode port 0x3f8-0x3ff (Serial 0), 0x2f8-0x2ff (Serial 1) */ reg8 = pci_read_config8(dev, 0x44); - reg8 |= 1 << 6; + reg8 |= (1 << 6) | (1 << 7); pci_write_config8(dev, 0x44, reg8); /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/

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New patch to review for coreboot: 84628e8 siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
by Patrick Georgi 07 Oct '11

07 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/242 -gerrit commit 84628e8a3e0f67d638d62af7910ebaab8f85e855 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Oct 6 14:34:22 2011 +0200 siemens/sitemp_g1p1: Get rid of bus_isa and bus_type Each variable is essentially unused or incorrect. Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 23 +--------------------- src/mainboard/siemens/sitemp_g1p1/irq_tables.c | 1 - src/mainboard/siemens/sitemp_g1p1/mptable.c | 14 ++++-------- 3 files changed, 6 insertions(+), 32 deletions(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c index 24b9f28..2b0fca7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c +++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c @@ -32,7 +32,6 @@ /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. */ -u8 bus_isa; u8 bus_rs690[8]; u8 bus_sb600[2]; u32 apicid_sb600; @@ -54,8 +53,6 @@ u32 hcdnx[] = { 0x20202020, }; -u32 bus_type[256]; - u32 sbdn_rs690; u32 sbdn_sb600; @@ -67,7 +64,7 @@ void get_bus_conf(void) { u32 apicid_base; device_t dev; - int i, j; + int i; if (get_bus_conf_done == 1) return; /* do it only once */ @@ -92,25 +89,13 @@ void get_bus_conf(void) bus_rs690[i] = 0; } - for (i = 0; i < 256; i++) { - bus_type[i] = 0; /* default ISA bus. */ - } - - bus_type[0] = 1; /* pci */ - bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_sb600[0] = bus_rs690[0]; - bus_type[bus_rs690[0]] = 1; - /* sb600 */ dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4)); if (dev) { bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - for (j = bus_sb600[1]; j < bus_isa; j++) - bus_type[j] = 1; } /* rs690 */ @@ -118,16 +103,10 @@ void get_bus_conf(void) dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0)); if (dev) { bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - if(255 != bus_rs690[i]) { - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - bus_type[bus_rs690[i]] = 1; /* PCI bus. */ - } } } /* I/O APICs: APIC ID Version State Address */ - bus_isa = 10; #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c index 63b532d..b2a9668 100644 --- a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c @@ -68,7 +68,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_isa; extern u8 bus_rs690[8]; extern u8 bus_sb600[2]; extern unsigned long sbdn_sb600; diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index df2f77b..d5b18ec 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -26,13 +26,11 @@ #include <cpu/amd/amdk8_sysconf.h> -extern u8 bus_isa; extern u8 bus_rs690[8]; extern u8 bus_sb600[2]; extern u32 apicid_sb600; -extern u32 bus_type[256]; extern u32 sbdn_rs690; extern u32 sbdn_sb600; @@ -46,12 +44,9 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); get_bus_conf(); - printk(BIOS_DEBUG, "%s: bus_isa=%d, apic_id=0x%x\n", __func__, bus_isa, apicid_sb600); + printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600); mptable_write_buses(mc, NULL, &isa_bus); - if (isa_bus != bus_isa) { - printk(BIOS_ERR, "ISA bus numbering schemes differ! Please fix mptable.c\n"); - } /* I/O APICs: APIC ID Version State Address */ { device_t dev; @@ -63,10 +58,11 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_sb600, 0x20, res->base); } } - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); + mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum =

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New patch to review for coreboot: b768713 siemens/sitemp_g1p1: Don't mess with virtual wire settings
by Patrick Georgi 07 Oct '11

07 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/243 -gerrit commit b7687135f3d1f17fcaa3c47c9856319ac7ab7645 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Oct 6 15:24:08 2011 +0200 siemens/sitemp_g1p1: Don't mess with virtual wire settings That function broke SMP on Linux 2.4, now it works. Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/siemens/sitemp_g1p1/mptable.c | 10 ---------- 1 files changed, 0 insertions(+), 10 deletions(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index d5b18ec..f1f96d2 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -73,19 +73,9 @@ static void *smp_write_config_table(void *v) return smp_next_mpe_entry(mc); } -static void fixup_virtual_wire(void *v) -{ - struct intel_mp_floating *mf = v; - - mf->mpf_checksum = 0; - mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE; - mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); -} - unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); - fixup_virtual_wire(v); return (unsigned long)smp_write_config_table(v); }

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Re: [coreboot] Coreboot on Axiomtek PICO821
by Alp Eren Köse 07 Oct '11

07 Oct '11

> If you store that spare rom in a safe place and only use it to boot > from, you don't need an external programmer. A often used trick to > ease removal is to glue a handle to the chip: > http://www.settoplinux.org/images/thumb/5/56/Push_pin2.jpg/500px-Push_pin2.… Ok, if I understand it right, when I brick the first rom, I can boot using the second one into a freedos, remove the rom while the system is running and put the bricked rom in and flash the original BIOS, is that correct?? The pin trick is very nice btw:) > 4) Copy the files from the iwave board (cd src/mainboard/iwave/iWRainbowG6/ ; cp -r * ../../axiomtek/pico821/ ), > edit at least devicetree.cb, Kconfig and mainboard.c. Then replace the names but keep the (C) copyright headers. I suppose I will edit devicetree.cb file according to my lspci output, but I didn't get how to modify the lines similar to following: chip southbridge/intel/sch register "pirqa_routing" = "0xa" register "pirqb_routing" = "0xb" Are those something about IRQ routing? my board also have Intel SCH so I hope they are the same.. And there is not much in mainboard.c file, I couldn't see much to change apart from the CHIP_NAME? > Compile and run superiotool, it's in util/superiotool/ I have run it on my board, i have an " Winbond W83627HF/F/HG/G (id=0x52, rev=0x41)", but I don't know what iWRainbowG6 has on it? I looked at the code, but couldn't figure what it's SuperIO chip is? Anyone know, or own this board, could tell me? Sorry it's been lots of questions, thank you very much for guiding, Thanks in advance, Alp 2011/10/7 Idwer Vollering <vidwer(a)gmail.com> > 2011/10/7 Alp Eren Köse <alperenkose(a)buyutech.com.tr>: > > > >> 1. Make sure you can recover from a bad image (extra flash chip with > >> the original BIOS) > > > > Ok, I have got a spare rom which is a "SST SST49LF008A" (1024 KB, FWH) > with > > the original bios, but i don't have an external programmer to flash if > the > > first one is bricked.. > > If you store that spare rom in a safe place and only use it to boot > from, you don't need an external programmer. A often used trick to > ease removal is to glue a handle to the chip: > > http://www.settoplinux.org/images/thumb/5/56/Push_pin2.jpg/500px-Push_pin2.… > > > > >> 2. Make sure you can get serial output > > > > I believe I can do it, the board has an RS232 port, so I guess i need a > null > > modem cable to connect it to the computer.. > > > >> 3. Choose the most similar supported motherboard > > > > I guess it is the iWave iW-RainboW-G6 as Idwer Vollering suggested.. > > > >> 4. Change the code to support your board > > > > Well this is a little problem, I don't know exactly where and what to > change > > in the code, > > I believe i need to make a copy of src/mainboard/iwave/iWRainbowG6 and > > modify files to fit it my mainboard.. > > 0) Compile crossgcc: run "make crossgcc" in the top source directory > 1) Edit src/mainboard/Kconfig > 2) Make a directory named axiomtek/pico821 in src/mainboard/ (run this > in the top source code directory: mkdir -p src/mainboard > /axiomtek/pico821 ) > 3) Add the file src/mainboard/axiomtek/Kconfig and edit that file, > you'll want to take src/mainboard/iwave/iWRainbowG6/Kconfig as an > example. > 4) Copy the files from the iwave board (cd > src/mainboard/iwave/iWRainbowG6/ ; cp -r * ../../axiomtek/pico821/ ), > edit at least devicetree.cb, Kconfig and mainboard.c. Then replace the > names but keep the (C) copyright headers. > 5) "cd" back into the top source dir and run "make menuconfig ; make" > (or make xconfig/gconfig) where you select the axiomtek mainboard. > Exit the menu, save the configuration and run "make"; after a minute > or so you should have the file build/coreboot.rom which you'll have to > program into the first chip. > 6) Make sure that you have stored the spare rom in a safe place, then > download, compile and install flashrom: > http://www.flashrom.org/Downloads#Installation_from_source > > http://www.coreboot.org/Developer_Manual#How_to_support_a_new_board > > > I have some C knowledge, but I would really need help, and some people to > > show me the way what and where to change in the code at least to make it > > work? > > > >> 5. Try it > >> 6. Iterate on 4&5 until you're happy with it > >> 7. Send a patch > > > > I would for sure send a patch if I can make it work :) > > Btw the CPU and the southbridge/northbridge matches with the Rainbow-G6, > but > > I don't know about the SuperIO of it, there is just a "-" in the list of > > supported motherboards for superIO of Rainbow-G6.. > > Compile and run superiotool, it's in util/superiotool/ > > > > > Thanks in advance, > > Alp > > > > 2011/10/5 Myles Watson <mylesgw(a)gmail.com> > >> > >> 2011/10/5 Alp Eren Köse <alperenkose(a)buyutech.com.tr>: > >> > Anyone has an idea? > >> > > >> > Another question is I can't find my mainboard vendor "Axiomtek" in > >> > Mainboard > >> > Vendor selection list in menuconfig as expectedly, but all the chips > and > >> > chipset of it seem to be supported as I see them in coreboot website. > Is > >> > it > >> > still possible to install coreboot, if so how can I do it? > >> > It would be really nice if someone could point a way.. > >> > >> Generally the steps are: > >> 1. Make sure you can recover from a bad image (extra flash chip with > >> the original BIOS) > >> 2. Make sure you can get serial output > >> 3. Choose the most similar supported motherboard > >> 4. Change the code to support your board > >> 5. Try it > >> 6. Iterate on 4&5 until you're happy with it > >> 7. Send a patch > >> > >> If you don't have 1 & 2 you shouldn't try at all. > >> > >> Good luck! > >> Myles > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > >

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Re: [coreboot] Coreboot on Axiomtek PICO821
by Idwer Vollering 07 Oct '11

07 Oct '11

2011/10/7 Alp Eren Köse <alperenkose(a)buyutech.com.tr>: > >> 1. Make sure you can recover from a bad image (extra flash chip with >> the original BIOS) > > Ok, I have got a spare rom which is a "SST SST49LF008A" (1024 KB, FWH) with > the original bios, but i don't have an external programmer to flash if the > first one is bricked.. If you store that spare rom in a safe place and only use it to boot from, you don't need an external programmer. A often used trick to ease removal is to glue a handle to the chip: http://www.settoplinux.org/images/thumb/5/56/Push_pin2.jpg/500px-Push_pin2.… > >> 2. Make sure you can get serial output > > I believe I can do it, the board has an RS232 port, so I guess i need a null > modem cable to connect it to the computer.. > >> 3. Choose the most similar supported motherboard > > I guess it is the iWave iW-RainboW-G6 as Idwer Vollering suggested.. > >> 4. Change the code to support your board > > Well this is a little problem, I don't know exactly where and what to change > in the code, > I believe i need to make a copy of src/mainboard/iwave/iWRainbowG6 and > modify files to fit it my mainboard.. 0) Compile crossgcc: run "make crossgcc" in the top source directory 1) Edit src/mainboard/Kconfig 2) Make a directory named axiomtek/pico821 in src/mainboard/ (run this in the top source code directory: mkdir -p src/mainboard /axiomtek/pico821 ) 3) Add the file src/mainboard/axiomtek/Kconfig and edit that file, you'll want to take src/mainboard/iwave/iWRainbowG6/Kconfig as an example. 4) Copy the files from the iwave board (cd src/mainboard/iwave/iWRainbowG6/ ; cp -r * ../../axiomtek/pico821/ ), edit at least devicetree.cb, Kconfig and mainboard.c. Then replace the names but keep the (C) copyright headers. 5) "cd" back into the top source dir and run "make menuconfig ; make" (or make xconfig/gconfig) where you select the axiomtek mainboard. Exit the menu, save the configuration and run "make"; after a minute or so you should have the file build/coreboot.rom which you'll have to program into the first chip. 6) Make sure that you have stored the spare rom in a safe place, then download, compile and install flashrom: http://www.flashrom.org/Downloads#Installation_from_source http://www.coreboot.org/Developer_Manual#How_to_support_a_new_board > I have some C knowledge, but I would really need help, and some people to > show me the way what and where to change in the code at least to make it > work? > >> 5. Try it >> 6. Iterate on 4&5 until you're happy with it >> 7. Send a patch > > I would for sure send a patch if I can make it work :) > Btw the CPU and the southbridge/northbridge matches with the Rainbow-G6, but > I don't know about the SuperIO of it, there is just a "-" in the list of > supported motherboards for superIO of Rainbow-G6.. Compile and run superiotool, it's in util/superiotool/ > > Thanks in advance, > Alp > > 2011/10/5 Myles Watson <mylesgw(a)gmail.com> >> >> 2011/10/5 Alp Eren Köse <alperenkose(a)buyutech.com.tr>: >> > Anyone has an idea? >> > >> > Another question is I can't find my mainboard vendor "Axiomtek" in >> > Mainboard >> > Vendor selection list in menuconfig as expectedly, but all the chips and >> > chipset of it seem to be supported as I see them in coreboot website. Is >> > it >> > still possible to install coreboot, if so how can I do it? >> > It would be really nice if someone could point a way.. >> >> Generally the steps are: >> 1. Make sure you can recover from a bad image (extra flash chip with >> the original BIOS) >> 2. Make sure you can get serial output >> 3. Choose the most similar supported motherboard >> 4. Change the code to support your board >> 5. Try it >> 6. Iterate on 4&5 until you're happy with it >> 7. Send a patch >> >> If you don't have 1 & 2 you shouldn't try at all. >> >> Good luck! >> Myles > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Coreboot on Axiomtek PICO821
by Alp Eren Köse 07 Oct '11

07 Oct '11

> 1. Make sure you can recover from a bad image (extra flash chip with > the original BIOS) Ok, I have got a spare rom which is a "SST SST49LF008A" (1024 KB, FWH) with the original bios, but i don't have an external programmer to flash if the first one is bricked.. > 2. Make sure you can get serial output I believe I can do it, the board has an RS232 port, so I guess i need a null modem cable to connect it to the computer.. > 3. Choose the most similar supported motherboard I guess it is the iWave iW-RainboW-G6 as Idwer Vollering suggested.. > 4. Change the code to support your board Well this is a little problem, I don't know exactly where and what to change in the code, I believe i need to make a copy of src/mainboard/iwave/iWRainbowG6 and modify files to fit it my mainboard.. I have some C knowledge, but I would really need help, and some people to show me the way what and where to change in the code at least to make it work? > 5. Try it > 6. Iterate on 4&5 until you're happy with it > 7. Send a patch I would for sure send a patch if I can make it work :) Btw the CPU and the southbridge/northbridge matches with the Rainbow-G6, but I don't know about the SuperIO of it, there is just a "-" in the list of supported motherboards for superIO of Rainbow-G6.. Thanks in advance, Alp 2011/10/5 Myles Watson <mylesgw(a)gmail.com> > 2011/10/5 Alp Eren Köse <alperenkose(a)buyutech.com.tr>: > > Anyone has an idea? > > > > Another question is I can't find my mainboard vendor "Axiomtek" in > Mainboard > > Vendor selection list in menuconfig as expectedly, but all the chips and > > chipset of it seem to be supported as I see them in coreboot website. Is > it > > still possible to install coreboot, if so how can I do it? > > It would be really nice if someone could point a way.. > > Generally the steps are: > 1. Make sure you can recover from a bad image (extra flash chip with > the original BIOS) > 2. Make sure you can get serial output > 3. Choose the most similar supported motherboard > 4. Change the code to support your board > 5. Try it > 6. Iterate on 4&5 until you're happy with it > 7. Send a patch > > If you don't have 1 & 2 you shouldn't try at all. > > Good luck! > Myles >

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coreboot October 2011