coreboot October 2011

coreboot@coreboot.org

46 participants
501 discussions

Patch set updated for coreboot: eb837a7 sb800: Add sata ahci/raid mode kconfig option
by Kerry Sheh 10 Oct '11

10 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/225 -gerrit commit eb837a74ad78ed6d98ba0799f7ed2ed8475b1fd5 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Mon Oct 10 17:17:39 2011 +0800 sb800: Add sata ahci/raid mode kconfig option If sb800 sata was configured as ahci or raid mode, give the option to add ROM files. Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 66 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 18 +++++++ 2 files changed, 84 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 681c881..b7ac0db 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,8 +28,74 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +choice + prompt "SATA Mode" + default SB800_SATA_IDE + help + Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. + The default is NATIVE. + +config SB800_SATA_IDE + bool "NATIVE" + help + NATIVE is the default mode and does not require a ROM. + +config SB800_SATA_AHCI + bool "AHCI" + help + AHCI may work with or without AHCI ROM. It depends on the payload support. + For example, seabios does not require the AHCI ROM. + +config SB800_SATA_RAID + bool "RAID" + help + sb800 RAID mode must have the two required ROM files. + +endchoice + +config SB800_SATA_MODE + hex + depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) + default "0x0" if SB800_SATA_IDE + default "0x1" if SB800_SATA_RAID + default "0x2" if SB800_SATA_AHCI + config SB_SUPERIO_HWM bool default n + +if SB800_SATA_AHCI +config AHCI_ROM_ID + string "AHCI device PCI IDs" + default "1002,4391" + +config SB800_AHCI_ROM + bool "Add a AHCI ROM" + +config AHCI_ROM_FILE + string "AHCI ROM path and filename" + depends on SB800_AHCI_ROM + default "site-local/sb800/ahci.bin" +endif + +if SB800_SATA_RAID +config RAID_ROM_ID + string "RAID device PCI IDs" + default "1002,4393" + help + 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode + +config RAID_ROM_FILE + string "RAID ROM path and filename" + depends on SB800_SATA_RAID + default "site-local/sb800/raid.bin" + +config RAID_MISC_ROM_FILE + string "RAID Misc ROM path and filename" + default "site-local/sb800/misc.bin" + depends on SB800_SATA_RAID + +endif + endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index acc5fdf..30c0d39 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -31,4 +31,22 @@ ramstage-y += late.c driver-y += smbus.c driver-y += lpc.c +ifeq ($(CONFIG_SB800_SATA_AHCI), y) +ifdef CONFIG_SB800_AHCI_ROM + stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) + cbfs-files-y += pci$(stripped_ahci_rom_id).rom + pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) + pci$(stripped_ahci_rom_id).rom-type := optionrom +endif +endif +ifeq ($(CONFIG_SB800_SATA_RAID), y) + stripped_raid_rom_id = $(call strip_quotes,$(CONFIG_RAID_ROM_ID)) + cbfs-files-y += pci$(stripped_raid_rom_id).rom + pci$(stripped_raid_rom_id).rom-file := $(call strip_quotes,$(CONFIG_RAID_ROM_FILE)) + pci$(stripped_raid_rom_id).rom-type := optionrom + + cbfs-files-y += raid/misc.bin + raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE)) + raid/misc.bin-type := raw +endif

1 0

Patch set updated for coreboot: 701e1e7 persimmon: sb800 sata mode configure update
by Kerry Sheh 10 Oct '11

10 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/227 -gerrit commit 701e1e7d68150ce9d31bca103501aea50b300e65 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Sun Oct 9 14:24:44 2011 +0800 persimmon: sb800 sata mode configure update persimmon configure sb800 sata mode according to the southbridge kconfig selection. Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/persimmon/platform_cfg.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 5e3c3f4..e4fedd9 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -103,7 +103,7 @@ * @breif INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE AHCI_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @breif INCHIP Sata IDE Controller Mode

1 0

Patch set updated for coreboot: dd211b4 sb800: sata combine mode configure fix
by Kerry Sheh 10 Oct '11

10 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/229 -gerrit commit dd211b4537f4122403b20a9e8cf568a81e617cd8 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Sun Oct 9 14:25:54 2011 +0800 sb800: sata combine mode configure fix Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to configure SataIdeCombinedMode is wrong. sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller 0: IDE controller is exposed and Combined Mode is enabled. SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5 1: IDE controller is hidden and Combined Mode is disabled, SATA controller has full control of all 6 Ports when operating in non-IDE mode Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/vendorcode/amd/cimx/sb800/SATA.c | 4 ++-- src/vendorcode/amd/cimx/sb800/SBTYPE.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 1c0e7e6..b7bbacd 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -470,7 +470,7 @@ sataInitAfterPciEnum ( if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { // RIAD or AHCI - if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. @@ -631,7 +631,7 @@ sataInitLatePost ( //Enable write access to pci header, pm capabilities RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); -// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); // } sataBar5setting (pConfig, &ddBar5); diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index b8278cf..f8e825e 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -1106,6 +1106,16 @@ typedef unsigned int CIM_STATUS; */ #define CIMX_OPTION_ENABLED 1 +/** + * SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode + */ +#define SATA_IDE_COMBINE_ENABLE 0 + +/** + * SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode + */ +#define SATA_IDE_COMBINE_DISABLE 1 + // mov al, code // out 80h, al // jmp $

1 0

Patch set updated for coreboot: f14ebb9 sb800: Update entry point of sb_Before_Pci_Init
by Kerry Sheh 10 Oct '11

10 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/230 -gerrit commit f14ebb9af7d47bae97b37158664c64448db442c9 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Sun Oct 9 14:25:56 2011 +0800 sb800: Update entry point of sb_Before_Pci_Init Formally sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 6 ++++++ src/northbridge/amd/agesa/family14/northbridge.c | 3 +++ src/northbridge/amd/amdfam10/northbridge.c | 3 +++ src/southbridge/amd/cimx/sb800/late.c | 3 --- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b3e4c63..b347469 100755 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -38,6 +38,9 @@ #include <Porting.h> #include <AGESA.h> #include <Options.h> +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif #include "root_complex/chip.h" #include "northbridge.h" #include "amdfam10.h" @@ -775,6 +778,9 @@ static void amdfam10_domain_read_resources(device_t dev) { unsigned reg; +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b2ca256..712145b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -488,6 +488,9 @@ static void domain_read_resources(device_t dev) unsigned reg; printk(BIOS_DEBUG, "\nFam14h - domain_read_resources.\n"); +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 89bd673..33843b8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -634,6 +634,9 @@ static void amdfam10_domain_read_resources(device_t dev) { unsigned reg; +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b581212..d0e752f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -418,9 +418,6 @@ static void sb800_enable(device_t dev) break; case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; - - /* the last sb800 device */ - sb_Before_Pci_Init(); break; default:

1 0

Patch set updated for coreboot: 6944d47 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
by Kerry Sheh 10 Oct '11

10 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/231 -gerrit commit 6944d473008bd12414d18b171240703346133653 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Sun Oct 9 14:26:21 2011 +0800 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE Add this option to enable/disable SATA IDE Combined Mode feature Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 16 ++++++++++++++++ src/southbridge/amd/cimx/sb800/cfg.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 5 ----- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index dc4dd7a..1370e7e 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +config ENABLE_IDE_COMBINED_MODE + bool "Enable SATA IDE combined mode" + default n + help + If Combined Mode is enabled. IDE controller is exposed and + SATA controller has control over Port0 through Port3, + IDE controller has control over Port4 and Port5. + + If Combined Mode is disabled, IDE controller is hidden and + SATA controller has full control of all 6 Ports when operating in non-IDE mode. + +config IDE_COMBINED_MODE + hex + default "0x0" if ENABLE_IDE_COMBINED_MODE + default "0x1" if !ENABLE_IDE_COMBINED_MODE + choice prompt "SATA Mode" default SB800_SATA_IDE diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a7801a8..a34dd14 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. //TODO: set to secondary not take effect. - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; /* Azalia HDA */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index d0e752f..74f952a 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -343,11 +343,6 @@ static void sb800_enable(device_t dev) break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ - if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; - } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; - } break; case (0x14 << 3) | 2: /* 0:14:2 HDA */

1 0

Patch set updated for coreboot: dc8722c persimmon: Add usb3 dev in devicetree
by Kerry Sheh 10 Oct '11

10 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/232 -gerrit commit dc8722c6d48a18ad82e8a4b2cc9afb8d6cfc25ec Author: Kerry Sheh <shekairui(a)gmail.com> Date: Mon Oct 10 14:36:25 2011 +0800 persimmon: Add usb3 dev in devicetree The sb800 southbridge requires the usb3 devices in the devicetree, Persimmon doesn't have the connector, so they are off. Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/persimmon/devicetree.cb | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 7da2169..fe87bca 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -87,6 +87,8 @@ chip northbridge/amd/agesa/family14/root_complex device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI-USB3 + device pci 16.2 off end # UHCI-USB3 register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800

1 0

Re: [coreboot] Issues with Supermicro H8SCM
by She, Kerry 09 Oct '11

09 Oct '11

Hello, Thomas > -----Original Message----- > From: coreboot-bounces+kerry.she=amd.com(a)coreboot.org [mailto:coreboot- > bounces+kerry.she=amd.com(a)coreboot.org] On Behalf Of Marc Jones > Sent: Saturday, October 08, 2011 3:45 AM > To: Thomas Gstädtner > Cc: coreboot > Subject: Re: [coreboot] Issues with Supermicro H8SCM > > On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gstädtner <thomas(a)gstaedtner.net> > wrote: > > On Wed, Oct 5, 2011 at 20:08, Marc Jones <marcj303(a)gmail.com> wrote: > >> On Tue, Oct 4, 2011 at 5:26 PM, Thomas Gstädtner > <thomas(a)gstaedtner.net> wrote: > >>> Hi everyone, > >>> > >>> I own a Supermicro H8SCM-F-O mainboard (AMDs SP5100 Chipset), one of > >>> the boards AMD as of recently claims to officially support. > >>> So I decided to try coreboot, but (as expected) it is not really an > >>> out-of-the-box experience. > >>> > >>> First of all, flashrom does not support flashing out-of-the-box, but > >>> Frederic Temporelli's patches ( > >>> http://patchwork.coreboot.org/patch/3326/ and > >>> http://patchwork.coreboot.org/patch/3326/ ) work fine for me (I > tested > >>> multiple reads and multiple writes, always worked), I can report that > >>> to the flashrom list separately if you want. > >>> > >>> I built coreboot from the gerrit-branch (also tried a "stable" > >>> revision), coreboot-4.0-1714-gf8adf7a, using the "default" > >>> board-config incl. seabios (stable) as payload. > >>> After powering on nothing happens (apart from the fans running and > the > >>> power led flashing) and it stays that way, it is silent on VGA as > well > >>> as serial. > >>> After manually triggering a reset I immediately get the following > >>> output on serial: > >>> > >>> coreboot-4.0-1714-gf8adf7a Wed Oct 5 00:31:05 CEST 2011 starting... > >>> BSP Family_Model: > >>> > >>> Here it hangs, and I don't quite know how to move on and debug the > issue. > >>> > >>> Can you give me any hints where to go on from here? I have external > >>> flashing equipment at hand (which also works fine btw.), but no fancy > >>> bios-debugging hardware. > >>> > >>> Regards, > >>> > >>> thomasg > >>> > >>> P.S. In case anyone else stumbles upon it: the board has 2 separate > >>> flash chips, one Macronix MX25L12845E with 128 Mbit (the SOIC16W > >>> package on the left of the board) as well as a SST25VF016B, 16 Mbit, > >>> as the SOIC8W on the right. The first one holds the IPMI firmware, > the > >>> second one the AMI BIOS. > >>> Flashing requires a testclip or some really serious soldering skills. > >>> Attaching a SO8 socket can only be done with hot air soldering. > >> > >> Hi Thomas, > >> > >> Thanks for the report. While many people overlap with the flashrom > >> list, please post about those patches on that list. Seems that you > >> should be able to ack them. > >> > >> It looks like maybe the platform build doesn't support your CPU. > >> There have been a number of recent contributions from AMD, but they > >> don't all align with the platform contributions. So, the H8SCM should > >> support all fam10 revD, but may have issue with Fam10 rev E. To get > >> more information, you can turn the console debug output to SPEW in > >> menuconfig. > >> > >> Marc > >> > >> > >> > >> -- > >> http://se-eng.com > >> > > > > Thanks for the advice Marc, > > > > I already had the loglevel set to spew (8). I additionally tried the > > other "Verbose output" debugging options, unfortunately I don't get > > any output at all when they are built in. > > Also, while it is hard to find and AMD doesn't have any official > > document confirming this, according to some google hits the processor > > should be revision D1 not rev E (AMD model number: OS4170OFU6DGOWOF ). I also found the latest code not boot on my H8SCM-F mainboard with Rev D1 processor. So I have made some update to using the AGESA wrapper framework, the attachment is some of my update, with this series of patches applied, we can boot to Debian Linux Destop or Windows Server 2008 R2 standard edition. Thanks > > > > (Sry for sending the mail twice, hit the wrong button) > > > > Oh, I just recalled something about the H8SCM. There is jumper to > disable the bmc which might have a watchdog that coreboot can't deal > with. Did you disable that? > > Marc > > > -- > http://se-eng.com > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

2 1

Patch set updated for coreboot: 1a3976e sb800: Add sata ahci/raid mode kconfig option
by Kerry Sheh 09 Oct '11

09 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/225 -gerrit commit 1a3976e5ab189193ece8114ac533b00af6f9a293 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Sun Oct 9 14:18:28 2011 +0800 sb800: Add sata ahci/raid mode kconfig option If sb800 sata was configured as ahci or raid mode, locate the corresponding option rom at site-local directory by default. Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 59 ++++++++++++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 681c881..dc4dd7a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,8 +28,67 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +choice + prompt "SATA Mode" + default SB800_SATA_IDE + help + Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. + The default is NATIVE. + +config SB800_SATA_IDE + bool "NATIVE" + +config SB800_SATA_AHCI + bool "AHCI" + +config SB800_SATA_RAID + bool "RAID" +endchoice + +config SB800_SATA_MODE + hex + depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) + default "0x0" if SB800_SATA_IDE + default "0x1" if SB800_SATA_RAID + default "0x2" if SB800_SATA_AHCI + config SB_SUPERIO_HWM bool default n + +if SB800_SATA_AHCI +config AHCI_ROM_ID + string "AHCI device PCI IDs" + default "1002,4391" + +config AHCI_ROM_FILE + string "AHCI ROM path and filename" + default "site-local/sb800/ahci.bin" +endif + +if SB800_SATA_RAID +config RAID_ROM_ID + string "RAID device PCI IDs" + default "1002,4393" + help + 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode + +config RAID_ROM_FILE + string "RAID ROM path and filename" + default "site-local/sb800/raid.bin" + +config RAID_MISC_ROM + bool + default y + help + SB800 Promisc RAID Option ROM misc binary + +config RAID_MISC_ROM_FILE + string "RAID Misc ROM path and filename" + default "site-local/sb800/misc.bin" + depends on RAID_MISC_ROM + +endif + endif #SOUTHBRIDGE_AMD_CIMX_SB800

1 0

Patch set updated for coreboot: 16b2ad3 persimmon: sb800 sata mode configure update
by Kerry Sheh 09 Oct '11

09 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/227 -gerrit commit 16b2ad39712307be5235bb0a00e501339f0afef1 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Sun Oct 9 14:24:44 2011 +0800 persimmon: sb800 sata mode configure update persimmon configure sb800 sata mode according to the southbridge kconfig selection. Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/persimmon/platform_cfg.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 5e3c3f4..e4fedd9 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -103,7 +103,7 @@ * @breif INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE AHCI_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @breif INCHIP Sata IDE Controller Mode

1 0

Patch set updated for coreboot: 84b249e sb800: sata combine mode configure fix
by Kerry Sheh 09 Oct '11

09 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/229 -gerrit commit 84b249e7750d850f524c68788708be7c9b7942e4 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Sun Oct 9 14:25:54 2011 +0800 sb800: sata combine mode configure fix Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to configure SataIdeCombinedMode is wrong. sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller 0: IDE controller is exposed and Combined Mode is enabled. SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5 1: IDE controller is hidden and Combined Mode is disabled, SATA controller has full control of all 6 Ports when operating in non-IDE mode Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/vendorcode/amd/cimx/sb800/SATA.c | 4 ++-- src/vendorcode/amd/cimx/sb800/SBTYPE.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 1c0e7e6..b7bbacd 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -470,7 +470,7 @@ sataInitAfterPciEnum ( if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { // RIAD or AHCI - if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. @@ -631,7 +631,7 @@ sataInitLatePost ( //Enable write access to pci header, pm capabilities RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); -// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); // } sataBar5setting (pConfig, &ddBar5); diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index b8278cf..f8e825e 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -1106,6 +1106,16 @@ typedef unsigned int CIM_STATUS; */ #define CIMX_OPTION_ENABLED 1 +/** + * SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode + */ +#define SATA_IDE_COMBINE_ENABLE 0 + +/** + * SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode + */ +#define SATA_IDE_COMBINE_DISABLE 1 + // mov al, code // out 80h, al // jmp $

1 0

← Newer
1
...
42
43
44
45
46
47
48
...
51
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2011