coreboot October 2011

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Patch merged into coreboot/master: 2e6a214 persimmon: complete the sb800 devicetree
by gerrit＠coreboot.org 12 Oct '11

12 Oct '11

the following patch was just integrated into master: commit 2e6a214fe93272b99f7bbb0c6786d8392653f412 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 17:27:00 2011 +0800 persimmon: complete the sb800 devicetree sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. So the missing sb800 USB3 devicees was add to the mainboard devicetree. Because of no physical usb connector connected to USB3, the USB3 device setting was off. Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/232 for details. -gerrit

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Re: [coreboot] Issues with Supermicro H8SCM
by Marc Jones 12 Oct '11

12 Oct '11

On Tue, Oct 11, 2011 at 6:17 AM, Thomas Gstädtner <thomas(a)gstaedtner.net> wrote: > On Tue, Oct 11, 2011 at 12:41, She, Kerry <Kerry.She(a)amd.com> wrote: >> Hello, Thomas >> >>> -----Original Message----- >>> From: Thomas Gstädtner [mailto:thomas@gstaedtner.net] >>> Sent: Sunday, October 09, 2011 11:53 PM >>> To: She, Kerry >>> Cc: Marc Jones; coreboot >>> Subject: Re: [coreboot] Issues with Supermicro H8SCM >>> >>> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She(a)amd.com> wrote: >>> > Hello, Thomas >>> > >>> >> -----Original Message----- >>> >> From: coreboot-bounces+kerry.she=amd.com(a)coreboot.org >>> >> [mailto:coreboot- >>> >> bounces+kerry.she=amd.com(a)coreboot.org] On Behalf Of Marc Jones >>> >> Sent: Saturday, October 08, 2011 3:45 AM >>> >> To: Thomas Gstädtner >>> >> Cc: coreboot >>> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM >>> >> >>> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gstädtner >>> >> <thomas(a)gstaedtner.net> >>> >> wrote: >>> >> > >>> >> > Thanks for the advice Marc, >>> >> > >>> >> > I already had the loglevel set to spew (8). I additionally tried >>> >> > the other "Verbose output" debugging options, unfortunately I don't >>> >> > get any output at all when they are built in. >>> >> > Also, while it is hard to find and AMD doesn't have any official >>> >> > document confirming this, according to some google hits the >>> >> > processor should be revision D1 not rev E (AMD model number: >>> OS4170OFU6DGOWOF ). >>> > >>> > I also found the latest code not boot on my H8SCM-F mainboard with Rev >>> D1 processor. >>> > So I have made some update to using the AGESA wrapper framework, the >>> > attachment is some of my update, with this series of patches applied, >>> > we can boot to Debian Linux Destop or Windows Server 2008 R2 standard >>> > edition. >>> > Thanks >>> > >>> >>> Hi Kerry, >>> >>> first of all: thanks for your effort! >>> While I had no success at first, I now can get to the boot prompt >>> (haven't tried any further yet). >>> >>> Anyway, I currently have 2 DIMMs, each 4 GiB. >>> A dual-channel configuration does not seem to work, the DIMMs are >>> detected, but coreboot throws an "ASSERTION FAILED" error (see attached >>> log cb_h8scm_01.log). >>> It seems to fail because it somehow seems to think no DIMM is found >>> (despite both DIMMs being detected). I tried disabling this check, but >>> this only leads to a reset. >>> The same problem exists with a single-DIMM configuration. >>> >>> However, when I switch to a dual-DIMM, single-channel config, it at first >>> does not start at all (i.e. no output on serial and no heartbeat from the >>> BMC) - but when I trigger a manual reset it immediately starts up (see >>> attached log cb_h8scm_dimma1a2_success.log). >>> >>> I'll report back when I find out more. >> >> >> I have only test with 4 Registered ECC DIMMs, so I can confirm dual DIMMs in one channel should works, >> It seems that the DRAM training has some problem for single DIMM on one channel situation. >> Thanks >> Kerry >> > > I unfortunately only have 2 registered DIMMs, so I can't test a dual > channel configuration, but yes, seems 1 DIMM per Channel does not work > at all. > > Anyway, I built a rom with vga bios included and can boot to FILO > prompt or SeaBIOS. So far USB is not working, neither the attached USB > keybord, nor the USB flashdrive I wanted to boot from. > A related warning seems to be: "WARNING - Timeout at > ehci_wait_qh:319!", might try to disable ehci to see if ohci works. > > Also, it seems it now starts up most of the time immediately, > approximately 1 out of 5 times it needs a manual reset after powering > up. > Time from power-on to FILO prompt is about 2 seconds with loglevel 3 > (over serial, via VGA I can't tell, it's ready long before the display > makes it from wake-up to active). > > So in short, > What Works: All 6 CPU cores are detected, clock is correct, VGA, > Serial, SeaBIOS and FILO > What Doesn't: USB/EHCI, Single-DIMM per Channel, reliable bootup > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Hi Tomas This is great feedback. Maybe you can narrow down the boot failure. Is it in coreboot, payload, or Linux when it fails? Kerry, Please add this info to the wiki for this board. Thanks, Marc -- http://se-eng.com

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FILO fails to build via coreboot
by Thomas Gstädtner 11 Oct '11

11 Oct '11

Hi everyone, FILO (0.6 and SVN tested) fails to build as a coreboot payload with the following error: MAKE FILO HEAD Found Libpayload /home/thomasg/sources/coreboot/payloads/external/FILO/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o CC build/main/filo.o CC build/main/strtox.o CC build/main/elfload.o CC build/main/ipchecksum.o CC build/main/grub/grub.o CC build/main/grub/builtins.o /home/thomasg/sources/coreboot/payloads/external/FILO/filo/main/grub/builtins.c:456:2: warning: #warning "FIND not implemented yet." CC build/main/grub/cmdline.o CC build/main/grub/char_io.o CC build/main/grub/completions.o CC build/main/grub/md5.o CC build/fs/blockdev.o CC build/fs/vfs.o CC build/fs/eltorito.o CC build/fs/fsys_ext2fs.o CC build/fs/fsys_fat.o CC build/fs/fsys_reiserfs.o CC build/fs/fsys_iso9660.o CC build/fs/fsys_cbfs.o CC build/fs/cbfs.o /home/thomasg/sources/coreboot/payloads/external/FILO/filo/fs/cbfs.c:113:20: error: conflicting types for ‘cbfs_find_file’ /home/thomasg/sources/coreboot/payloads/external/FILO/filo/build/libpayload/include/cbfs_core.h:175:7: note: previous declaration of ‘cbfs_find_file’ was here make[2]: *** [/home/thomasg/sources/coreboot/payloads/external/FILO/filo/build/fs/cbfs.o] Error 1 make[1]: *** [filo] Error 2 make: *** [filo] Error 2 The reason is, that cbfs_find_file is defined in coreboot as "void *cbfs_find_file(const char *name, int type)" while FILO defines it as "struct cbfs_stage *cbfs_find_file(const char *name, int type)". As far as I can tell it works either way as the void is cast to the right type where used, but I assume it got changed somewhere for a reason, I just don't know which way it should be. I could provide a patch, but I suggest that someone who actually knows the code take a look. If you need any more information, let me know. thomasg

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Re: [coreboot] Issues with Supermicro H8SCM
by She, Kerry 11 Oct '11

11 Oct '11

Hello, Thomas > -----Original Message----- > From: Thomas Gstädtner [mailto:thomas@gstaedtner.net] > Sent: Sunday, October 09, 2011 11:53 PM > To: She, Kerry > Cc: Marc Jones; coreboot > Subject: Re: [coreboot] Issues with Supermicro H8SCM > > On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She(a)amd.com> wrote: > > Hello, Thomas > > > >> -----Original Message----- > >> From: coreboot-bounces+kerry.she=amd.com(a)coreboot.org > >> [mailto:coreboot- > >> bounces+kerry.she=amd.com(a)coreboot.org] On Behalf Of Marc Jones > >> Sent: Saturday, October 08, 2011 3:45 AM > >> To: Thomas Gstädtner > >> Cc: coreboot > >> Subject: Re: [coreboot] Issues with Supermicro H8SCM > >> > >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gstädtner > >> <thomas(a)gstaedtner.net> > >> wrote: > >> > > >> > Thanks for the advice Marc, > >> > > >> > I already had the loglevel set to spew (8). I additionally tried > >> > the other "Verbose output" debugging options, unfortunately I don't > >> > get any output at all when they are built in. > >> > Also, while it is hard to find and AMD doesn't have any official > >> > document confirming this, according to some google hits the > >> > processor should be revision D1 not rev E (AMD model number: > OS4170OFU6DGOWOF ). > > > > I also found the latest code not boot on my H8SCM-F mainboard with Rev > D1 processor. > > So I have made some update to using the AGESA wrapper framework, the > > attachment is some of my update, with this series of patches applied, > > we can boot to Debian Linux Destop or Windows Server 2008 R2 standard > > edition. > > Thanks > > > > Hi Kerry, > > first of all: thanks for your effort! > While I had no success at first, I now can get to the boot prompt > (haven't tried any further yet). > > Anyway, I currently have 2 DIMMs, each 4 GiB. > A dual-channel configuration does not seem to work, the DIMMs are > detected, but coreboot throws an "ASSERTION FAILED" error (see attached > log cb_h8scm_01.log). > It seems to fail because it somehow seems to think no DIMM is found > (despite both DIMMs being detected). I tried disabling this check, but > this only leads to a reset. > The same problem exists with a single-DIMM configuration. > > However, when I switch to a dual-DIMM, single-channel config, it at first > does not start at all (i.e. no output on serial and no heartbeat from the > BMC) - but when I trigger a manual reset it immediately starts up (see > attached log cb_h8scm_dimma1a2_success.log). > > I'll report back when I find out more. I have only test with 4 Registered ECC DIMMs, so I can confirm dual DIMMs in one channel should works, It seems that the DRAM training has some problem for single DIMM on one channel situation. Thanks Kerry

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Re: [coreboot] make crossgcc fails with 'Building IASL 20110623 ... failed'
by Stefan Reinauer 11 Oct '11

11 Oct '11

On 10/10/11 9:02 AM, Alp Eren Köse wrote: > As written on the subject 'make crossgcc' fails as following: > Skipping GDB as requested by command line > Building IASL 20110623 ... failed > make[1]: *** [build-without-gdb] Error 1 > make: *** [crossgcc] Error 2 > > Anyone knows why? > and the > "util/crossgcc/acpica-unix-20110623/compiler/crossgcc-build.log" file > is at the attachment. > > complete output below: > > Welcome to the coresystems cross toolchain builder v1.04 (August 8th, > 2011) > > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.0.1.tar.bz2 (downloading) > * mpfr-3.0.0.tar.bz2 (downloading) > * mpc-0.8.2.tar.gz (downloading) > * libelf-0.8.13.tar.gz (downloading) > * gcc-core-4.5.2.tar.bz2 (downloading) > * binutils-2.20.1.tar.bz2 (downloading) > * acpica-unix-20110623.tar.gz (downloading) > Downloaded tar balls ... ok > Unpacking and patching ... > * gmp-5.0.1.tar.bz2 > * mpfr-3.0.0.tar.bz2 > o mpfr-3.0.0_allpatches_20101216.patch > * mpc-0.8.2.tar.gz > * libelf-0.8.13.tar.gz > * gcc-core-4.5.2.tar.bz2 > o gcc-4.5.2_pragma.patch > * binutils-2.20.1.tar.bz2 > o binutils-2.20.1_no-bfd-doc.patch > * acpica-unix-20110623.tar.gz > Unpacked and patched ... ok > Building GMP 5.0.1 ... ok > Building MPFR 3.0.0 ... ok > Building MPC 0.8.2 ... ok > Building libelf 0.8.13 ... ok > Building binutils 2.20.1 ... ok > Building GCC 4.5.2 ... ok > Skipping GDB as requested by command line > Building IASL 20110623 ... failed > make[1]: *** [build-without-gdb] Error 1 > make: *** [crossgcc] Error 2 > Sounds like $(CC) is not set for some reason?

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Patch set updated for coreboot: b4b90b6 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/249 -gerrit commit b4b90b6a6feece0ff9a911ca2e41653d2ba94092 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 18:54:54 2011 +0800 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION SB800 RAID ROM require to put the misc ROM to specific position, this patch enable user to put the RAID misc ROM to the right place in the coreboot image. Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 9 +++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 1 + 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 17ff3f9..41a167a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -111,6 +111,15 @@ config RAID_MISC_ROM_FILE default "site-local/sb800/misc.bin" depends on SB800_SATA_RAID +config RAID_MISC_ROM_POSITION + hex "RAID Misc ROM Position" + default 0xFFF00000 + depends on SB800_SATA_RAID + help + RAID ROM require to put the misc ROM at range from 0xFFF0_0000 to + 0xFFF0_FFFF, and must 1K bytes aligned. + So CONFIG_ROM_SIZE must larger than 0x100000. + endif endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30c0d39..48b198d 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -48,5 +48,6 @@ ifeq ($(CONFIG_SB800_SATA_RAID), y) cbfs-files-y += raid/misc.bin raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE)) + raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION) raid/misc.bin-type := raw endif

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Patch set updated for coreboot: c20defe SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/248 -gerrit commit c20defe1c19d01f86ee53d013b00c352ec445eca Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 18:54:48 2011 +0800 SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode In order to make sure AHCI/RAID ROM works correctly For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should enable bus master and the ahci also should be enabled. Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/include/device/pci_ids.h | 1 + src/southbridge/amd/cimx/sb800/late.c | 56 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 2 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 390a42a..d16f85e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -15,6 +15,7 @@ #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_SATA 0x0106 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_BASE_CLASS_NETWORK 0x02 diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b78f1ce..6fa3dcf 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -74,6 +74,47 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config) return ret; } +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ + +#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ +static void ahci_raid_init(struct device *dev) +{ + u8 irq = 0; + u32 bar5, caps, ports, val; + + val = pci_read_config16(dev, PCI_CLASS_DEVICE); + if (val == PCI_CLASS_STORAGE_SATA) { + printk(BIOS_DEBUG, "AHCI controller "); + } else if (val == PCI_CLASS_STORAGE_RAID) { + printk(BIOS_DEBUG, "RAID controller "); + } else { + printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); + return; + } + + irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); + bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); + + caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = (caps & 0x1F) + 1; + ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); + + //dev->command = pci_read_config8(dev, PCI_COMMAND); + dev->command |= PCI_COMMAND_MASTER; + pci_write_config8(dev, PCI_COMMAND, dev->command); + + /* make sure ahci is enabled */ + val = *(volatile u32 *)(bar5 + HOST_CTL); + if (!(val & HOST_CTL_AHCI_EN)) { + *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + } + printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); +} static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, @@ -98,17 +139,28 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = ahci_raid_init, .scan_bus = 0, .ops_pci = &lops_pci, }; -static const struct pci_driver sata_driver __pci_driver = { +static const struct pci_driver ahci_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, }; +static const struct pci_driver raid_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, +}; +static const struct pci_driver raid5_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, +}; + #if CONFIG_USBDEBUG == 1 static void usb_set_resources(struct device *dev) {

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Patch set updated for coreboot: c098e66 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/231 -gerrit commit c098e66cd2aff9089afde58fc37226a3dff220fe Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 17:27:06 2011 +0800 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE Add this option to enable/disable SATA IDE Combined Mode feature Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 16 ++++++++++++++++ src/southbridge/amd/cimx/sb800/cfg.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 5 ----- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index b7ac0db..17ff3f9 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +config ENABLE_IDE_COMBINED_MODE + bool "Enable SATA IDE combined mode" + default n + help + If Combined Mode is enabled. IDE controller is exposed and + SATA controller has control over Port0 through Port3, + IDE controller has control over Port4 and Port5. + + If Combined Mode is disabled, IDE controller is hidden and + SATA controller has full control of all 6 Ports when operating in non-IDE mode. + +config IDE_COMBINED_MODE + hex + default "0x0" if ENABLE_IDE_COMBINED_MODE + default "0x1" if !ENABLE_IDE_COMBINED_MODE + choice prompt "SATA Mode" default SB800_SATA_IDE diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a7801a8..a34dd14 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. //TODO: set to secondary not take effect. - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; /* Azalia HDA */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index c36ee03..b78f1ce 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -343,11 +343,6 @@ static void sb800_enable(device_t dev) break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ - if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; - } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; - } break; case (0x14 << 3) | 2: /* 0:14:2 HDA */

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Patch set updated for coreboot: 2e6a214 persimmon: complete the sb800 devicetree
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/232 -gerrit commit 2e6a214fe93272b99f7bbb0c6786d8392653f412 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 17:27:00 2011 +0800 persimmon: complete the sb800 devicetree sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. So the missing sb800 USB3 devicees was add to the mainboard devicetree. Because of no physical usb connector connected to USB3, the USB3 device setting was off. Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/persimmon/devicetree.cb | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 7da2169..b47e6b9 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -87,6 +87,8 @@ chip northbridge/amd/agesa/family14/root_complex device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800

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Patch set updated for coreboot: 6607c70 avalue/eax-785e: Get SATA Mode from Kconfig option
by Kerry Sheh 11 Oct '11

11 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/233 -gerrit commit 6607c70b9e63e53ba1657118b5808a7c3c76ca28 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 17:27:26 2011 +0800 avalue/eax-785e: Get SATA Mode from Kconfig option Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/avalue/eax-785e/platform_cfg.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index 24dcae0..e503585 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -103,7 +103,7 @@ * @breif INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @breif INCHIP Sata IDE Controller Mode

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coreboot October 2011