coreboot October 2011

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501 discussions

missing read resources
by Oskar Enoksson 12 Oct '11

12 Oct '11

I get the following warnings: APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources I2C: 01:08 missing read_resources I2C: 04:50 missing read_resources I2C: 04:51 missing read_resources I2C: 04:52 missing read_resources I2C: 04:53 missing read_resources I2C: 05:50 missing read_resources I2C: 05:51 missing read_resources I2C: 05:52 missing read_resources I2C: 05:53 missing read_resources I2C: 03:69 missing read_resources What does it mean? Should I do something about it in devicetree.cb?

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Patch merged into coreboot/master: 94e9f37 w83627hf: ASL include containing virtual device tree of the SuperIO
by gerrit＠coreboot.org 12 Oct '11

12 Oct '11

the following patch was just integrated into master: commit 94e9f377664dbb9b49aa80ff47aa7ae3b7d78c34 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Sun Sep 18 22:53:18 2011 +0200 w83627hf: ASL include containing virtual device tree of the SuperIO Add a ACPI Source Language snippet to superio/w83627hf which maps the SuperIO and most of the logical devices to PnP devices, exposing configuration options and chip power management to the OS. Written using the Winbond W83627HF/F datasheet. Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> See http://review.coreboot.org/223 for details. -gerrit

1 0

Patch merged into coreboot/master: 6803e54 amdk8: ASL include for K8 temperature sensor support in ACPI
by gerrit＠coreboot.org 12 Oct '11

12 Oct '11

the following patch was just integrated into master: commit 6803e546d97b07d01845e3be2708e99d09591378 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Sun Sep 18 23:20:55 2011 +0200 amdk8: ASL include for K8 temperature sensor support in ACPI Add a ACPI Source Language snippet which if included as shown in the comments in the file, exposes the 4 possible temperature sensors in the CPU as ACPI thermal zones. Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> See http://review.coreboot.org/222 for details. -gerrit

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Patch merged into coreboot/master: cf271c1 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
by gerrit＠coreboot.org 12 Oct '11

12 Oct '11

the following patch was just integrated into master: commit cf271c1a7851527c035e3f2061abfba7ade6d475 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Oct 12 11:42:59 2011 +0800 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION SB800 RAID ROM require to put the misc ROM to specific position, this patch enable user to put the RAID misc ROM to the right place in the coreboot image. Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> See http://review.coreboot.org/249 for details. -gerrit

1 0

Patch merged into coreboot/master: a9f89fe SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
by gerrit＠coreboot.org 12 Oct '11

12 Oct '11

the following patch was just integrated into master: commit a9f89fe8ff733c2aeb2c6629ede625c4374e2181 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Oct 12 11:42:59 2011 +0800 SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode In order to make sure AHCI/RAID ROM works correctly For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should enable bus master and the ahci also should be enabled. Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> See http://review.coreboot.org/248 for details. -gerrit

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Patch set updated for coreboot: 84aaa51 SB800: Hide unused gpp ports
by Kerry Sheh 12 Oct '11

12 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/207 -gerrit commit 84aaa51051020920f5f42b7ea4c2410693cba36a Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Oct 12 12:06:23 2011 +0800 SB800: Hide unused gpp ports Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/advansus/a785e-i/platform_cfg.h | 6 ++++++ src/mainboard/amd/inagua/platform_cfg.h | 6 ++++++ src/mainboard/amd/persimmon/platform_cfg.h | 6 ++++++ src/mainboard/asrock/e350m1/platform_cfg.h | 6 ++++++ src/southbridge/amd/cimx/sb800/cfg.c | 2 +- 5 files changed, 25 insertions(+), 1 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index ee68386..5fd49d6 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -211,6 +211,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 4a3f080..aa7cb5c 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -213,6 +213,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index e4fedd9..66aab8b 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -213,6 +213,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index a0cbd11..6aa31d2 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -213,6 +213,12 @@ */ #define SB_GPP_GEN2 TRUE +/** + * @def SB_GPP_UNHIDE_PORTS + * TRUE - ports visable always, even port empty + * FALSE - ports invisable if port empty + */ +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a34dd14..2998fa2 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -108,7 +108,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; - sb_config->GppUnhidePorts = TRUE; //visable always, even port empty + sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS; sb_config->NbSbGen2 = NB_SB_GEN2; sb_config->GppGen2 = SB_GPP_GEN2;

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Patch set updated for coreboot: cf271c1 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
by Kerry Sheh 12 Oct '11

12 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/249 -gerrit commit cf271c1a7851527c035e3f2061abfba7ade6d475 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Oct 12 11:42:59 2011 +0800 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION SB800 RAID ROM require to put the misc ROM to specific position, this patch enable user to put the RAID misc ROM to the right place in the coreboot image. Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 9 +++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 1 + 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 17ff3f9..79624e0 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -111,6 +111,15 @@ config RAID_MISC_ROM_FILE default "site-local/sb800/misc.bin" depends on SB800_SATA_RAID +config RAID_MISC_ROM_POSITION + hex "RAID Misc ROM Position" + default 0xFFF00000 + depends on SB800_SATA_RAID + help + The RAID ROM requires that the MISC ROM is located between the range + 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. + The CONFIG_ROM_SIZE must larger than 0x100000. + endif endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30c0d39..48b198d 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -48,5 +48,6 @@ ifeq ($(CONFIG_SB800_SATA_RAID), y) cbfs-files-y += raid/misc.bin raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE)) + raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION) raid/misc.bin-type := raw endif

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Patch set updated for coreboot: a9f89fe SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
by Kerry Sheh 12 Oct '11

12 Oct '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/248 -gerrit commit a9f89fe8ff733c2aeb2c6629ede625c4374e2181 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Oct 12 11:42:59 2011 +0800 SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode In order to make sure AHCI/RAID ROM works correctly For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should enable bus master and the ahci also should be enabled. Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/include/device/pci_ids.h | 1 + src/southbridge/amd/cimx/sb800/late.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 390a42a..d16f85e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -15,6 +15,7 @@ #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_SATA 0x0106 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_BASE_CLASS_NETWORK 0x02 diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b78f1ce..8c7abdb 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -74,6 +74,46 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config) return ret; } +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ + +#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ +static void ahci_raid_init(struct device *dev) +{ + u8 irq = 0; + u32 bar5, caps, ports, val; + + val = pci_read_config16(dev, PCI_CLASS_DEVICE); + if (val == PCI_CLASS_STORAGE_SATA) { + printk(BIOS_DEBUG, "AHCI controller "); + } else if (val == PCI_CLASS_STORAGE_RAID) { + printk(BIOS_DEBUG, "RAID controller "); + } else { + printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); + return; + } + + irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); + bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); + + caps = *(volatile u32 *)(bar5 + HOST_CAP); + caps = (caps & 0x1F) + 1; + ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); + printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); + + /* make sure ahci is enabled */ + val = *(volatile u32 *)(bar5 + HOST_CTL); + if (!(val & HOST_CTL_AHCI_EN)) { + *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; + } + + dev->command |= PCI_COMMAND_MASTER; + pci_write_config8(dev, PCI_COMMAND, dev->command); + printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); +} static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, @@ -98,17 +138,28 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = ahci_raid_init, .scan_bus = 0, .ops_pci = &lops_pci, }; -static const struct pci_driver sata_driver __pci_driver = { +static const struct pci_driver ahci_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, }; +static const struct pci_driver raid_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, +}; +static const struct pci_driver raid5_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, +}; + #if CONFIG_USBDEBUG == 1 static void usb_set_resources(struct device *dev) {

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Patch merged into coreboot/master: 6607c70 avalue/eax-785e: Get SATA Mode from Kconfig option
by gerrit＠coreboot.org 12 Oct '11

12 Oct '11

the following patch was just integrated into master: commit 6607c70b9e63e53ba1657118b5808a7c3c76ca28 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 17:27:26 2011 +0800 avalue/eax-785e: Get SATA Mode from Kconfig option Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/233 for details. -gerrit

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Patch merged into coreboot/master: c098e66 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
by gerrit＠coreboot.org 12 Oct '11

12 Oct '11

the following patch was just integrated into master: commit c098e66cd2aff9089afde58fc37226a3dff220fe Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Oct 11 17:27:06 2011 +0800 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE Add this option to enable/disable SATA IDE Combined Mode feature Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> See http://review.coreboot.org/231 for details. -gerrit

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coreboot October 2011