coreboot October 2011

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New patch to review for coreboot: b296563 refactor vesa mode setting code and bootsplash code
by Stefan Reinauer 13 Oct '11

13 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/256 -gerrit commit b296563878a245bc138fb213f1fb60e04ae1751a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 14:30:59 2011 -0700 refactor vesa mode setting code and bootsplash code - adds possibility to set a vesa mode without showing a bootsplash - make bootsplash / mode setting code available in real mode. Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 46 +++++++------ src/arch/x86/boot/coreboot_table.c | 2 +- src/devices/oprom/include/vbe.h | 8 ++- src/devices/oprom/x86.c | 103 ++++++++++++++++++++++++++-- src/devices/oprom/x86.h | 1 + src/devices/oprom/x86_asm.S | 5 ++ src/devices/oprom/yabel/compat/functions.c | 2 +- src/devices/oprom/yabel/device.c | 2 + src/devices/oprom/yabel/vbe.c | 9 ++- src/lib/fallback_boot.c | 2 +- 10 files changed, 145 insertions(+), 35 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index e9ceed5..525d452 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,40 +516,31 @@ config MBI_FILE endmenu -menu "Bootsplash" - depends on PCI_OPTION_ROM_RUN_YABEL +menu "Display" + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE -config BOOTSPLASH - prompt "Show graphical bootsplash" +config FRAMEBUFFER_SET_VESA_MODE + prompt "Set VESA framebuffer mode" bool - depends on PCI_OPTION_ROM_RUN_YABEL + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE help - This option shows a graphical bootsplash screen. The grapics are - loaded from the CBFS file bootsplash.jpg. - -config BOOTSPLASH_FILE - string "Bootsplash path and filename" - depends on BOOTSPLASH - default "bootsplash.jpg" - help - The path and filename of the file to use as graphical bootsplash - screen. The file format has to be jpg. + Set VESA framebuffer mode (needed for bootsplash) # TODO: Turn this into a "choice". config FRAMEBUFFER_VESA_MODE prompt "VESA framebuffer video mode" hex default 0x117 - depends on BOOTSPLASH + depends on FRAMEBUFFER_SET_VESA_MODE help - This option sets the resolution used for the coreboot framebuffer and - bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will + This option sets the resolution used for the coreboot framebuffer (and + bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will some day make this a "choice". -config COREBOOT_KEEP_FRAMEBUFFER +config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on BOOTSPLASH + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a @@ -557,6 +548,21 @@ config COREBOOT_KEEP_FRAMEBUFFER framebuffer driver. If this option is disabled, coreboot will switch back to text mode before handing control to a payload. +config BOOTSPLASH + prompt "Show graphical bootsplash" + bool + depends on FRAMEBUFFER_SET_VESA_MODE + help + This option shows a graphical bootsplash screen. The grapics are + loaded from the CBFS file bootsplash.jpg. + +config BOOTSPLASH_FILE + string "Bootsplash path and filename" + depends on BOOTSPLASH + default "bootsplash.jpg" + help + The path and filename of the file to use as graphical bootsplash + screen. The file format has to be jpg. endmenu menu "Debugging" diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index db3a8a9..d53a23a 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -148,7 +148,7 @@ static void lb_console(struct lb_header *header) static void lb_framebuffer(struct lb_header *header) { -#if CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER +#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); struct lb_framebuffer *framebuffer; diff --git a/src/devices/oprom/include/vbe.h b/src/devices/oprom/include/vbe.h index b87b0d5..f857b67 100644 --- a/src/devices/oprom/include/vbe.h +++ b/src/devices/oprom/include/vbe.h @@ -104,9 +104,11 @@ typedef struct { struct lb_framebuffer; -void vbe_set_graphics(void); // yabel only - -void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void vbe_set_graphics(void); void vbe_textmode_console(void); +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +#define VESA_GET_INFO 0x4f00 +#define VESA_GET_MODE_INFO 0x4f01 +#define VESA_SET_MODE 0x4f02 diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c index 9a6ce41..22fc2c5 100644 --- a/src/devices/oprom/x86.c +++ b/src/devices/oprom/x86.c @@ -25,14 +25,19 @@ #include <arch/registers.h> #include <console/console.h> #include <arch/interrupt.h> - +#include <cbfs.h> +#include <delay.h> #include "x86.h" +#include "vbe.h" +#include "../../src/lib/jpeg.h" void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, - u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call; + u32 esi, u32 edi) __attribute__((regparm(0))) = + (void *)&__realmode_call; void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, - u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt; + u32 esi, u32 edi) __attribute__((regparm(0))) = + (void *)&__realmode_interrupt; static void setup_bda(void) { @@ -107,9 +112,9 @@ static void setup_interrupt_handlers(void) if(!intXX_handler[i]) { /* Now set the default functions that are actually - * needed to initialize the option roms. This is very - * slick, as it allows us to implement mainboard specific - * interrupt handlers, such as the int15 + * needed to initialize the option roms. This is + * very slick, as it allows us to implement mainboard + * specific interrupt handlers, such as the int15. */ switch (i) { case 0x10: @@ -178,6 +183,88 @@ static void setup_realmode_idt(void) write_idt_stub((void *)0xffe6e, 0x1a); } +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +static u8 vbe_get_mode_info(vbe_mode_info_t * mode_info) +{ + char *buffer = (char *)&__buffer; + u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; + u16 buffer_adr = ((unsigned long)buffer) & 0xffff; + realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, + mode_info->video_mode, 0x0000, buffer_seg, buffer_adr); + memcpy(mode_info, buffer, sizeof(vbe_mode_info_t)); + return 0; +} + +static u8 vbe_set_mode(vbe_mode_info_t * mode_info) +{ + // request linear framebuffer mode + mode_info->video_mode |= (1 << 14); + // request clearing of framebuffer + mode_info->video_mode &= ~(1 << 15); + realmode_interrupt(0x10, VESA_SET_MODE, mode_info->video_mode, + 0x0000, 0x0000, 0x0000, 0x0000); + return 0; +} + +vbe_mode_info_t mode_info; + +/* These two functions could probably even be generic between + * yabel and x86 native. TBD later. + */ +void vbe_set_graphics(void) +{ + mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; + vbe_get_mode_info(&mode_info); + unsigned char *framebuffer = + (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); + printk(BIOS_DEBUG, "framebuffer: %p\n", framebuffer); + printk(BIOS_DEBUG, "framebuffer: %x\n", mode_info.vesa.phys_base_ptr); + vbe_set_mode(&mode_info); +#if CONFIG_BOOTSPLASH + struct jpeg_decdata *decdata; + decdata = malloc(sizeof(*decdata)); + unsigned char *jpeg = cbfs_find_file("bootsplash.jpg", + CBFS_TYPE_BOOTSPLASH); + if (!jpeg) { + return; + } + int ret = 0; + ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata); +#endif +} + +void vbe_textmode_console(void) +{ + delay(2); + realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000); +} + +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + framebuffer->physical_address = + le32_to_cpu(mode_info.vesa.phys_base_ptr); + + framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); + framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); + framebuffer->bytes_per_line = + le16_to_cpu(mode_info.vesa.bytes_per_scanline); + framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; + + framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; + framebuffer->red_mask_size = mode_info.vesa.red_mask_size; + + framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; + framebuffer->green_mask_size = mode_info.vesa.green_mask_size; + + framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; + framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; + + framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; + framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; +} +#endif + void run_bios(struct device *dev, unsigned long addr) { u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn; @@ -203,6 +290,10 @@ void run_bios(struct device *dev, unsigned long addr) /* Option ROM entry point is at OPROM start + 3 */ realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); + +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE + vbe_set_graphics(); +#endif } #if CONFIG_GEODE_VSA diff --git a/src/devices/oprom/x86.h b/src/devices/oprom/x86.h index 0bc2412..40c5778 100644 --- a/src/devices/oprom/x86.h +++ b/src/devices/oprom/x86.h @@ -30,6 +30,7 @@ void x86_exception(struct eregs *info); extern unsigned char __idt_handler, __idt_handler_size; extern unsigned char __realmode_code, __realmode_code_size; extern unsigned char __realmode_call, __realmode_interrupt; +extern unsigned char __buffer; extern void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, u32 esi, u32 edi) __attribute__((regparm(0))); diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S index d5b5e18..57c5338 100644 --- a/src/devices/oprom/x86_asm.S +++ b/src/devices/oprom/x86_asm.S @@ -66,6 +66,11 @@ __registers = RELOCATED(.) .long 0 /* 16 - ESI */ .long 0 /* 20 - EDI */ +/* 256 byte buffer, used by int10 */ + .globl __buffer +__buffer = RELOCATED(.) + .skip 256 + .code32 .globl __realmode_call __realmode_call = RELOCATED(.) diff --git a/src/devices/oprom/yabel/compat/functions.c b/src/devices/oprom/yabel/compat/functions.c index db37fbc..542c81f 100644 --- a/src/devices/oprom/yabel/compat/functions.c +++ b/src/devices/oprom/yabel/compat/functions.c @@ -38,7 +38,7 @@ void run_bios(struct device * dev, unsigned long addr) biosemu(vmem, VMEM_SIZE, dev, addr); -#if CONFIG_BOOTSPLASH +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE vbe_set_graphics(); #endif } diff --git a/src/devices/oprom/yabel/device.c b/src/devices/oprom/yabel/device.c index 8259594..b09f50e 100644 --- a/src/devices/oprom/yabel/device.c +++ b/src/devices/oprom/yabel/device.c @@ -364,6 +364,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr) pci_ds.device_id = in16le(&pci_ds.device_id); pci_ds.img_length = in16le(&pci_ds.img_length); pci_ds.pci_ds_length = in16le(&pci_ds.pci_ds_length); +#ifdef DO_THIS_TEST_TWICE if (pci_ds.vendor_id != bios_device.pci_vendor_id) { printf ("Image has invalid Vendor ID: %04x, expected: %04x\n", @@ -376,6 +377,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr) pci_ds.device_id, bios_device.pci_device_id); break; } +#endif DEBUG_PRINTF("Image Length: %d\n", pci_ds.img_length * 512); DEBUG_PRINTF("Image Code Type: %d\n", pci_ds.code_type); if (pci_ds.code_type == 0) { diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c index 27bf5e6..b1d6984 100644 --- a/src/devices/oprom/yabel/vbe.c +++ b/src/devices/oprom/yabel/vbe.c @@ -13,7 +13,7 @@ #include <string.h> #include <types.h> -#if CONFIG_BOOTSPLASH +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE #include <boot/coreboot_tables.h> #endif @@ -64,7 +64,7 @@ vbe_prepare(void) return 0; // successfull init } -#if CONFIG_BOOTSPLASH +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE // VBE Function 00h static u8 vbe_info(vbe_info_t * info) @@ -704,10 +704,12 @@ void vbe_set_graphics(void) mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); + vbe_set_mode(&mode_info); + +#if CONFIG_BOOTSPLASH unsigned char *framebuffer = (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer); - vbe_set_mode(&mode_info); struct jpeg_decdata *decdata; decdata = malloc(sizeof(*decdata)); @@ -728,6 +730,7 @@ void vbe_set_graphics(void) DEBUG_PRINTF_VBE("Decompressing boot splash screen...\n"); ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata); DEBUG_PRINTF_VBE("returns %x\n", ret); +#endif } void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index a8fe377..b5ec6c3 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -28,7 +28,7 @@ void set_boot_successful(void) void boot_successful(void) { -#if CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_FRAMEBUFFER_KEEP_VESA_MODE void vbe_textmode_console(void); vbe_textmode_console();

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New patch to review for coreboot: 38860f7 Refactor option rom initialization code in coreboot.
by Stefan Reinauer 13 Oct '11

13 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/255 -gerrit commit 38860f7f936d58ca777a55dfc3c458feccfc0137 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 14:25:07 2011 -0700 Refactor option rom initialization code in coreboot. - move int15 handler out of the generic code into the mainboard directories of those mainboards that actually use it. - move vbe headers to vbe.h - move function prototypes used in native oprom code to x86.h Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/oprom/include/vbe.h | 112 +++++++++++++++++++++ src/devices/oprom/x86.c | 93 +----------------- src/devices/oprom/x86.h | 48 +++++++++ src/devices/oprom/x86_interrupts.c | 150 +++++++++++++++------------ src/devices/oprom/yabel/vbe.c | 94 +----------------- src/mainboard/kontron/986lcd-m/mainboard.c | 50 +++++++++- src/mainboard/roda/rk886ex/mainboard.c | 49 +++++++++- 7 files changed, 343 insertions(+), 253 deletions(-) diff --git a/src/devices/oprom/include/vbe.h b/src/devices/oprom/include/vbe.h new file mode 100644 index 0000000..b87b0d5 --- /dev/null +++ b/src/devices/oprom/include/vbe.h @@ -0,0 +1,112 @@ +/****************************************************************************** + * Copyright (c) 2004, 2008 IBM Corporation + * Copyright (c) 2009 Pattrick Hueper <phueper(a)hueper.net> + * All rights reserved. + * This program and the accompanying materials + * are made available under the terms of the BSD License + * which accompanies this distribution, and is available at + * http://www.opensource.org/licenses/bsd-license.php + * + * Contributors: + * IBM Corporation - initial implementation + *****************************************************************************/ + +// these structs are for input from and output to OF +typedef struct { + u8 display_type; // 0=NONE, 1= analog, 2=digital + u16 screen_width; + u16 screen_height; + u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width + u8 color_depth; // color depth in bpp + u32 framebuffer_address; + u8 edid_block_zero[128]; +} __attribute__ ((__packed__)) screen_info_t; + +typedef struct { + u8 signature[4]; + u16 size_reserved; + u8 monitor_number; + u16 max_screen_width; + u8 color_depth; +} __attribute__ ((__packed__)) screen_info_input_t; + +// these structs only store a subset of the VBE defined fields +// only those needed. +typedef struct { + char signature[4]; + u16 version; + u8 *oem_string_ptr; + u32 capabilities; + u16 video_mode_list[256]; // lets hope we never have more than 256 video modes... + u16 total_memory; +} vbe_info_t; + +typedef struct { + u16 mode_attributes; // 00 + u8 win_a_attributes; // 02 + u8 win_b_attributes; // 03 + u16 win_granularity; // 04 + u16 win_size; // 06 + u16 win_a_segment; // 08 + u16 win_b_segment; // 0a + u32 win_func_ptr; // 0c + u16 bytes_per_scanline; // 10 + u16 x_resolution; // 12 + u16 y_resolution; // 14 + u8 x_charsize; // 16 + u8 y_charsize; // 17 + u8 number_of_planes; // 18 + u8 bits_per_pixel; // 19 + u8 number_of_banks; // 20 + u8 memory_model; // 21 + u8 bank_size; // 22 + u8 number_of_image_pages; // 23 + u8 reserved_page; + u8 red_mask_size; + u8 red_mask_pos; + u8 green_mask_size; + u8 green_mask_pos; + u8 blue_mask_size; + u8 blue_mask_pos; + u8 reserved_mask_size; + u8 reserved_mask_pos; + u8 direct_color_mode_info; + u32 phys_base_ptr; + u32 offscreen_mem_offset; + u16 offscreen_mem_size; + u8 reserved[206]; +} __attribute__ ((__packed__)) vesa_mode_info_t; + +typedef struct { + u16 video_mode; + union { + vesa_mode_info_t vesa; + u8 mode_info_block[256]; + }; + // our crap + //u16 attributes; + //u16 linebytes; + //u16 x_resolution; + //u16 y_resolution; + //u8 x_charsize; + //u8 y_charsize; + //u8 bits_per_pixel; + //u8 memory_model; + //u32 framebuffer_address; +} vbe_mode_info_t; + +typedef struct { + u8 port_number; // i.e. monitor number + u8 edid_transfer_time; + u8 ddc_level; + u8 edid_block_zero[128]; +} vbe_ddc_info_t; + +struct lb_framebuffer; + +void vbe_set_graphics(void); // yabel only + +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void vbe_textmode_console(void); + + diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c index 37b45e6..9a6ce41 100644 --- a/src/devices/oprom/x86.c +++ b/src/devices/oprom/x86.c @@ -26,18 +26,7 @@ #include <console/console.h> #include <arch/interrupt.h> -#define REALMODE_BASE ((void *)0x600) - -struct realmode_idt { - u16 offset, cs; -}; - -void x86_exception(struct eregs *info); - -/* From x86_asm.S */ -extern unsigned char __idt_handler, __idt_handler_size; -extern unsigned char __realmode_code, __realmode_code_size; -extern unsigned char __realmode_call, __realmode_interrupt; +#include "x86.h" void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call; @@ -45,10 +34,6 @@ void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt; -#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB -#define INITIAL_EBDA_SEGMENT 0xF600 -#define INITIAL_EBDA_SIZE 0x400 - static void setup_bda(void) { /* clear BIOS DATA AREA */ @@ -104,79 +89,6 @@ void mainboard_interrupt_handlers(int intXX, void *intXX_func) intXX_handler[intXX] = intXX_func; } -static int int10_handler(struct eregs *regs) -{ - int res=-1; - static u8 cursor_row=0, cursor_col=0; - switch((regs->eax & 0xff00)>>8) { - case 0x01: // Set cursor shape - res = 0; - break; - case 0x02: // Set cursor position - if (cursor_row != ((regs->edx >> 8) & 0xff) || - cursor_col >= (regs->edx & 0xff)) { - printk(BIOS_INFO, "\n"); - } - cursor_row = (regs->edx >> 8) & 0xff; - cursor_col = regs->edx & 0xff; - res = 0; - break; - case 0x03: // Get cursor position - regs->eax &= 0x00ff; - regs->ecx = 0x0607; - regs->edx = (cursor_row << 8) | cursor_col; - res = 0; - break; - case 0x06: // Scroll up - printk(BIOS_INFO, "\n"); - res = 0; - break; - case 0x08: // Get Character and Mode at Cursor Position - regs->eax = 0x0f00 | 'A'; // White on black 'A' - res = 0; - break; - case 0x09: // Write Character and attribute - case 0x10: // Write Character - printk(BIOS_INFO, "%c", regs->eax & 0xff); - res = 0; - break; - case 0x0f: // Get video mode - regs->eax = 0x5002; //80x25 - regs->ebx &= 0x00ff; - res = 0; - break; - default: - printk(BIOS_WARNING, "Unknown INT10 function %04x!\n", - regs->eax & 0xffff); - break; - } - return res; -} - -static int int16_handler(struct eregs *regs) -{ - int res=-1; - switch((regs->eax & 0xff00)>>8) { - case 0x00: // Check for Keystroke - regs->eax = 0x6120; // Space Bar, Space - res = 0; - break; - case 0x01: // Check for Keystroke - regs->eflags |= 1<<6; // Zero Flag set (no key available) - res = 0; - break; - default: - printk(BIOS_WARNING, "Unknown INT16 function %04x!\n", - regs->eax & 0xffff); - break; - } - return res; -} - -int int12_handler(struct eregs *regs); -int int15_handler(struct eregs *regs); -int int1a_handler(struct eregs *regs); - static void setup_interrupt_handlers(void) { int i; @@ -206,9 +118,6 @@ static void setup_interrupt_handlers(void) case 0x12: intXX_handler[0x12] = &int12_handler; break; - case 0x15: - intXX_handler[0x15] = &int15_handler; - break; case 0x16: intXX_handler[0x16] = &int16_handler; break; diff --git a/src/devices/oprom/x86.h b/src/devices/oprom/x86.h new file mode 100644 index 0000000..0bc2412 --- /dev/null +++ b/src/devices/oprom/x86.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#define REALMODE_BASE ((void *)0x600) + +struct realmode_idt { + u16 offset, cs; +}; + +void x86_exception(struct eregs *info); + +/* From x86_asm.S */ +extern unsigned char __idt_handler, __idt_handler_size; +extern unsigned char __realmode_code, __realmode_code_size; +extern unsigned char __realmode_call, __realmode_interrupt; + +extern void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); + +extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, + u32 esi, u32 edi) __attribute__((regparm(0))); + +#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB +#define INITIAL_EBDA_SEGMENT 0xF600 +#define INITIAL_EBDA_SIZE 0x400 + +int int10_handler(struct eregs *regs); +int int12_handler(struct eregs *regs); +int int16_handler(struct eregs *regs); +int int1a_handler(struct eregs *regs); + diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c index 1dd645b..86d20d7 100644 --- a/src/devices/oprom/x86_interrupts.c +++ b/src/devices/oprom/x86_interrupts.c @@ -26,17 +26,7 @@ #include <console/console.h> #include <arch/io.h> #include <arch/registers.h> - -enum { - PCIBIOS_CHECK = 0xb101, - PCIBIOS_FINDDEV = 0xb102, - PCIBIOS_READCONFBYTE = 0xb108, - PCIBIOS_READCONFWORD = 0xb109, - PCIBIOS_READCONFDWORD = 0xb10a, - PCIBIOS_WRITECONFBYTE = 0xb10b, - PCIBIOS_WRITECONFWORD = 0xb10c, - PCIBIOS_WRITECONFDWORD = 0xb10d -}; +#include "x86.h" // errors go in AH. Just set these up so that word assigns // will work. KISS. @@ -48,9 +38,54 @@ enum { PCIBIOS_BADREG = 0x8700 }; -int int12_handler(struct eregs *regs); -int int1a_handler(struct eregs *regs); -int int15_handler(struct eregs *regs); +int int10_handler(struct eregs *regs) +{ + int res=-1; + static u8 cursor_row=0, cursor_col=0; + switch((regs->eax & 0xff00)>>8) { + case 0x01: // Set cursor shape + res = 0; + break; + case 0x02: // Set cursor position + if (cursor_row != ((regs->edx >> 8) & 0xff) || + cursor_col >= (regs->edx & 0xff)) { + printk(BIOS_INFO, "\n"); + } + cursor_row = (regs->edx >> 8) & 0xff; + cursor_col = regs->edx & 0xff; + res = 0; + break; + case 0x03: // Get cursor position + regs->eax &= 0x00ff; + regs->ecx = 0x0607; + regs->edx = (cursor_row << 8) | cursor_col; + res = 0; + break; + case 0x06: // Scroll up + printk(BIOS_INFO, "\n"); + res = 0; + break; + case 0x08: // Get Character and Mode at Cursor Position + regs->eax = 0x0f00 | 'A'; // White on black 'A' + res = 0; + break; + case 0x09: // Write Character and attribute + case 0x10: // Write Character + printk(BIOS_INFO, "%c", regs->eax & 0xff); + res = 0; + break; + case 0x0f: // Get video mode + regs->eax = 0x5002; //80x25 + regs->ebx &= 0x00ff; + res = 0; + break; + default: + printk(BIOS_WARNING, "Unknown INT10 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} int int12_handler(struct eregs *regs) { @@ -58,6 +93,26 @@ int int12_handler(struct eregs *regs) return 0; } +int int16_handler(struct eregs *regs) +{ + int res=-1; + switch((regs->eax & 0xff00)>>8) { + case 0x00: // Check for Keystroke + regs->eax = 0x6120; // Space Bar, Space + res = 0; + break; + case 0x01: // Check for Keystroke + regs->eflags |= 1<<6; // Zero Flag set (no key available) + res = 0; + break; + default: + printk(BIOS_WARNING, "Unknown INT16 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} + #define PCI_CONFIG_SPACE_TYPE1 (1 << 0) #define PCI_CONFIG_SPACE_TYPE2 (1 << 1) #define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) @@ -77,7 +132,7 @@ int int1a_handler(struct eregs *regs) u8 byte, reg; switch (func) { - case PCIBIOS_CHECK: + case 0xb101: /* PCIBIOS Check */ regs->edx = 0x20494350; /* ' ICP' */ regs->eax &= 0xffff0000; /* Clear AH / AL */ regs->eax |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1; @@ -87,7 +142,7 @@ int int1a_handler(struct eregs *regs) regs->edi = 0x00000000; /* protected mode entry */ retval = 0; break; - case PCIBIOS_FINDDEV: + case 0xb102: /* Find Device */ devid = regs->ecx; vendorid = regs->edx; devindex = regs->esi; @@ -114,12 +169,12 @@ int int1a_handler(struct eregs *regs) retval = -1; } break; - case PCIBIOS_READCONFDWORD: - case PCIBIOS_READCONFWORD: - case PCIBIOS_READCONFBYTE: - case PCIBIOS_WRITECONFDWORD: - case PCIBIOS_WRITECONFWORD: - case PCIBIOS_WRITECONFBYTE: + case 0xb10a: /* Read Config Dword */ + case 0xb109: /* Read Config Word */ + case 0xb108: /* Read Config Byte */ + case 0xb10d: /* Write Config Dword */ + case 0xb10c: /* Write Config Word */ + case 0xb10b: /* Write Config Byte */ devfn = regs->ebx & 0xff; bus = regs->ebx >> 8; reg = regs->edi; @@ -133,27 +188,27 @@ int int1a_handler(struct eregs *regs) return retval; } switch (func) { - case PCIBIOS_READCONFBYTE: + case 0xb108: /* Read Config Byte */ byte = pci_read_config8(dev, reg); regs->ecx = byte; break; - case PCIBIOS_READCONFWORD: + case 0xb109: /* Read Config Word */ word = pci_read_config16(dev, reg); regs->ecx = word; break; - case PCIBIOS_READCONFDWORD: + case 0xb10a: /* Read Config Dword */ dword = pci_read_config32(dev, reg); regs->ecx = dword; break; - case PCIBIOS_WRITECONFBYTE: + case 0xb10b: /* Write Config Byte */ byte = regs->ecx; pci_write_config8(dev, reg, byte); break; - case PCIBIOS_WRITECONFWORD: + case 0xb10c: /* Write Config Word */ word = regs->ecx; pci_write_config16(dev, reg, word); break; - case PCIBIOS_WRITECONFDWORD: + case 0xb10d: /* Write Config Dword */ dword = regs->ecx; pci_write_config32(dev, reg, dword); break; @@ -178,42 +233,3 @@ int int1a_handler(struct eregs *regs) return retval; } -int int15_handler(struct eregs *regs) -{ - int res = -1; - - /* This int15 handler is Intel IGD. specific. Other chipsets need other - * handlers. The right way to do this is to move this handler code into - * the mainboard or northbridge code. - * TODO: completely move to mainboards / chipsets. - */ - switch (regs->eax & 0xffff) { - /* And now Intel IGD code */ -#define BOOT_DISPLAY_DEFAULT 0 -#define BOOT_DISPLAY_CRT (1 << 0) -#define BOOT_DISPLAY_TV (1 << 1) -#define BOOT_DISPLAY_EFP (1 << 2) -#define BOOT_DISPLAY_LCD (1 << 3) -#define BOOT_DISPLAY_CRT2 (1 << 4) -#define BOOT_DISPLAY_TV2 (1 << 5) -#define BOOT_DISPLAY_EFP2 (1 << 6) -#define BOOT_DISPLAY_LCD2 (1 << 7) - case 0x5f35: - regs->eax = 0x5f; - regs->ecx = BOOT_DISPLAY_DEFAULT; - res = 0; - break; - case 0x5f40: - regs->eax = 0x5f; - regs->ecx = 3; // This is mainboard specific - printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx); - res = 0; - break; - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - regs->eax & 0xffff); - } - - return res; -} - diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c index 75e8f3e..27bf5e6 100644 --- a/src/devices/oprom/yabel/vbe.c +++ b/src/devices/oprom/yabel/vbe.c @@ -31,13 +31,14 @@ #include "mem.h" #include "interrupt.h" #include "device.h" -#include "vbe.h" #include <cbfs.h> #include <delay.h> #include "../../src/lib/jpeg.h" +#include <vbe.h> + // pointer to VBEInfoBuffer, set by vbe_prepare u8 *vbe_info_buffer = 0; @@ -45,97 +46,6 @@ u8 *vbe_info_buffer = 0; u8 *biosmem; u32 biosmem_size; -// these structs are for input from and output to OF -typedef struct { - u8 display_type; // 0=NONE, 1= analog, 2=digital - u16 screen_width; - u16 screen_height; - u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width - u8 color_depth; // color depth in bpp - u32 framebuffer_address; - u8 edid_block_zero[128]; -} __attribute__ ((__packed__)) screen_info_t; - -typedef struct { - u8 signature[4]; - u16 size_reserved; - u8 monitor_number; - u16 max_screen_width; - u8 color_depth; -} __attribute__ ((__packed__)) screen_info_input_t; - -// these structs only store a subset of the VBE defined fields -// only those needed. -typedef struct { - char signature[4]; - u16 version; - u8 *oem_string_ptr; - u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than 256 video modes... - u16 total_memory; -} vbe_info_t; - -typedef struct { - u16 mode_attributes; // 00 - u8 win_a_attributes; // 02 - u8 win_b_attributes; // 03 - u16 win_granularity; // 04 - u16 win_size; // 06 - u16 win_a_segment; // 08 - u16 win_b_segment; // 0a - u32 win_func_ptr; // 0c - u16 bytes_per_scanline; // 10 - u16 x_resolution; // 12 - u16 y_resolution; // 14 - u8 x_charsize; // 16 - u8 y_charsize; // 17 - u8 number_of_planes; // 18 - u8 bits_per_pixel; // 19 - u8 number_of_banks; // 20 - u8 memory_model; // 21 - u8 bank_size; // 22 - u8 number_of_image_pages; // 23 - u8 reserved_page; - u8 red_mask_size; - u8 red_mask_pos; - u8 green_mask_size; - u8 green_mask_pos; - u8 blue_mask_size; - u8 blue_mask_pos; - u8 reserved_mask_size; - u8 reserved_mask_pos; - u8 direct_color_mode_info; - u32 phys_base_ptr; - u32 offscreen_mem_offset; - u16 offscreen_mem_size; - u8 reserved[206]; -} __attribute__ ((__packed__)) vesa_mode_info_t; - -typedef struct { - u16 video_mode; - union { - vesa_mode_info_t vesa; - u8 mode_info_block[256]; - }; - // our crap - //u16 attributes; - //u16 linebytes; - //u16 x_resolution; - //u16 y_resolution; - //u8 x_charsize; - //u8 y_charsize; - //u8 bits_per_pixel; - //u8 memory_model; - //u32 framebuffer_address; -} vbe_mode_info_t; - -typedef struct { - u8 port_number; // i.e. monitor number - u8 edid_transfer_time; - u8 ddc_level; - u8 edid_block_zero[128]; -} vbe_ddc_info_t; - static inline u8 vbe_prepare(void) { diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 1d0c494..d7b1f13 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -25,6 +25,7 @@ #endif #include <pc80/mc146818rtc.h> #include <arch/io.h> +#include <arch/interrupt.h> #include "chip.h" #if CONFIG_PCI_OPTION_ROM_RUN_YABEL @@ -70,6 +71,53 @@ static void int15_install(void) } #endif +#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(struct eregs *regs) +{ + int res = -1; + + /* This int15 handler is Intel IGD. specific. Other chipsets need other + * handlers. The right way to do this is to move this handler code into + * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. + */ + switch (regs->eax & 0xffff) { + /* And now Intel IGD code */ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + case 0x5f35: + regs->eax = 0x5f; + regs->ecx = BOOT_DISPLAY_DEFAULT; + res = 0; + break; + case 0x5f40: + regs->eax = 0x5f; + regs->ecx = 3; // This is mainboard specific + printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx); + res = 0; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + } + + return res; +} + +static void int15_install(void) +{ + mainboard_interrupt_handlers(0x15, &int15_handler); +} +#endif + + /* Hardware Monitor */ static u16 hwm_base = 0xa00; @@ -221,7 +269,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ int15_install(); #endif diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 2c5b5e3..d87d712 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/device.h> #include <arch/io.h> +#include <arch/interrupt.h> #include <boot/tables.h> #include <delay.h> #if CONFIG_PCI_OPTION_ROM_RUN_YABEL @@ -99,6 +100,52 @@ static void int15_install(void) } #endif +#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(struct eregs *regs) +{ + int res = -1; + + /* This int15 handler is Intel IGD. specific. Other chipsets need other + * handlers. The right way to do this is to move this handler code into + * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. + */ + switch (regs->eax & 0xffff) { + /* And now Intel IGD code */ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + case 0x5f35: + regs->eax = 0x5f; + regs->ecx = BOOT_DISPLAY_DEFAULT; + res = 0; + break; + case 0x5f40: + regs->eax = 0x5f; + regs->ecx = 3; // This is mainboard specific + printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx); + res = 0; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + } + + return res; +} + +static void int15_install(void) +{ + mainboard_interrupt_handlers(0x15, &int15_handler); +} +#endif + #if DUMP_RUNTIME_REGISTERS static void dump_runtime_registers(void) { @@ -125,7 +172,7 @@ static void mainboard_enable(device_t dev) /* Disable Dummy DCC -> GP45 = 1 */ outb(inb(0x60f) | (1 << 5), 0x60f); -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ int15_install(); #endif

1 0

New patch to review for coreboot: b49e5b5 Enable/fix compilation of i8254 code in ram stage.
by Stefan Reinauer 13 Oct '11

13 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/254 -gerrit commit b49e5b5bb66a9194728471ed7c04badf5897fb46 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Sep 27 16:26:05 2011 -0700 Enable/fix compilation of i8254 code in ram stage. Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/pc80/i8254.h | 5 +++-- src/pc80/Makefile.inc | 1 + src/pc80/i8254.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index 82f31e6..4c5e703 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -20,8 +20,6 @@ #ifndef PC80_I8254_H #define PC80_I8254_H -void setup_i8254(void); - /* Ports for the 8254 timer chip */ #define TIMER0_PORT 0x40 #define TIMER1_PORT 0x41 @@ -60,4 +58,7 @@ void setup_i8254(void); #define PPCB_SPKR 0x02 /* Bit 1 */ #define PPCB_T2GATE 0x01 /* Bit 0 */ +#ifndef __ROMCC__ +void setup_i8254(void); +#endif #endif diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc index 4f126f6..2c8a80e 100644 --- a/src/pc80/Makefile.inc +++ b/src/pc80/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += mc146818rtc.c ramstage-y += isa-dma.c +ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c diff --git a/src/pc80/i8254.c b/src/pc80/i8254.c index ca993f4..f75216d 100644 --- a/src/pc80/i8254.c +++ b/src/pc80/i8254.c @@ -35,7 +35,7 @@ void setup_i8254(void) outb(0x12, TIMER1_PORT); } -#if CONFIG_UDELAY_TIMER2 +#if defined(CONFIG_UDELAY_TIMER2) && CONFIG_UDELAY_TIMER2 static void load_timer2(unsigned int ticks) { /* Set up the timer gate, turn off the speaker */

1 0

New patch to review for coreboot: 7c934a0 Update "STABLE" SeaBIOS selection to release 1.6.3
by Stefan Reinauer 13 Oct '11

13 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/253 -gerrit commit 7c934a0665195ffb523cdc05366492e7acfb0ff0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 14:05:49 2011 -0700 Update "STABLE" SeaBIOS selection to release 1.6.3 1.6.3 has a lot of benefits over the previous version, the two most important being: - working AHCI support - compiles with gcc 4.6.x Change-Id: Ie3a4d8f2624e0aa85e48ca09da53474c085838db Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/external/SeaBIOS/Makefile.inc | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index e04ffea..99d402c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,7 +1,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=1efb10b9ea30c45a8c9c6230234fefa10d2886ed +TAG-$(CONFIG_SEABIOS_STABLE)=e66fb31eac3e6be6aaab548c229af9bb1ba55c33 unexport KCONFIG_AUTOCONFIG @@ -24,6 +24,7 @@ config: checkout $(MAKE) -C seabios defconfig echo "CONFIG_COREBOOT=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> seabios/.config echo "CONFIG_COREBOOT_FLASH=y" >> seabios/.config echo "CONFIG_LZMA=y" >> seabios/.config echo "CONFIG_FLASH_FLOPPY=y" >> seabios/.config

1 0

New patch to review for coreboot: b130550 Fix romstage creation with gcc 4.6 and CAR targets
by Stefan Reinauer 13 Oct '11

13 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/252 -gerrit commit b1305505c57e4a4c34cf7f11b7028bf52dc8fd2a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 12:54:08 2011 -0700 Fix romstage creation with gcc 4.6 and CAR targets newer gcc versions generate ".section .text" instead of just ".text" in their assembler output. This patch makes sure that we don't end up with a superfluous ".section" that makes the build fail. Add -Wno-unused-but-set-variable to CFLAGS if the flag exists. Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Makefile.inc | 3 ++- util/xcompile/xcompile | 4 ++++ 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e9c00de..65c2a92 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -247,7 +247,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc @printf " POST romstage.inc\n" - sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $^ > $@.tmp + sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ + -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp mv $@.tmp $@ endif diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index fd4dbeb..b68e1b3 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -79,6 +79,10 @@ CC="${GCCPREFIX}gcc" testcc "$CC" "$CFLAGS-Wa,--divide " && CFLAGS="$CFLAGS-Wa,--divide " testcc "$CC" "$CFLAGS-fno-stack-protector " && CFLAGS="$CFLAGS-fno-stack-protector " testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none " +# GCC 4.6 is much more picky about unused variables. Turn off it's warnings for +# now: +testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \ + CFLAGS="$CFLAGS-Wno-unused-but-set-variable " if which gcc 2>/dev/null >/dev/null; then HOSTCC=gcc

1 0

New patch to review for coreboot: 8125150 Make Asus A8V-E SE better ACPI citizen.
by Rudolf Marek 12 Oct '11

12 Oct '11

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/251 -gerrit commit 8125150119b0bcbf4ce588dc5c731365bbd362e4 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Wed Oct 12 22:11:40 2011 +0200 Make Asus A8V-E SE better ACPI citizen. Use the SSDT autogen infrastructure to support the automatic reserved resources, automatic P-state generation and automatic _CRS PCI0 method. Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/a8v-e_se/acpi_tables.c | 19 ++++++++++ src/mainboard/asus/a8v-e_se/dsdt.asl | 52 +++++++++++++++++++++++++---- 2 files changed, 64 insertions(+), 7 deletions(-) diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c index fe8d475..e08b305 100644 --- a/src/mainboard/asus/a8v-e_se/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c @@ -31,6 +31,8 @@ #include <device/pci_ids.h> #include "southbridge/via/vt8237r/vt8237r.h" #include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include <cpu/amd/model_fxx_powernow.h> extern const unsigned char AmlCode[]; @@ -81,6 +83,14 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -91,6 +101,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_mcfg_t *mcfg; acpi_fadt_t *fadt; acpi_facs_t *facs; + acpi_header_t *ssdt; acpi_header_t *dsdt; /* Align ACPI tables to 16 byte. */ @@ -151,6 +162,14 @@ unsigned long write_acpi_tables(unsigned long start) current += srat->header.length; acpi_add_table(rsdp, srat); + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + printk(BIOS_INFO, "ACPI: done.\n"); return current; } diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl index 6a46102..16ad92c 100644 --- a/src/mainboard/asus/a8v-e_se/dsdt.asl +++ b/src/mainboard/asus/a8v-e_se/dsdt.asl @@ -24,12 +24,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (\_PR) - { - Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} - Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} - } + #include "northbridge/amd/amdk8/util.asl" /* For now only define 2 power states: * - S0 which is fully on @@ -50,8 +45,44 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Name (_UID, 0x00) Name (_BBN, 0x00) + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + /* PCI Routing Table */ - /* aaa */ Name (_PRT, Package () { Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, @@ -206,6 +237,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) } } } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + } } }

1 0

Re: [coreboot] Issues with Supermicro H8SCM
by She, Kerry 12 Oct '11

12 Oct '11

> -----Original Message----- > From: Thomas Gstädtner [mailto:thomas@gstaedtner.net] > Sent: Wednesday, October 12, 2011 4:10 PM > To: Marc Jones > Cc: She, Kerry; coreboot > Subject: Re: [coreboot] Issues with Supermicro H8SCM > > On Wed, Oct 12, 2011 at 02:46, Marc Jones <marcj303(a)gmail.com> wrote: > > On Tue, Oct 11, 2011 at 6:17 AM, Thomas Gstädtner > <thomas(a)gstaedtner.net> wrote: > >> On Tue, Oct 11, 2011 at 12:41, She, Kerry <Kerry.She(a)amd.com> wrote: > >>> Hello, Thomas > >>> > >>>> -----Original Message----- > >>>> From: Thomas Gstädtner [mailto:thomas@gstaedtner.net] > >>>> Sent: Sunday, October 09, 2011 11:53 PM > >>>> To: She, Kerry > >>>> Cc: Marc Jones; coreboot > >>>> Subject: Re: [coreboot] Issues with Supermicro H8SCM > >>>> > >>>> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She(a)amd.com> wrote: > >>>> > Hello, Thomas > >>>> > > >>>> >> -----Original Message----- > >>>> >> From: coreboot-bounces+kerry.she=amd.com(a)coreboot.org > >>>> >> [mailto:coreboot- > >>>> >> bounces+kerry.she=amd.com(a)coreboot.org] On Behalf Of Marc Jones > >>>> >> Sent: Saturday, October 08, 2011 3:45 AM > >>>> >> To: Thomas Gstädtner > >>>> >> Cc: coreboot > >>>> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM > >>>> >> > >>>> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gstädtner > >>>> >> <thomas(a)gstaedtner.net> > >>>> >> wrote: > >>>> >> > > >>>> >> > Thanks for the advice Marc, > >>>> >> > > >>>> >> > I already had the loglevel set to spew (8). I additionally > tried > >>>> >> > the other "Verbose output" debugging options, unfortunately I > don't > >>>> >> > get any output at all when they are built in. > >>>> >> > Also, while it is hard to find and AMD doesn't have any > official > >>>> >> > document confirming this, according to some google hits the > >>>> >> > processor should be revision D1 not rev E (AMD model number: > >>>> OS4170OFU6DGOWOF ). > >>>> > > >>>> > I also found the latest code not boot on my H8SCM-F mainboard with > Rev > >>>> D1 processor. > >>>> > So I have made some update to using the AGESA wrapper framework, > the > >>>> > attachment is some of my update, with this series of patches > applied, > >>>> > we can boot to Debian Linux Destop or Windows Server 2008 R2 > standard > >>>> > edition. > >>>> > Thanks > >>>> > > >>>> > >>>> Hi Kerry, > >>>> > >>>> first of all: thanks for your effort! > >>>> While I had no success at first, I now can get to the boot prompt > >>>> (haven't tried any further yet). > >>>> > >>>> Anyway, I currently have 2 DIMMs, each 4 GiB. > >>>> A dual-channel configuration does not seem to work, the DIMMs are > >>>> detected, but coreboot throws an "ASSERTION FAILED" error (see > attached > >>>> log cb_h8scm_01.log). > >>>> It seems to fail because it somehow seems to think no DIMM is found > >>>> (despite both DIMMs being detected). I tried disabling this check, > but > >>>> this only leads to a reset. > >>>> The same problem exists with a single-DIMM configuration. > >>>> > >>>> However, when I switch to a dual-DIMM, single-channel config, it at > first > >>>> does not start at all (i.e. no output on serial and no heartbeat > from the > >>>> BMC) - but when I trigger a manual reset it immediately starts up > (see > >>>> attached log cb_h8scm_dimma1a2_success.log). > >>>> > >>>> I'll report back when I find out more. > >>> > >>> > >>> I have only test with 4 Registered ECC DIMMs, so I can confirm dual > DIMMs in one channel should works, > >>> It seems that the DRAM training has some problem for single DIMM on > one channel situation. > >>> Thanks > >>> Kerry > >>> > >> > >> I unfortunately only have 2 registered DIMMs, so I can't test a dual > >> channel configuration, but yes, seems 1 DIMM per Channel does not work > >> at all. > >> > >> Anyway, I built a rom with vga bios included and can boot to FILO > >> prompt or SeaBIOS. So far USB is not working, neither the attached USB > >> keybord, nor the USB flashdrive I wanted to boot from. > >> A related warning seems to be: "WARNING - Timeout at > >> ehci_wait_qh:319!", might try to disable ehci to see if ohci works. > >> > >> Also, it seems it now starts up most of the time immediately, > >> approximately 1 out of 5 times it needs a manual reset after powering > >> up. > >> Time from power-on to FILO prompt is about 2 seconds with loglevel 3 > >> (over serial, via VGA I can't tell, it's ready long before the display > >> makes it from wake-up to active). > >> > >> So in short, > >> What Works: All 6 CPU cores are detected, clock is correct, VGA, > >> Serial, SeaBIOS and FILO > >> What Doesn't: USB/EHCI, Single-DIMM per Channel, reliable bootup > >> > >> -- > >> coreboot mailing list: coreboot(a)coreboot.org > >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > Hi Tomas > > > > This is great feedback. Maybe you can narrow down the boot failure. Is > > it in coreboot, payload, or Linux when it fails? > > > > > > > > Kerry, > > > > Please add this info to the wiki for this board. > > > > Thanks, > > Marc > > > > -- > > http://se-eng.com > > > > This is really hard to figure out so far, because I can get zero > output that would help me debug this problem. > I don't know how the hardware works exactly, but the board has a neat > watchdog in the BMC that seems to give a hint. > There's a heartbeat-LED that flashes when coreboot seems to run (when > it flashes I usually get output on serial and VGA), and when it > doesn't come up, the heartbeat-LED is off. So I _assume_ it is failing > early on, no clue how the BMC is powered on or what it looks for. The H8SCM Serial port connection is dependent on the BMC, Some older BMC implementation require the system BIOS to waiting for the BMC initialization, The serial console log printed by coreboot was dropped away during BMC initialize stage. The mainbaord manual says after the BMC init was finished, the LED will blanking. So you can power on the board after the BMC LED is blanking. Otherwise you need the BMC datasheet to figure out a solution to waiting for the BMC initialization. > I'm pretty sure the payload is not the problem and as I have not tried > to load linux yet we can rule that out :) The EHCI ports works well under Linux/windows OS, But I get some problem with seabios payload to using the EHCI CDROM and FlashDrive. EHCI cdrom boot sometimes, fail to boot some other time, it's quite not stable. Thanks > I'm happy to help with the wiki btw.

1 0

[RFC] Tracking run tested coreboot revisions for boards
by Paul Menzel 12 Oct '11

12 Oct '11

Dear coreboot folks, on IRC Rudolf mentioned that the A8V SE [1] works with the latest revision of coreboot and he asked if there is a way to tag that in the repository. There are several ways to accomplish that but all seem to have down sides. 1. Git tags. We could use `git tag <board name> <commit>` and interested folks could then do `git tag | grep <board name>` to find tested revisions. Peter wrote, that Git tags could slow down the repository and that only finitely many tags can be used. Would the last point be a problem for us? 2. Git notes. Peter suggested also to use Git notes. But Rudolf wrote he finds it difficult to handle. 3. Wiki. We could use the Wiki by either adding tested revisions to the corresponding board pages or by creating a new page with a table. The first solution is not feasible because not all boards have their own page. Patrick wrote that using the Wiki often it gets out of date pretty quickly. Although in this case I think that would not be a huge problem considering that the noted revision actually was tested. Additionally not a lot of developers are comfortable using the Wiki. OpenEmbedded once did something like that [2]. 4. Provide tested images. In addition to specifying the revision such tested images could be uploaded somewhere so users would not have to build it themselves. This would not work though, since the infrastructure is not in place and we have to be careful with images containing option roms(?). 5. ROM-o-matic.net [3]. Idwer suggested a service similar to ROM-o-matic.net where know revisions get build by this server and users can configure an image to be built. That is an interesting idea although it is probably the most difficult to realize. Could this be a GSoC project? 6. File in repository. An other suggestion by Patrick and myself is to put a file in for example `Documentation/working-revisions.mdtext` and note the tested revision and board there or to put a file in each board directory and note tested revisions there. The downside is that people would have to register with Gerrit to submit changes. If we would manage our Wiki in our repository [4] options 3 and 6 could be combined. 7. Messages to the list. Thinking about it the easiest solution would be to create something like the script `alsa-info.sh`. This script collects the necessary information – in our case for example revision, boards, cbfs output, used build tools. Even better would be to run that script on the tested machine so also something like the tested distribution could be tested. Then a mbox or text file with an appropriate name/subject line is created [Tested] ASUS M2V-MX SE works with revision <commit> which gets send to the list by the user or automatically. People then can search the archive. The only downside is that a nice table is missing. All in all I am quite surprised that no nice solutions seem to exist especially since I would imagine quality assurance (QA) folks in companies need to maintain similar data. Please comment and add your ideas. Thanks, Paul [1] http://www.coreboot.org/Supported_Motherboards [2] http://www.openembedded.org/wiki/Testing [3] http://rom-o-matic.net/ [4] http://www.coreboot.org/pipermail/coreboot/2011-June/065706.html [5] http://alsa-project.org/main/index.php/Help_To_Debug

3 2

Re: [coreboot] Issues with Supermicro H8SCM
by Thomas Gstädtner 12 Oct '11

12 Oct '11

On Wed, Oct 12, 2011 at 02:46, Marc Jones <marcj303(a)gmail.com> wrote: > On Tue, Oct 11, 2011 at 6:17 AM, Thomas Gstädtner <thomas(a)gstaedtner.net> wrote: >> On Tue, Oct 11, 2011 at 12:41, She, Kerry <Kerry.She(a)amd.com> wrote: >>> Hello, Thomas >>> >>>> -----Original Message----- >>>> From: Thomas Gstädtner [mailto:thomas@gstaedtner.net] >>>> Sent: Sunday, October 09, 2011 11:53 PM >>>> To: She, Kerry >>>> Cc: Marc Jones; coreboot >>>> Subject: Re: [coreboot] Issues with Supermicro H8SCM >>>> >>>> On Sun, Oct 9, 2011 at 07:17, She, Kerry <Kerry.She(a)amd.com> wrote: >>>> > Hello, Thomas >>>> > >>>> >> -----Original Message----- >>>> >> From: coreboot-bounces+kerry.she=amd.com(a)coreboot.org >>>> >> [mailto:coreboot- >>>> >> bounces+kerry.she=amd.com(a)coreboot.org] On Behalf Of Marc Jones >>>> >> Sent: Saturday, October 08, 2011 3:45 AM >>>> >> To: Thomas Gstädtner >>>> >> Cc: coreboot >>>> >> Subject: Re: [coreboot] Issues with Supermicro H8SCM >>>> >> >>>> >> On Fri, Oct 7, 2011 at 1:10 PM, Thomas Gstädtner >>>> >> <thomas(a)gstaedtner.net> >>>> >> wrote: >>>> >> > >>>> >> > Thanks for the advice Marc, >>>> >> > >>>> >> > I already had the loglevel set to spew (8). I additionally tried >>>> >> > the other "Verbose output" debugging options, unfortunately I don't >>>> >> > get any output at all when they are built in. >>>> >> > Also, while it is hard to find and AMD doesn't have any official >>>> >> > document confirming this, according to some google hits the >>>> >> > processor should be revision D1 not rev E (AMD model number: >>>> OS4170OFU6DGOWOF ). >>>> > >>>> > I also found the latest code not boot on my H8SCM-F mainboard with Rev >>>> D1 processor. >>>> > So I have made some update to using the AGESA wrapper framework, the >>>> > attachment is some of my update, with this series of patches applied, >>>> > we can boot to Debian Linux Destop or Windows Server 2008 R2 standard >>>> > edition. >>>> > Thanks >>>> > >>>> >>>> Hi Kerry, >>>> >>>> first of all: thanks for your effort! >>>> While I had no success at first, I now can get to the boot prompt >>>> (haven't tried any further yet). >>>> >>>> Anyway, I currently have 2 DIMMs, each 4 GiB. >>>> A dual-channel configuration does not seem to work, the DIMMs are >>>> detected, but coreboot throws an "ASSERTION FAILED" error (see attached >>>> log cb_h8scm_01.log). >>>> It seems to fail because it somehow seems to think no DIMM is found >>>> (despite both DIMMs being detected). I tried disabling this check, but >>>> this only leads to a reset. >>>> The same problem exists with a single-DIMM configuration. >>>> >>>> However, when I switch to a dual-DIMM, single-channel config, it at first >>>> does not start at all (i.e. no output on serial and no heartbeat from the >>>> BMC) - but when I trigger a manual reset it immediately starts up (see >>>> attached log cb_h8scm_dimma1a2_success.log). >>>> >>>> I'll report back when I find out more. >>> >>> >>> I have only test with 4 Registered ECC DIMMs, so I can confirm dual DIMMs in one channel should works, >>> It seems that the DRAM training has some problem for single DIMM on one channel situation. >>> Thanks >>> Kerry >>> >> >> I unfortunately only have 2 registered DIMMs, so I can't test a dual >> channel configuration, but yes, seems 1 DIMM per Channel does not work >> at all. >> >> Anyway, I built a rom with vga bios included and can boot to FILO >> prompt or SeaBIOS. So far USB is not working, neither the attached USB >> keybord, nor the USB flashdrive I wanted to boot from. >> A related warning seems to be: "WARNING - Timeout at >> ehci_wait_qh:319!", might try to disable ehci to see if ohci works. >> >> Also, it seems it now starts up most of the time immediately, >> approximately 1 out of 5 times it needs a manual reset after powering >> up. >> Time from power-on to FILO prompt is about 2 seconds with loglevel 3 >> (over serial, via VGA I can't tell, it's ready long before the display >> makes it from wake-up to active). >> >> So in short, >> What Works: All 6 CPU cores are detected, clock is correct, VGA, >> Serial, SeaBIOS and FILO >> What Doesn't: USB/EHCI, Single-DIMM per Channel, reliable bootup >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > Hi Tomas > > This is great feedback. Maybe you can narrow down the boot failure. Is > it in coreboot, payload, or Linux when it fails? > > > > Kerry, > > Please add this info to the wiki for this board. > > Thanks, > Marc > > -- > http://se-eng.com > This is really hard to figure out so far, because I can get zero output that would help me debug this problem. I don't know how the hardware works exactly, but the board has a neat watchdog in the BMC that seems to give a hint. There's a heartbeat-LED that flashes when coreboot seems to run (when it flashes I usually get output on serial and VGA), and when it doesn't come up, the heartbeat-LED is off. So I _assume_ it is failing early on, no clue how the BMC is powered on or what it looks for. I'm pretty sure the payload is not the problem and as I have not tried to load linux yet we can rule that out :) I'm happy to help with the wiki btw.

1 0

New patch to review for coreboot: 5308dd7 Update coreboot cross toolchain to gcc 4.6.1
by Stefan Reinauer 12 Oct '11

12 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/250 -gerrit commit 5308dd7bafe6981863bf817efdea8432c00c58cf Author: Stefan Reinauer <reinauer(a)google.com> Date: Tue Oct 11 22:37:59 2011 -0700 Update coreboot cross toolchain to gcc 4.6.1 - tested on Mac OS X 10.7.1 Please test on Windows and Linux Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/crossgcc/buildgcc | 76 ++++-- .../acpica-unix-20110922_unknown_warnings.patch | 19 ++ .../binutils-2.20_no-i386-svr4-asm-comments.patch | 10 - .../patches/binutils-2.21.1_no-bfd-doc.patch | 11 + .../patches/gcc-4.4.2_less-junk-in-crtbegin.patch | 50 ---- util/crossgcc/patches/gcc-4.5.1_pragma.patch | 10 - .../patches/mpfr-2.4.2_allpatches_20100308.patch | 266 -------------------- 7 files changed, 80 insertions(+), 362 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6061f26..40444a5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA # -CROSSGCC_DATE="August 8th, 2011" -CROSSGCC_VERSION="1.04" +CROSSGCC_DATE="October 10th, 2011" +CROSSGCC_VERSION="1.05" # default settings TARGETDIR=`pwd`/xgcc @@ -29,17 +29,18 @@ TARGETARCH=i386-elf DESTDIR= # version numbers -GMP_VERSION=5.0.1 -MPFR_VERSION=3.0.0 -MPC_VERSION=0.8.2 +GMP_VERSION=5.0.2 +MPFR_VERSION=3.1.0 +MPC_VERSION=0.9 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.5.2 -BINUTILS_VERSION=2.20.1 +GCC_VERSION=4.6.1 +GCC_AUTOCONF_VERSION=2.64 +BINUTILS_VERSION=2.21.1 GDB_VERSION=7.3.1 W32API_VERSION=3.17-2 W32API_VERSION_SHORT=3.17 MINGWRT_VERSION=3.18 -IASL_VERSION=20110623 +IASL_VERSION=20110922 # archive locations GMP_ARCHIVE="ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2" @@ -146,7 +147,7 @@ GNU General Public License for more details. EOF } -printf "${blue}Welcome to the ${red}coresystems${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n" +printf "${blue}Welcome to the ${red}coreboot${blue} cross toolchain builder v$CROSSGCC_VERSION ($CROSSGCC_DATE)${NC}\n\n" # Look if we have getopt. If not, build it. export PATH=$PATH:. @@ -198,14 +199,12 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then MINGW_ARCHIVES="$W32API_ARCHIVE $MINGWRT_ARCHIVE" fi -if [ ${GCC_VERSION} = "4.5.0" -o ${GCC_VERSION} = "4.6.0" ]; then - # coreboot does not like the GOLD linker - # USE_GOLD="--enable-gold" - USE_GOLD="" - GCC_OPTIONS="--enable-lto" -fi +# coreboot does not like the GOLD linker +# USE_GOLD="--enable-gold" +USE_GOLD="" +GCC_OPTIONS="--enable-lto" -if [ ${GCC_VERSION} = "4.6.0" ]; then +if [ ${GCC_VERSION} = "4.6.2" ]; then if [ ! -r tarballs/gcc-core-${GCC_VERSION}.tar.bz2 ]; then printf "Pre-Release GCC ${GCC_VERSION}, checking out subversion trunk\n" mkdir -p tarballs/.tmp @@ -273,6 +272,7 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then mv $MINGWRT_DIR/include/* $W32API_DIR/include/* $TARGETDIR/i386-mingw32/sys-include fi +CC=cc if [ `uname` = "Darwin" ]; then #GCC_OPTIONS="$GCC_OPTIONS --enable-threads=posix" @@ -286,13 +286,14 @@ if [ `uname` = "Darwin" ]; then else OPTIONS="ABI=32" fi - # old check: - #OPTIONS="ABI=32" - #touch .architecture_check.c - #gcc .architecture_check.c -c -o .architecture_check.o - #ARCH=`file .architecture_check.o |cut -f5 -d\ ` - #test "$ARCH" = "x86_64" && OPTIONS="ABI=64" - #rm .architecture_check.c .architecture_check.o + + # In Xcode 4 the default compiler was switched to gcc-llvm. + # However, this compiler fails to compile gcc 4.6.x. As a + # workaround it's possible to compile gcc with gcc-4.2 or + # clang. + if $CC -v 2>&1 | grep -q LLVM; then + CC=clang + fi fi mkdir -p build-gmp build-mpfr build-mpc build-libelf build-binutils build-gcc @@ -321,8 +322,10 @@ fi # ln -s $DESTDIR$TARGETDIR $TARGETDIR #fi -# Now set CFLAGS to match GMP CFLAGS. -HOSTCFLAGS=`grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2` +# Now set CFLAGS to match GMP CFLAGS but strip out -pedantic +# as GCC 4.6.x fails if it's there. +HOSTCFLAGS=`grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2 |\ + sed s,-pedantic,,` if [ -f build-mpfr/.success ]; then printf "Skipping MPFR as it is already built\n" @@ -393,6 +396,12 @@ if [ -f build-binutils/.success ]; then else printf "Building binutils ${BINUTILS_VERSION} ... " ( + # What a pain: binutils don't come with configure + # script anymore. Create it: + cd binutils-${BINUTILS_VERSION}/ + autoconf + cd .. + # Now build binutils cd build-binutils rm -f .failed ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \ @@ -411,6 +420,19 @@ if [ -f build-gcc/.success ]; then else printf "Building GCC ${GCC_VERSION} ... " ( + # Even worse than binutils: GCC does not come with configure + # script anymore, but also enforces an obsolete autoconf version + # to create it. This is a poster child of how autotools help make + # software portable. + cd gcc-${GCC_VERSION} + sed '/dnl Ensure exactly this Autoconf version is used/d' \ + config/override.m4 > config/override.m4.new + autoconf_version=`autoconf -V | grep "autoconf" | tr ' ' '\n' | tail -1` + sed "s/${GCC_AUTOCONF_VERSION}/${autoconf_version}/g" \ + config/override.m4.new > config/override.m4 + autoconf + cd .. + # Now, finally, we can build gcc: cd build-gcc export PATH=$PATH:$DESTDIR$TARGETDIR/bin rm -f .failed @@ -419,10 +441,12 @@ printf "Building GCC ${GCC_VERSION} ... " # There's a work-around called CFLAGS_FOR_BUILD and CFLAGS_FOR_TARGET # but it does not seem to work properly. At least the host library # libiberty is not compiled with CFLAGS_FOR_BUILD. - CFLAGS_FOR_TARGET="-O2" CFLAGS="$HOSTCFLAGS" CFLAGS_FOR_BUILD="$HOSTCFLAGS" `readlink -f ../gcc-${GCC_VERSION}/configure` \ + CC="$CC" CFLAGS_FOR_TARGET="-O2" CFLAGS="$HOSTCFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS" ../gcc-${GCC_VERSION}/configure \ --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ --target=${TARGETARCH} --disable-werror --disable-shared \ --disable-libssp --disable-bootstrap --disable-nls \ + --disable-libquadmath \ $GCC_OPTIONS --enable-languages="c" $USE_GOLD \ --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ diff --git a/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch new file mode 100644 index 0000000..f53be92 --- /dev/null +++ b/util/crossgcc/patches/acpica-unix-20110922_unknown_warnings.patch @@ -0,0 +1,19 @@ +--- acpica-unix-20110922/compiler/Makefile 2011-09-22 08:59:34.000000000 -0700 ++++ acpica-unix-20110922/compiler/Makefile 2011-10-11 23:47:29.000000000 -0700 +@@ -245,15 +245,11 @@ + -Waggregate-return \ + -Wchar-subscripts \ + -Wempty-body \ +- -Wlogical-op \ + -Wmissing-declarations \ + -Wmissing-field-initializers \ +- -Wmissing-parameter-type \ + -Wnested-externs \ +- -Wold-style-declaration \ + -Wold-style-definition \ +- -Wredundant-decls \ +- -Wtype-limits ++ -Wredundant-decls + + # + # Bison/Flex configuration diff --git a/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch b/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch deleted file mode 100644 index 3c0cef9..0000000 --- a/util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- binutils-2.20/gas/config/tc-i386.c~ 2009-01-20 14:19:04.000000000 +0100 -+++ binutils-2.20/gas/config/tc-i386.c 2009-01-20 14:20:47.000000000 +0100 -@@ -318,6 +318,7 @@ - && !defined (TE_GNU) \ - && !defined (TE_LINUX) \ - && !defined (TE_NETWARE) \ -+ && 0 \ - && !defined (TE_FreeBSD) \ - && !defined (TE_NetBSD))) - /* This array holds the chars that always start a comment. If the diff --git a/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch new file mode 100644 index 0000000..4fb9e21 --- /dev/null +++ b/util/crossgcc/patches/binutils-2.21.1_no-bfd-doc.patch @@ -0,0 +1,11 @@ +--- binutils-2.21.1/bfd/Makefile.in 2011-06-27 01:57:12.000000000 -0700 ++++ binutils-2.21.1/bfd/Makefile.in 2011-10-11 21:59:15.000000000 -0700 +@@ -323,7 +323,7 @@ + RELEASE = y + INCDIR = $(srcdir)/../include + CSEARCH = -I. -I$(srcdir) -I$(INCDIR) +-SUBDIRS = doc po ++SUBDIRS = po + bfddocdir = doc + libbfd_la_LDFLAGS = $(am__append_1) -release `cat libtool-soversion` \ + @SHARED_LDFLAGS@ $(am__empty) diff --git a/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch b/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch deleted file mode 100644 index a1c2480..0000000 --- a/util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- t/gcc-4.4.2/gcc/crtstuff.c Fr. Apr 10 01:23:07 2009 -+++ gcc-4.4.2/gcc/crtstuff.c Di. Jul 28 16:43:28 2009 -@@ -204,6 +204,7 @@ - = { (func_ptr) (-1) }; - #endif /* __DTOR_LIST__ alternatives */ - -+#if 0 - #ifdef USE_EH_FRAME_REGISTRY - /* Stick a label at the beginning of the frame unwind info so we can register - and deregister it with the exception handling library code. */ -@@ -219,6 +220,7 @@ - __attribute__ ((unused, section(JCR_SECTION_NAME), aligned(sizeof(void*)))) - = { }; - #endif /* JCR_SECTION_NAME */ -+#endif - - #if defined(INIT_SECTION_ASM_OP) || defined(INIT_ARRAY_SECTION_ASM_OP) - -@@ -309,6 +311,7 @@ - } - #endif /* !defined(FINI_ARRAY_SECTION_ASM_OP) */ - -+#if 0 - #ifdef USE_EH_FRAME_REGISTRY - #ifdef CRT_GET_RFIB_DATA - /* If we used the new __register_frame_info_bases interface, -@@ -320,6 +323,7 @@ - __deregister_frame_info (__EH_FRAME_BEGIN__); - #endif - #endif -+#endif - - completed = 1; - } -@@ -333,6 +337,7 @@ - = { __do_global_dtors_aux }; - #endif /* !defined(FINI_SECTION_ASM_OP) */ - -+#if 0 - #if defined(USE_EH_FRAME_REGISTRY) || defined(JCR_SECTION_NAME) - /* Stick a call to __register_frame_info into the .init section. For some - reason calls with no arguments work more reliably in .init, so stick the -@@ -364,6 +369,7 @@ - } - #endif /* JCR_SECTION_NAME */ - } -+#endif - - #ifdef INIT_SECTION_ASM_OP - CRT_CALL_STATIC_FUNCTION (INIT_SECTION_ASM_OP, frame_dummy) diff --git a/util/crossgcc/patches/gcc-4.5.1_pragma.patch b/util/crossgcc/patches/gcc-4.5.1_pragma.patch deleted file mode 100644 index 36ac8f4..0000000 --- a/util/crossgcc/patches/gcc-4.5.1_pragma.patch +++ /dev/null @@ -1,10 +0,0 @@ -diff -ur gcc-4.5.1.orig/gcc/config/i386/i386elf.h gcc-4.5.1/gcc/config/i386/i386elf.h ---- gcc-4.5.1.orig/gcc/config/i386/i386elf.h 2010-11-17 19:48:16.184401200 -0700 -+++ gcc-4.5.1/gcc/config/i386/i386elf.h 2010-11-17 20:52:54.443969900 -0700 -@@ -123,3 +123,6 @@ - #undef ASM_OUTPUT_ALIGNED_BSS - #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ - asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) -+ -+/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop). */ -+#define HANDLE_PRAGMA_PACK_PUSH_POP 1 diff --git a/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch b/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch deleted file mode 100644 index 6603337..0000000 --- a/util/crossgcc/patches/mpfr-2.4.2_allpatches_20100308.patch +++ /dev/null @@ -1,266 +0,0 @@ -diff -ur mpfr-2.4.2.orig/PATCHES mpfr-2.4.2/PATCHES ---- mpfr-2.4.2.orig/PATCHES 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/PATCHES 2010-03-08 22:28:53.000000000 +0100 -@@ -0,0 +1,3 @@ -+gmp5 -+longlong.h -+sin_cos_underflow -diff -ur mpfr-2.4.2.orig/VERSION mpfr-2.4.2/VERSION ---- mpfr-2.4.2.orig/VERSION 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/VERSION 2010-03-08 22:28:53.000000000 +0100 -@@ -1 +1 @@ --2.4.2 -+2.4.2-p3 -diff -ur mpfr-2.4.2.orig/configure mpfr-2.4.2/configure ---- mpfr-2.4.2.orig/configure 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/configure 2010-03-08 22:28:53.000000000 +0100 -@@ -20449,6 +20449,9 @@ - main () - { - -+#ifndef BITS_PER_MP_LIMB -+#define BITS_PER_MP_LIMB GMP_LIMB_BITS -+#endif - return BITS_PER_MP_LIMB == BYTES_PER_MP_LIMB * CHAR_BIT - && sizeof(mp_limb_t) == BYTES_PER_MP_LIMB ? 0 : 1; - -diff -ur mpfr-2.4.2.orig/configure.in mpfr-2.4.2/configure.in ---- mpfr-2.4.2.orig/configure.in 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/configure.in 2010-03-08 22:28:53.000000000 +0100 -@@ -424,6 +424,9 @@ - #include "gmp.h" - #include "gmp-impl.h" - ]], [[ -+#ifndef BITS_PER_MP_LIMB -+#define BITS_PER_MP_LIMB GMP_LIMB_BITS -+#endif - return BITS_PER_MP_LIMB == BYTES_PER_MP_LIMB * CHAR_BIT - && sizeof(mp_limb_t) == BYTES_PER_MP_LIMB ? 0 : 1; - ]])], [AC_MSG_RESULT(yes)], [ -diff -ur mpfr-2.4.2.orig/mpfr-impl.h mpfr-2.4.2/mpfr-impl.h ---- mpfr-2.4.2.orig/mpfr-impl.h 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/mpfr-impl.h 2010-03-08 22:28:53.000000000 +0100 -@@ -65,6 +65,12 @@ - # ifndef __GMP_IMPL_H__ - # include "gmp-impl.h" - # endif -+# ifndef BITS_PER_MP_LIMB -+# define BITS_PER_MP_LIMB GMP_LIMB_BITS -+# endif -+#ifndef mpn_sqr_n -+# define mpn_sqr_n mpn_sqr -+#endif - # ifdef MPFR_NEED_LONGLONG_H - # include "longlong.h" - # endif -diff -ur mpfr-2.4.2.orig/mpfr-longlong.h mpfr-2.4.2/mpfr-longlong.h ---- mpfr-2.4.2.orig/mpfr-longlong.h 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/mpfr-longlong.h 2010-03-08 22:28:53.000000000 +0100 -@@ -1011,7 +1011,15 @@ - #endif /* __m88000__ */ - - #if defined (__mips) && W_TYPE_SIZE == 32 --#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7 -+#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4) -+#define umul_ppmm(w1, w0, u, v) \ -+ do { \ -+ UDItype _r; \ -+ _r = (UDItype) u * v; \ -+ (w1) = _r >> 32; \ -+ (w0) = (USItype) _r; \ -+ } while (0) -+#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7 - #define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v)) - #else -@@ -1024,7 +1032,16 @@ - #endif /* __mips */ - - #if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64 --#if __GNUC__ > 2 || __GNUC_MINOR__ >= 7 -+#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4) -+typedef unsigned int UTItype __attribute__ ((mode (TI))); -+#define umul_ppmm(w1, w0, u, v) \ -+ do { \ -+ UTItype _r; \ -+ _r = (UTItype) u * v; \ -+ (w1) = _r >> 64; \ -+ (w0) = (UDItype) _r; \ -+ } while (0) -+#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7 - #define umul_ppmm(w1, w0, u, v) \ - __asm__ ("dmultu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v)) - #else -diff -ur mpfr-2.4.2.orig/mpfr.h mpfr-2.4.2/mpfr.h ---- mpfr-2.4.2.orig/mpfr.h 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/mpfr.h 2010-03-08 22:28:53.000000000 +0100 -@@ -27,7 +27,7 @@ - #define MPFR_VERSION_MAJOR 2 - #define MPFR_VERSION_MINOR 4 - #define MPFR_VERSION_PATCHLEVEL 2 --#define MPFR_VERSION_STRING "2.4.2" -+#define MPFR_VERSION_STRING "2.4.2-p3" - - /* Macros dealing with MPFR VERSION */ - #define MPFR_VERSION_NUM(a,b,c) (((a) << 16L) | ((b) << 8) | (c)) -diff -ur mpfr-2.4.2.orig/sin_cos.c mpfr-2.4.2/sin_cos.c ---- mpfr-2.4.2.orig/sin_cos.c 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/sin_cos.c 2010-03-08 22:28:53.000000000 +0100 -@@ -82,17 +82,19 @@ - if (y != x) - /* y and x differ, thus we can safely try to compute y first */ - { -- MPFR_FAST_COMPUTE_IF_SMALL_INPUT (y, x, -2 * expx, 2, 0, rnd_mode, -- { inexy = _inexact; -- goto small_input; }); -+ MPFR_FAST_COMPUTE_IF_SMALL_INPUT ( -+ y, x, -2 * expx, 2, 0, rnd_mode, -+ { inexy = _inexact; -+ goto small_input; }); - if (0) - { - small_input: - /* we can go here only if we can round sin(x) */ -- MPFR_FAST_COMPUTE_IF_SMALL_INPUT (z, __gmpfr_one, -2 * expx, -- 1, 0, rnd_mode, -- { inexz = _inexact; -- goto end; }); -+ MPFR_FAST_COMPUTE_IF_SMALL_INPUT ( -+ z, __gmpfr_one, -2 * expx, 1, 0, rnd_mode, -+ { inexz = _inexact; -+ MPFR_SAVE_EXPO_UPDATE_FLAGS (expo, __gmpfr_flags); -+ goto end; }); - } - - /* if we go here, one of the two MPFR_FAST_COMPUTE_IF_SMALL_INPUT -@@ -101,18 +103,19 @@ - else /* y and x are the same variable: try to compute z first, which - necessarily differs */ - { -- MPFR_FAST_COMPUTE_IF_SMALL_INPUT (z, __gmpfr_one, -2 * expx, -- 1, 0, rnd_mode, -- { inexz = _inexact; -- goto small_input2; }); -+ MPFR_FAST_COMPUTE_IF_SMALL_INPUT ( -+ z, __gmpfr_one, -2 * expx, 1, 0, rnd_mode, -+ { inexz = _inexact; -+ goto small_input2; }); - if (0) - { - small_input2: - /* we can go here only if we can round cos(x) */ -- MPFR_FAST_COMPUTE_IF_SMALL_INPUT (y, x, -2 * expx, 2, 0, -- rnd_mode, -- { inexy = _inexact; -- goto end; }); -+ MPFR_FAST_COMPUTE_IF_SMALL_INPUT ( -+ y, x, -2 * expx, 2, 0, rnd_mode, -+ { inexy = _inexact; -+ MPFR_SAVE_EXPO_UPDATE_FLAGS (expo, __gmpfr_flags); -+ goto end; }); - } - } - m += 2 * (-expx); -@@ -207,7 +210,6 @@ - mpfr_clear (xr); - - end: -- /* FIXME: update the underflow flag if need be. */ - MPFR_SAVE_EXPO_FREE (expo); - mpfr_check_range (y, inexy, rnd_mode); - mpfr_check_range (z, inexz, rnd_mode); -diff -ur mpfr-2.4.2.orig/tests/tsin_cos.c mpfr-2.4.2/tests/tsin_cos.c ---- mpfr-2.4.2.orig/tests/tsin_cos.c 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/tests/tsin_cos.c 2010-03-08 22:28:53.000000000 +0100 -@@ -382,23 +382,56 @@ - consistency (void) - { - mpfr_t x, s1, s2, c1, c2; -+ mp_exp_t emin, emax; - mp_rnd_t rnd; -+ unsigned int flags_sin, flags_cos, flags, flags_before, flags_ref; -+ int inex_sin, inex_cos, inex, inex_ref; - int i; - -+ emin = mpfr_get_emin (); -+ emax = mpfr_get_emax (); -+ - for (i = 0; i <= 10000; i++) - { - mpfr_init2 (x, MPFR_PREC_MIN + (randlimb () % 8)); - mpfr_inits2 (MPFR_PREC_MIN + (randlimb () % 8), s1, s2, c1, c2, - (mpfr_ptr) 0); -- tests_default_random (x, 256, -5, 50); -- rnd = RND_RAND (); -- mpfr_sin (s1, x, rnd); -- mpfr_cos (c1, x, rnd); -- mpfr_sin_cos (s2, c2, x, rnd); -- if (!(mpfr_equal_p (s1, s2) && mpfr_equal_p (c1, c2))) -+ if (i < 8 * GMP_RND_MAX) -+ { -+ int j = i / GMP_RND_MAX; -+ if (j & 1) -+ mpfr_set_emin (MPFR_EMIN_MIN); -+ mpfr_set_si (x, (j & 2) ? 1 : -1, GMP_RNDN); -+ mpfr_set_exp (x, mpfr_get_emin ()); -+ rnd = (mpfr_rnd_t) (i % GMP_RND_MAX); -+ flags_before = 0; -+ if (j & 4) -+ mpfr_set_emax (-17); -+ } -+ else -+ { -+ tests_default_random (x, 256, -5, 50); -+ rnd = RND_RAND (); -+ flags_before = (randlimb () & 1) ? -+ (unsigned int) (MPFR_FLAGS_ALL ^ MPFR_FLAGS_ERANGE) : -+ (unsigned int) 0; -+ } -+ __gmpfr_flags = flags_before; -+ inex_sin = mpfr_sin (s1, x, rnd); -+ flags_sin = __gmpfr_flags; -+ __gmpfr_flags = flags_before; -+ inex_cos = mpfr_cos (c1, x, rnd); -+ flags_cos = __gmpfr_flags; -+ __gmpfr_flags = flags_before; -+ inex = !!mpfr_sin_cos (s2, c2, x, rnd); -+ flags = __gmpfr_flags; -+ inex_ref = inex_sin || inex_cos; -+ flags_ref = flags_sin | flags_cos; -+ if (!(mpfr_equal_p (s1, s2) && mpfr_equal_p (c1, c2)) || -+ inex != inex_ref || flags != flags_ref) - { -- printf ("mpfr_sin_cos and mpfr_sin/mpfr_cos disagree on %s,\nx = ", -- mpfr_print_rnd_mode (rnd)); -+ printf ("mpfr_sin_cos and mpfr_sin/mpfr_cos disagree on %s," -+ " i = %d\nx = ", mpfr_print_rnd_mode (rnd), i); - mpfr_dump (x); - printf ("s1 = "); - mpfr_dump (s1); -@@ -408,9 +441,16 @@ - mpfr_dump (c1); - printf ("c2 = "); - mpfr_dump (c2); -+ printf ("inex_sin = %d, inex_cos = %d, inex = %d (expected %d)\n", -+ inex_sin, inex_cos, inex, inex_ref); -+ printf ("flags_sin = 0x%x, flags_cos = 0x%x, " -+ "flags = 0x%x (expected 0x%x)\n", -+ flags_sin, flags_cos, flags, flags_ref); - exit (1); - } - mpfr_clears (x, s1, s2, c1, c2, (mpfr_ptr) 0); -+ mpfr_set_emin (emin); -+ mpfr_set_emax (emax); - } - } - -diff -ur mpfr-2.4.2.orig/version.c mpfr-2.4.2/version.c ---- mpfr-2.4.2.orig/version.c 2010-03-08 22:28:46.000000000 +0100 -+++ mpfr-2.4.2/version.c 2010-03-08 22:28:53.000000000 +0100 -@@ -25,5 +25,5 @@ - const char * - mpfr_get_version (void) - { -- return "2.4.2"; -+ return "2.4.2-p3"; - }

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coreboot October 2011