coreboot January 2011

coreboot@coreboot.org

65 participants
299 discussions

Re: [coreboot] [PATCH] Freeze SeaBIOS master tag
by Peter Stuge 29 Jan '11

29 Jan '11

Patrick Georgi wrote: > > > I suppose a .config could be copied in and "make oldconfig run". > > > > complete config if SeaBIOS adds more Kconfig options. > > oldconfig is made just for that. Send in a partial set of options, > and it'll fill in anything missing with defaults as defined in > Kconfig (and subject to the rough dependency mechanisms Kconfig > provides) I get a prompt for the missing options with oldconfig. But I've seen what you describe too, just not sure how it happened? //Peter

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Re: [coreboot] Patch to superiotool - add basic indexing of devices detected at IO ports
by Frantisek Rysanek 29 Jan '11

29 Jan '11

Dear gentlemen, sorry for a noob question... noone has responded to my suggested patch - is there something more I can do? I can see on the mailing list that the admins are busy doing other things, and I understand they are volunteers, so I'd hate to sound abusive :-) I guess the patch may look long, but it's mostly the same one-liners over and over in all the vendor-specific files. And it's so simple conceptually, that it shouldn't cause any trouble. I've spent an enjoyable evening coding the patch and I'd like to have it merged, for the benefit of others... Thanks for your time and attention :-) Frank Rysanek ----------- On 10 Jan 2011 at 8:49, Frantisek.Rysanek(a)post.cz wrote: This patch adds a simple table of SuperIO chips already detected in the system. This allows superiotool to properly avoid scanning the same IO port again by another vendor-specific probe, after some device has already been found on that particular port. The table of chips detected contains entries that, apart from the IO port known to be "inhabited", also relate the port to a particular "chip entry" (struct superio_registers*). There's no immediate use for this, but in the future it could facilitate further functionality enhancements, such as - separation of the "dump" function from the "detect" function - write support (with validity checking of the desired LDN/CR) As suggested by Mr. Hendricks, the vendor-specific probe functions now return a result code, indicating that a particular chip was found and which one that was, or that none was detected. The simple "framework" is headquartered in superiotool.c, with some necessary mods to superiotool.h. All the existing "vendor-specific" C files have been adapted to make use of this "framework". Apart from this addition, the patch scraps some previous attempts at the same functionality, and moves some table definitions from superiotool.h to superiotool.c, where they seem to belong. Signed-off-by: Frank Rysanek <Frantisek.Rysanek(a)post.cz> --- Tested on my AEC-6811 with two Winbond SuperIO chips. Note that the Winbond probe comes last in the "sequence of vendors", so my test is not entirely significant :-) I've tried the recommended method of deriving the patch via "svn diff". The resulting patch however fails to apply cleanly (hunk failed...). But if I try the bare "diff -Naur", the resulting patch *does* apply just fine. Go figure... Attached you'll find the manual diff that works for me. The following section of this message contains a file attachment prepared for transmission using the Internet MIME message format. If you are using Pegasus Mail, or any other MIME-compliant system, you should be able to save it or view it from within your mailer. If you cannot, please ask your system administrator for assistance. ---- File information ----------- File: device_counting.diff Date: 9 Jan 2011, 22:25 Size: 20401 bytes. Type: Unknown

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[PATCH] Fix infinite loop in pnp_get_ioresource()
by Alex G. 29 Jan '11

29 Jan '11

Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if a rare condition arises. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ---

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[commit] r6317 - in trunk: payloads/external/SeaBIOS src/arch/x86
by repository service 29 Jan '11

29 Jan '11

Author: stepan Date: Sat Jan 29 06:51:54 2011 New Revision: 6317 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6317 Log: Pass all required toolchain parts to SeaBIOS correctly Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/payloads/external/SeaBIOS/Makefile.inc trunk/src/arch/x86/Makefile.inc Modified: trunk/payloads/external/SeaBIOS/Makefile.inc ============================================================================== --- trunk/payloads/external/SeaBIOS/Makefile.inc Fri Jan 28 21:57:48 2011 (r6316) +++ trunk/payloads/external/SeaBIOS/Makefile.inc Sat Jan 29 06:51:54 2011 (r6317) @@ -6,7 +6,7 @@ all: seabios seabios: patch - cd seabios; $(MAKE) CC="$(CC)" LD="$(LD)" + cd seabios; $(MAKE) patch: checkout test -r seabios/.patched || \ @@ -23,7 +23,7 @@ cd seabios; git checkout -m $(TAG-y) clean: - test -d seabios && (cd seabios; $(MAKE) CC="$(CC)" LD="$(LD)" clean) || exit 0 + test -d seabios && (cd seabios; $(MAKE) clean) || exit 0 distclean: rm -rf seabios Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Fri Jan 28 21:57:48 2011 (r6316) +++ trunk/src/arch/x86/Makefile.inc Sat Jan 29 06:51:54 2011 (r6317) @@ -286,7 +286,8 @@ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ - CC="$(CC)" LD="$(LD)" \ + CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ + OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE)

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[PATCH] Fix infinite loop in pnp_get_ioresource()
by Alex G. 29 Jan '11

29 Jan '11

Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if a rare condition arises. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ---

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[PATCH] Add PCI ID's for VIA K8T800 and K8M800 chipsets
by Alex G. 29 Jan '11

29 Jan '11

Added PCI ID's for the functions of the VIA K8T800(Pro) and K8M800 chipsets. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Although this is very trivial, I don't think I'm in the position to ack. Alex

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[commit] r6316 - trunk/src/southbridge/amd/sb700
by repository service 28 Jan '11

28 Jan '11

Author: ruik Date: Fri Jan 28 21:57:48 2011 New Revision: 6316 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6316 Log: Attached patch fixes the LPC decode ranges of SB700. We enable early only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only... Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc... Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad. Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded. While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/southbridge/amd/sb700/early_setup.c trunk/src/southbridge/amd/sb700/lpc.c Modified: trunk/src/southbridge/amd/sb700/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/early_setup.c Fri Jan 28 09:05:54 2011 (r6315) +++ trunk/src/southbridge/amd/sb700/early_setup.c Fri Jan 28 21:57:48 2011 (r6316) @@ -411,25 +411,8 @@ /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); - /* IO Port Decode Enable */ - pci_write_config8(dev, 0x44, 0xFF); - pci_write_config8(dev, 0x45, 0xFF); - pci_write_config8(dev, 0x46, 0xC3); - pci_write_config8(dev, 0x47, 0xFF); - - // TODO: This has already been done(?) - /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports. - * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), - * Alternate Super I/O Configuration Port (4e/4f), Wide Generic IO Port (64/65). */ - byte = pci_read_config8(dev, 0x48); - byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - byte |= 1 << 6; /* enable for RTC I/O range */ - pci_write_config8(dev, 0x48, byte); + /* LPC Sync Timeout */ pci_write_config8(dev, 0x49, 0xFF); - /* Enable 0x480-0x4bf, 0x4700-0x470B */ - byte = pci_read_config8(dev, 0x4A); - byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ - pci_write_config8(dev, 0x4A, byte); /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ pci_write_config8(dev, 0x7C, 0x05); Modified: trunk/src/southbridge/amd/sb700/lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/lpc.c Fri Jan 28 09:05:54 2011 (r6315) +++ trunk/src/southbridge/amd/sb700/lpc.c Fri Jan 28 21:57:48 2011 (r6316) @@ -140,7 +140,8 @@ struct bus *link; u32 reg, reg_x; int var_num = 0; - u16 reg_var[3]; + u16 reg_var[3] = {0x0, 0x0, 0x0}; + u8 wiosize = pci_read_config8(dev, 0x74); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); @@ -171,13 +172,14 @@ case 0x2f8: /* COM2 */ reg |= (1 << 7); break; - case 0x378: /* Parallal 1 */ + case 0x378: /* Parallel 1 */ reg |= (1 << 0); + reg |= (1 << 1); /* + 0x778 for ECP */ break; case 0x3f0: /* FD0 */ reg |= (1 << 26); break; - case 0x220: /* Aduio 0 */ + case 0x220: /* Audio 0 */ reg |= (1 << 8); break; case 0x300: /* Midi 0 */ @@ -207,12 +209,19 @@ switch (var_num) { case 0: reg_x |= (1 << 2); + if ((end - base) < 16) + wiosize |= (1 << 0); break; case 1: reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 2); break; case 2: reg_x |= (1 << 25); + reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 3); break; } reg_var[var_num++] = @@ -234,6 +243,7 @@ pci_write_config16(dev, 0x64, reg_var[0]); break; } + pci_write_config8(dev, 0x74, wiosize); } static void sb700_lpc_enable_resources(device_t dev)

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[PATCH] rs780 PCIE GFX core add pcie ddi config option
by She, Kerry 28 Jan '11

28 Jan '11

Hello, This patch add pcie and ddi configuration option for rs780 PCIE GFX core. Reference rpr chapter 7. thanks signed-off-by: Kerry she <kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com>

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missing read_resources for CK804
by Joseph Smith 28 Jan '11

28 Jan '11

Hello, Working on a new CK804 board and I have it almost booting but it seems the resource allocator does not like / or want to enumerate the CK804. It seems to be working fine for K8 and SuperIO but not the Southbridge. I just get a "missing read_resources" on all CK804 devices. This is my first AMD board so any help/direction/clues/hints would be much appreciated. Attached is the bootlog. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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build service results for r6311
by repository service 28 Jan '11

28 Jan '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6311 to the coreboot repository. This caused the following changes: Change Log: rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST because that is what it does. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build Log: Compilation of a-trend:atc-6220 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot January 2011