coreboot July 2010

coreboot@coreboot.org

57 participants
142 discussions

Re: [coreboot] Mobo Support
by David Borg 16 Jul '10

16 Jul '10

Thanks a lot! I'll start working on it as soon as I have some time. Regards, David On 14 July 2010 23:38, Anders Jenbo <anders(a)jenbo.dk> wrote: > Here is the patch > > lør, 10 07 2010 kl. 01:16 +0200, skrev David Borg: >> Hey Anders, >> I can help out with coding and testing support for the GA-6VX7-4X. Do >> you have a patch with the code you have done already, so we don't >> duplicate efforts? I've got datasheets for the north and south >> bridges, so it shouldn't be too difficult to include support for this >> board. Let me know how I can help. >> >> Thanks, >> David > > -- David Borg

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[commit] r5665 - trunk/util/sconfig
by repository service 15 Jul '10

15 Jul '10

Author: oxygene Date: Thu Jul 15 17:59:07 2010 New Revision: 5665 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5665 Log: Trivial: Improve error reporting of sconfig slightly by reporting the line number. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/sconfig/main.c Modified: trunk/util/sconfig/main.c ============================================================================== --- trunk/util/sconfig/main.c Fri Jul 9 20:52:17 2010 (r5664) +++ trunk/util/sconfig/main.c Thu Jul 15 17:59:07 2010 (r5665) @@ -21,6 +21,8 @@ #include "sconfig.h" #include "sconfig.tab.h" +extern int linenum; + struct device *head, *lastdev; struct header headers; @@ -87,7 +89,7 @@ void yyerror (char const *str) { - fprintf (stderr, "%s\n", str); + fprintf (stderr, "line %d: %s\n", linenum, str); } void postprocess_devtree(void) {

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Uncommitted GPIOs
by Gregg C Levine 14 Jul '10

14 Jul '10

Hello! Would anyone be able to confirm this line of reasoning? For anything based on the X86 design styles, only the GEODE families have these uncommitted GPIO points that are documented. But do the Intel designed chipsets contain undocumented GPIO points? ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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Jetway PA78VM5 Support
by Qing Pei Wang 14 Jul '10

14 Jul '10

add support of Jetway PA78VM5 and F71863FG super I/O support. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> -- Wang Qing Pei Phone: 86+13426369984

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cbfs for safe flashing
by Ed Swierk 14 Jul '10

14 Jul '10

Hi folks, I'm using Coreboot to implement an old-school Linux-as-bootloader for a prototype board, which has an 8-MByte SPI flash attached to an AMD SB800 southbridge. I'd like to take advantage of that nice roomy flash, as well as the normal/fallback capabilities of Coreboot and the layout and partial-rewrite features of flashrom, to provide a safe firmware upgrade path for end users. Ideally I'd divide up the flash so that the normal Coreboot+payload are separate from the fallback Coreboot+payload and bootblock. The end user would only rewrite the normal Coreboot+payload. If the rewrite fails leaving the normal area of the flash completely scrambled, the board would still boot using the fallback Coreboot+payload. And for extra credit, I'd try to put the critical fallback bits in an area of the flash that can be turned read-only once it's programmed at the factory. Following the flashrom layout format, here's how I imagine partitioning the flash: 00000000:003fffff normal+payload 00400000:ffffffff fallback+payload+bootblock Following Patrick's helpful recipe (http://www.coreboot.org/pipermail/coreboot/2010-February/055944.html) I figured out how to build a rom image with a cbfs containing normal and fallback files. Unfortunately the build system insists on placing each new file at the beginning of the free space; I didn't see any obvious way to convince cbfstool to leave a gap after normal+payload and place the fallback files at 00400000. I hacked around this by creating a dummy pad file and adding it before the fallback files. Is there a better way to do this? The next issue I encountered is that when I test my scheme by erasing the 00000000:003fffff region, Coreboot takes approximately forever to locate the fallback files. In cbfs, information about each file is stored in a header along with the file itself. To locate a file, Coreboot starts at the first file's header and hops from one to the next until it finds a matching filename. If instead of a header it finds gibberish, it doesn't throw up its hands in despair; rather, it goes into PRESS PLAY ON TAPE mode, scanning along until it either finds a header signature or hits the end of the rom. At this early stage of the boot process, caches and other such niceties aren't enabled; on my board, each iteration in the walkcbfs loop causes ~75 SPI reads, yielding a scan rate of ~175kB/sec. Placing the fallback files before the normal ones doesn't help, because the bootblock needs to discover that the normal files are AWOL before deciding to use the fallback. Increasing the cbfs file alignment from the default of 64 bytes is more promising, allowing the scan to take much bigger hops. I tried bumping it up to 4096 bytes and ran into several bugs in cbfstool and walkcbfs, which assume that the bootblock region is larger than the alignment in deciding when to terminate the scan. While I'm sure these issues can be fixed, the whole flash-as-tape thing bothers me. In my scheme, I've decided ahead of time where the files are supposed to reside. A file's header is either there or it isn't; there's no point wasting time scanning the entire flash in the vain hope that the file is actually present, just in an unexpected location. I'm thinking of extending the cbfs format to allow more than one top-level header in the bootblock. In my scheme, there would be two: one pointing to the first normal file, and another pointing to the first fallback file. Searching for a file would involve scanning each series of files linked from the headers in the bootblock, and would simply terminate if no matching filename were found in any of them. This implies changing cbfstool and any code in Coreboot that touches cbfs. Before I jump off the deep end, is there an easier or better way to achieve this? --Ed

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Add support for nuvoton WPCE775x/NPCE781x devices
by Amit.Maoz＠nuvoton.com 14 Jul '10

14 Jul '10

This patch was created by: dhendrix(a)google.com<mailto:dhendrix@google.com>. Amit Maoz Advanced PC Division Nuvoton Israel, P.O.Box 3007, Hertzlia B, 46130 Israel Phone : +972-9-9702266 Fax : +972-9-9702001 Email : Amit.Maoz(a)nuvoton.com<mailto:Amit.Maoz@nuvoton.com> =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton. =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

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Coreboot RS780 problem
by Grant 吳明祐 14 Jul '10

14 Jul '10

Hi all, Coreboot just added support for RS780 chipset. My mainboard is AM2+RS780+SB700. In Coreboot, I use "make menuconfig" command to choose motherboard. I can only choose "AMD + Tilapia" project. However, it is AM3+RS780+SB700. So how can I replace the cpu code to AM2 in coreboot? BR Grant

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Trac reminder: list of new ticket(s)
by coreboot tracker 12 Jul '10

12 Jul '10

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Necessary information for supporting chipsets
by Takuo Fukunaga 12 Jul '10

12 Jul '10

Hi, my apologies in advance for the newbie question. I would just like to know what information is necessary to support recent Intel chipsets such as Nehalem chipsets. Datasheets for these chipsets are available on Intel's web site and I think that is enough. Are there any information, for example, setup sequence, which isn't described in those datasheets? Best Regards, Takuo

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Re: [coreboot] Mobo Support
by Anders Jenbo 10 Jul '10

10 Jul '10

Ok that is a Hynix chip, no other chips of that bran is currently supported, but the data-sheet is available here: http://www.datasheetcatalog.org/datasheet/hynix/HY29F002TT-55.pdf So it shouldn't be to much trouble to get it working. It is a 256KB 5v PLCC32. I think it is parallel but you should check with the flashrom developers to confirm this. You probably want to desolder it and solder on a PLCC32 socket and get a compatible spare to experiment with, so that you do not brick you board. If you are no skilled with a solder iron i highly recommend paying some one who is. -Anders On Mon 07/06/10 01:16 , David Borg <borg.db(a)gmail.com> wrote: > Hey Anders, thanks for the reply. > Good to hear that progress is being made =] I should have some free > time available in the coming summer holidays, so I'll try to help > out > then. > Regarding the rom chip, I got its number (HY29F002TC-90). I'll > contact > the flashrom developers about support for it. > Cheers, > David > On 7 June 2010 00:20, Anders Jenbo wrote: > > Hallo David > > > > I am currently working on the chip-set that your board uses. So > support is in progress. I have debug console running via serial and i > am about a 1/3 in to getting the ram initialized. If you think you can > help (time is the only real skill required) coding in the support you > are more then welcome. > > > > You should get in contact with the flashrom developers to get > support for your flash chip. Remove the AMI BIOS lable from the rom > chip and read the fist number on the actual chip, should be some thing > similar to these http://www.flashrom.org/Supported_hardware. You can > find the flashrom developers at freenode.net #flashrom, or . > > > > Good luck > > -Anders > > > > > > On Sun 06/06/10 19:17 , David Borg wrote: > > > >> Hey all, I was thinking of trying out coreboot on my old desktop > pc > >> and would like to check whether the motherboard is supported, as > it is > >> not in the list of supported motherboards. > >> System description: > >> Board vendor : GigabyteBoard name : GA-6VX7-4XCPU : Intel Celeron > >> 633MHz > >> Northbridge : VT82C694X > >> (URL: > http://www.datasheetarchive.com/pdf-datasheets/Datasheets-23/DSA-446 > >> 497.pdf[1]) Southbridge : VT82C686A > >> (URL: http://www.charmed.com/PDF/VT82C686A.pdf [2]) > >> > >> The output of lspci -tvnn is attached (lscpi.txt). Note:-0b.0 > >> Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ > [10ec:8139] > >> > >> Links: > >> ------ > >> [1] > >> > http://www.datasheetarchive.com/pdf-datasheets/Datasheets-23/DSA-446497.pdf > >> [2] http://www.charmed.com/PDF/VT82C686A.pdf > >> [3] > >> > http://www.gigabyte.com/products/product-page.aspx?pid=1415&dl=#sp > >> > >> > > ---- Msg sent via @Mail - http://atmail.com/ > > > > ---- Msg sent via @Mail - http://atmail.com/

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coreboot July 2010