coreboot July 2010

coreboot@coreboot.org

57 participants
142 discussions

[commit] r5659 - in trunk/src: cpu/amd/dualcore cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/quadcore include/cpu/amd northbridge/amd/amdfam10 northbridge/amd/amdmct/mct northbridge/amd/amdmct/wra...
by repository service 08 Jul '10

08 Jul '10

Author: stepan Date: Thu Jul 8 02:37:23 2010 New Revision: 5659 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5659 Log: get rid of even more fam10 and k8 warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/northbridge/amd/amdmct/mct/mct_fd.c Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore_id.c trunk/src/include/cpu/amd/multicore.h trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c trunk/src/northbridge/amd/amdfam10/setup_resource_map.c trunk/src/northbridge/amd/amdmct/mct/mct.h trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c trunk/src/southbridge/amd/amd8111/amd8111.h trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore_id.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/dualcore/dualcore_id.c Thu Jul 8 02:37:23 2010 (r5659) @@ -14,7 +14,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static inline unsigned get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xf); } Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) @@ -252,12 +252,11 @@ printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { /* Called by the BSP to indicate AP can stop */ - /* FIXME Do APs use this? - Looks like wait_till_sysinfo_in_ram is used instead. */ + /* FIXME Do APs use this? */ // allow aps to stop use 6 bits for state lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14); @@ -395,15 +394,11 @@ } #endif - /* AP is ready, Wait for the BSP to get memory configured */ - /* FIXME: many cores spinning on node0 pci register seems to be bad. - * Why do we need to wait? These APs are just going to go sit in a hlt. - */ - //wait_till_sysinfo_in_ram(); - + /* AP is ready, configure MTRRs and go to sleep */ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); STOP_CAR_AND_CPU(); + printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid); @@ -912,6 +907,7 @@ printk(BIOS_DEBUG, " done\n"); } +#ifdef UNUSED_CODE static void cpuInitializeMCA(void) { /* Clears Machine Check Architecture (MCA) registers, which power on @@ -939,6 +935,7 @@ } } } +#endif /** * finalize_node_setup() Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Jul 8 02:37:23 2010 (r5659) @@ -191,7 +191,7 @@ printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(u32 bsp_apicid) +void allow_all_aps_stop(u32 bsp_apicid) { // allow aps to stop Modified: trunk/src/cpu/amd/quadcore/quadcore_id.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore_id.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/cpu/amd/quadcore/quadcore_id.c Thu Jul 8 02:37:23 2010 (r5659) @@ -32,7 +32,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static u32 get_initial_apicid(void) +u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xff); } @@ -67,10 +67,12 @@ return id; } +#ifdef UNUSED_CODE static u32 get_core_num(void) { return (cpuid_ecx(0x80000008) & 0xff); } +#endif static struct node_core_id get_node_core_id_x(void) { Modified: trunk/src/include/cpu/amd/multicore.h ============================================================================== --- trunk/src/include/cpu/amd/multicore.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/include/cpu/amd/multicore.h Thu Jul 8 02:37:23 2010 (r5659) @@ -41,6 +41,8 @@ #else void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); +void allow_all_aps_stop(u32 bsp_apicid); #endif +u32 get_initial_apicid(void); #endif /* CPU_AMD_QUADCORE_H */ Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Thu Jul 8 02:37:23 2010 (r5659) @@ -1169,8 +1169,16 @@ #endif -#ifndef __ROMCC__ +#ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); + +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 + offset_pci_dev, u32 offset_io_base); + +void setup_resource_map_x(const u32 *register_values, u32 max); #endif #endif /* AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Jul 8 02:37:23 2010 (r5659) @@ -111,8 +111,6 @@ //#include "../amdmct/mct/mctardk5.c" #endif -#include "../amdmct/mct/mct_fd.c" - #endif /* DDR2 */ int mctRead_SPD(u32 smaddr, u32 reg) Modified: trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Thu Jul 8 02:37:23 2010 (r5659) @@ -28,7 +28,7 @@ pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword); } - +#ifdef UNUSED_CODE static u32 get_htic_bit(u8 i, u8 bit) { u32 dword; @@ -47,6 +47,7 @@ if(get_htic_bit(0, 9)) return; } } +#endif static void set_sysinfo_in_ram(u32 val) { Modified: trunk/src/northbridge/amd/amdfam10/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Thu Jul 8 02:37:23 2010 (r5659) @@ -41,9 +41,7 @@ } -static void setup_resource_map_offset(const u32 *register_values, - u32 max, u32 offset_pci_dev, - u32 offset_io_base) +void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; // print_debug("setting up resource map offset...."); @@ -66,8 +64,7 @@ #define RES_PORT_IO_32 0x20 #define RES_MEM_IO 0x40 -static void setup_resource_map_x_offset(const u32 *register_values, u32 max, - u32 offset_pci_dev, u32 offset_io_base) +void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; @@ -133,7 +130,8 @@ print_debug("done.\n"); #endif } -static void setup_resource_map_x(const u32 *register_values, u32 max) + +void setup_resource_map_x(const u32 *register_values, u32 max) { u32 i; Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mct.h Thu Jul 8 02:37:23 2010 (r5659) @@ -538,7 +538,6 @@ void K8FECCInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -unsigned amd_FD_support(void); void amd_MCTInit(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); Modified: trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Thu Jul 8 02:37:23 2010 (r5659) @@ -375,7 +375,7 @@ *enabled = 0; } - +#ifdef UNUSED_CODE static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) { u32 tmp; @@ -387,6 +387,7 @@ } return 0; } +#endif void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Thu Jul 8 02:37:23 2010 (r5659) @@ -70,13 +70,12 @@ return MaxValue; } - - +#ifdef UNUSED_CODE static u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p) { return (val_1p & 0xff) + ((val_2p & 0xff)<<8); } - +#endif u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass) { Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Thu Jul 8 02:37:23 2010 (r5659) @@ -337,6 +337,7 @@ static void coreDelay (void); +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ /* Erratum 350 */ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -398,6 +399,7 @@ coreDelay(); } +#endif static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Modified: trunk/src/southbridge/amd/amd8111/amd8111.h ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111.h Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/southbridge/amd/amd8111/amd8111.h Thu Jul 8 02:37:23 2010 (r5659) @@ -5,4 +5,8 @@ void amd8111_enable(device_t dev); +#ifdef __PRE_RAM__ +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif + #endif /* AMD8111_H */ Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Wed Jul 7 23:59:06 2010 (r5658) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Thu Jul 8 02:37:23 2010 (r5659) @@ -1,3 +1,4 @@ +#include "amd8111.h" #include <reset.h> /* by yhlu 2005.10 */ @@ -45,7 +46,7 @@ outb(0x0e, 0x0cf9); // make sure cf9 is enabled } -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { device_t dev;

1 0

Re: [coreboot] PATCH: Fix CMOS Tables support for all boards.
by Myles Watson 08 Jul '10

08 Jul '10

On Thu, Jun 24, 2010 at 7:08 AM, Edwin Beasant <edwin_beasant(a)virtensys.com> wrote: > Re-integrated the “USE_OPTION_TABLE” code so that it will compile for all > boards that define it at configure time. > > Made USE_OPTION_TABLE dependant on HAVE_OPTION_TABLE > > Signed-off-by: Edwin Beasant edwin_beasant(a)virtensys.com I updated your patch to: - Have a default value for USE_OPTION_TABLE even when HAVE_OPTION_TABLE isn't defined - Pass abuild with USE_OPTION_TABLE defaulting to y or n use_options.diff: Your patch, slightly modified options_fixup.diff: Fix boards to include the .h file instead of the .c file have_option_polarity.diff: Default to no cmos.layout file so it can be selected (like most other options) Patch for testing with USE_OPTION_TABLE defaulting to y use_option_default.diff I think it would make sense to default to using the option table if it is present. A next step might be to remove the "default" parameter from read_option and make it get the default from option_table.h. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 8

[commit] r5658 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx include/cpu/amd northbridge/amd/amdk8 southbridge/amd/rs780 southbridge/amd/sb600 southbridge/amd/sb700
by repository service 07 Jul '10

07 Jul '10

Author: stepan Date: Wed Jul 7 23:59:06 2010 New Revision: 5658 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5658 Log: fix some more warnings Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/include/cpu/amd/multicore.h trunk/src/northbridge/amd/amdk8/amdk8.h trunk/src/northbridge/amd/amdk8/amdk8_f.h trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/southbridge/amd/rs780/rs780_gfx.c trunk/src/southbridge/amd/sb600/sb600_smbus.c trunk/src/southbridge/amd/sb600/sb600_smbus.h trunk/src/southbridge/amd/sb700/sb700.h trunk/src/southbridge/amd/sb700/sb700_early_setup.c trunk/src/southbridge/amd/sb700/sb700_smbus.c trunk/src/southbridge/amd/sb700/sb700_smbus.h Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -244,7 +244,7 @@ } } -static void wait_all_other_cores_started(u32 bsp_apicid) +void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 printk(BIOS_DEBUG, "started ap apicid: "); Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -178,12 +178,12 @@ } } -static void wait_all_aps_started(u32 bsp_apicid) +void wait_all_aps_started(u32 bsp_apicid) { for_each_ap(bsp_apicid, 0, wait_ap_started, (void *)0); } -static void wait_all_other_cores_started(u32 bsp_apicid) +void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 printk(BIOS_DEBUG, "started ap apicid: "); Modified: trunk/src/include/cpu/amd/multicore.h ============================================================================== --- trunk/src/include/cpu/amd/multicore.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/include/cpu/amd/multicore.h Wed Jul 7 23:59:06 2010 (r5658) @@ -38,6 +38,9 @@ struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); +#else +void wait_all_other_cores_started(u32 bsp_apicid); +void wait_all_aps_started(u32 bsp_apicid); #endif #endif /* CPU_AMD_QUADCORE_H */ Modified: trunk/src/northbridge/amd/amdk8/amdk8.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/amdk8.h Wed Jul 7 23:59:06 2010 (r5658) @@ -8,8 +8,9 @@ #include "amdk8_pre_f.h" #endif -#ifndef __ROMCC__ +#ifdef __PRE_RAM__ void showallroutes(int level, device_t dev); +void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); #endif #endif /* AMDK8_H */ Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Jul 7 23:59:06 2010 (r5658) @@ -1,6 +1,6 @@ #ifndef AMDK8_F_H - #define AMDK8_F_H + /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 Modified: trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h Wed Jul 7 23:59:06 2010 (r5658) @@ -1,5 +1,4 @@ #ifndef AMDK8_PRE_F_H - #define AMDK8_PRE_F_H /* Definitions of various K8 registers */ Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Jul 7 23:59:06 2010 (r5658) @@ -206,12 +206,12 @@ print_spew(" done.\n"); } +#if CONFIG_MAX_PHYSICAL_CPUS > 1 static void fill_row(u8 node, u8 row, u32 value) { pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); } -#if CONFIG_MAX_PHYSICAL_CPUS > 1 static u8 link_to_register(int ldt) { /* @@ -447,28 +447,33 @@ } #if CROSS_BAR_47_56 -static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) { +static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) +{ uint32_t val; val = get_row(source, dest); val -= link_connection(source, kickout)<<16; fill_row(source, dest, val); } -static void opt_broadcast_rt_group(const u8 *conn, int num) { +static void opt_broadcast_rt_group(const u8 *conn, int num) +{ int i; for(i=0; i<num; i+=3) { opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); } } -static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) { + +static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) +{ uint32_t val; val = get_row(source, dest); val += link_connection(source, kickout)<<16; fill_row(source, dest, val); } -static void opt_broadcast_rt_plus_group(const u8 *conn, int num) { +static void opt_broadcast_rt_plus_group(const u8 *conn, int num) +{ int i; for(i=0; i<num; i+=3) { @@ -477,27 +482,22 @@ } #endif -static void setup_row_direct(u8 source, u8 dest, u8 linkn){ +static void setup_row_direct(u8 source, u8 dest, u8 linkn) +{ setup_row_direct_x(source, source, dest, linkn); } -static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){ +static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn) +{ setup_row_direct_x(7, source, dest, linkn); } static void setup_temp_row(u8 source, u8 dest) { - /* copy val from (source, dest) to (source,7) */ - fill_row(source,7,get_row(source,dest)); + /* copy value from (source, dest) to (source,7) */ + fill_row(source, 7, get_row(source, dest)); } -#if 0 -static void clear_temp_row(u8 source) -{ - fill_row(source, 7, DEFAULT); -} -#endif - static void setup_remote_node(u8 node) { static const uint8_t pci_reg[] = { @@ -670,7 +670,8 @@ } #if CONFIG_MAX_PHYSICAL_CPUS > 2 -static int optimize_connection_group(const u8 *opt_conn, int num) { +static int optimize_connection_group(const u8 *opt_conn, int num) +{ int needs_reset = 0; int i; for(i=0; i<num; i+=2) { Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Wed Jul 7 23:59:06 2010 (r5658) @@ -1717,6 +1717,7 @@ return reg; } +#if CONFIG_MEM_TRAIN_SEQ == 1 static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k) { msr_t msr; @@ -1730,6 +1731,7 @@ msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM, msr); } +#endif static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) { @@ -1802,6 +1804,7 @@ } +#if CONFIG_MEM_TRAIN_SEQ == 1 static unsigned get_htic_bit(unsigned i, unsigned bit) { uint32_t dword; @@ -1816,6 +1819,7 @@ if(get_htic_bit(0, 9)) return; } } +#endif static void set_sysinfo_in_ram(unsigned val) { Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Jul 7 23:59:06 2010 (r5658) @@ -1,6 +1,8 @@ +#include "amdk8.h" + #define RES_DEBUG 0 -static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) +void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) { int i; #if RES_DEBUG Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Jul 7 23:59:06 2010 (r5658) @@ -96,33 +96,33 @@ MMIORANGE MMIO[8], CreativeMMIO[8]; +#define CIM_STATUS u32 +#define CIM_SUCCESS 0x00000000 +#define CIM_ERROR 0x80000000 +#define CIM_UNSUPPORTED 0x80000001 +#define CIM_DISABLEPORT 0x80000002 + +#define MMIO_ATTRIB_NP_ONLY 1 +#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 +#define MMIO_ATTRIB_SKIP_ZERO 1<<2 + +#ifdef DONT_TRUST_RESOURCE_ALLOCATION static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) { int i; - for (i=0; i<8; i++) - { + for (i=0; i<8; i++) { if (pMMIO[i].Limit == 0) return &pMMIO[i]; } return 0; } + static void FreeMMIO(MMIORANGE* pMMIO) { pMMIO->Base = 0; pMMIO->Limit = 0; } -#define CIM_STATUS u32 -#define CIM_SUCCESS 0x00000000 -#define CIM_ERROR 0x80000000 -#define CIM_UNSUPPORTED 0x80000001 -#define CIM_DISABLEPORT 0x80000002 - -#define MMIO_ATTRIB_NP_ONLY 1 -#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 -#define MMIO_ATTRIB_SKIP_ZERO 1<<2 - -#ifdef DONT_TRUST_RESOURCE_ALLOCATION static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; @@ -584,7 +584,6 @@ { u32 l_dword; int i; - device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); msr_t sysmem; @@ -617,7 +616,7 @@ /* LPC DMA Deadlock workaround? */ /* GFX_InitCommon*/ - k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); l_dword = pci_read_config32(k8_f0, 0x68); l_dword &= ~(3 << 21); l_dword |= (1 << 21); @@ -632,7 +631,7 @@ #if (CONFIG_GFXUMA == 1) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ - k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_smbus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb600/sb600_smbus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -60,7 +60,7 @@ return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -87,8 +87,7 @@ return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, - u8 val) +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_smbus.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb600/sb600_smbus.h Wed Jul 7 23:59:06 2010 (r5658) @@ -20,8 +20,6 @@ #ifndef SB600_SMBUS_H #define SB600_SMBUS_H -//#include <stdint.h> - #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2 @@ -58,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700.h Wed Jul 7 23:59:06 2010 (r5658) @@ -49,4 +49,9 @@ void sb700_enable(device_t dev); +#ifdef __PRE_RAM__ +void sb700_lpc_port80(void); +void sb700_pci_port80(void); +#endif + #endif /* SB700_H */ Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Jul 7 23:59:06 2010 (r5658) @@ -231,7 +231,7 @@ outb(0x06, 0x0cf9); } -static void sb700_pci_port80(void) +void sb700_pci_port80(void) { u8 byte; device_t dev; @@ -276,7 +276,7 @@ pci_write_config8(dev, 0x4A, byte); } -static void sb700_lpc_port80(void) +void sb700_lpc_port80(void) { u8 byte; device_t dev; Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.c Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.c Wed Jul 7 23:59:06 2010 (r5658) @@ -63,7 +63,7 @@ return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -90,7 +90,7 @@ return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.h Wed Jul 7 19:51:41 2010 (r5657) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.h Wed Jul 7 23:59:06 2010 (r5658) @@ -56,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);

1 0

[PATCH] warnings
by Myles Watson 07 Jul '10

07 Jul '10

Kill a few more warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 3

mconf of libpayload
by baiyin cai 07 Jul '10

07 Jul '10

hi, as what you mentioned yesterday, i tried to make to use Makefile to load the libpayload kconfig instead of using "source" command. I can successfully load libpayload's config by modifying some code of the /util/kconfig/Makefile but the only problem left now is that i can not make them saved in separate files. There is a env variable "KCONFIG_CONFIG" which is used to indicate the file to save the configuration. i can make it work in the main frame of Makefile by "export KCONFIG_CONFIG=lib.config" but it can not work while i put this command under the rules. which looks like > memuconfig: > $(Q)export KCONFIG_CONFIG=.config > libpayload: > $(Q)export KCONFIG_CONFIG=lib.config > in this case i can not change this variable. Is there any suggestion about this? i cc this mail to the coreboot list, there may some one known this problem.

2 1

[commit] r5657 - trunk/src/northbridge/via/vx800
by repository service 07 Jul '10

07 Jul '10

Author: stepan Date: Wed Jul 7 19:51:41 2010 New Revision: 5657 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5657 Log: fix some warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/via/vx800/pci_rawops.h trunk/src/northbridge/via/vx800/vx800.h trunk/src/northbridge/via/vx800/vx800_early_serial.c trunk/src/northbridge/via/vx800/vx800_early_smbus.c Modified: trunk/src/northbridge/via/vx800/pci_rawops.h ============================================================================== --- trunk/src/northbridge/via/vx800/pci_rawops.h Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/pci_rawops.h Wed Jul 7 19:51:41 2010 (r5657) @@ -43,30 +43,6 @@ pci_write_config8(dev, where, data); } -static void pci_modify_config16(device_t dev, unsigned where, u16 orval, u16 mask) -{ - u16 data = pci_read_config16(dev, where); - data &= (~mask); - data |= orval; - pci_write_config16(dev, where, data); -} - -static void pci_modify_config32(device_t dev, unsigned where, u32 orval, u32 mask) -{ - u32 data = pci_read_config32(dev, where); - data &= (~mask); - data |= orval; - pci_write_config32(dev, where, data); -} - -static void io_modify_config8(u16 where, u8 orval, u8 mask) -{ - u8 data = inb(where); - data &= (~mask); - data |= orval; - outb(data, where); -} - static void via_pci_inittable(u8 chipversion, const struct VIA_PCI_REG_INIT_TABLE *initdata) { Modified: trunk/src/northbridge/via/vx800/vx800.h ============================================================================== --- trunk/src/northbridge/via/vx800/vx800.h Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/vx800.h Wed Jul 7 19:51:41 2010 (r5657) @@ -26,6 +26,17 @@ { } #endif + +#ifdef __PRE_RAM__ +/* vx800_early_smbus.c */ +struct mem_controller; +void enable_smbus(void); +void smbus_fixup(const struct mem_controller *mem_ctrl); + +/* vx800_early_serial.c */ +void enable_vx800_serial(void); +#endif + //#define REV_B0 0x10 #define REV_B1 0x11 //#define REV_B2 0x12 Modified: trunk/src/northbridge/via/vx800/vx800_early_serial.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_serial.c Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/vx800_early_serial.c Wed Jul 7 19:51:41 2010 (r5657) @@ -27,12 +27,6 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void vx800_writesuper(uint8_t reg, uint8_t val) -{ - outb(reg, SIO_BASE); - outb(val, SIO_DATA); -} - static void vx800_writepnpaddr(uint8_t val) { outb(val, 0x2e); @@ -59,7 +53,7 @@ mainboard */ -static void enable_vx800_serial(void) +void enable_vx800_serial(void) { outb(6, 0x80); outb(0x03, 0x22); Modified: trunk/src/northbridge/via/vx800/vx800_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Jul 7 17:09:09 2010 (r5656) +++ trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Jul 7 19:51:41 2010 (r5657) @@ -19,6 +19,7 @@ #include <device/pci_ids.h> #include "vx800.h" + #define SMBUS_IO_BASE 0x0500 //from award bios #define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here @@ -137,14 +138,11 @@ return val; } -static void enable_smbus(void) +void enable_smbus(void) { device_t dev; - dev = - pci_locate_device(PCI_ID - (PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), - 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); if (dev == PCI_DEV_INVALID) { /* This won't display text if enable_smbus() is before serial init */ @@ -183,7 +181,7 @@ * * @param mem_ctrl The memory controller and SMBus addresses. */ -static void smbus_fixup(const struct mem_controller *mem_ctrl) +void smbus_fixup(const struct mem_controller *mem_ctrl) { int i, ram_slots, current_slot = 0; u8 result = 0;

1 0

SIS645DX and SIS962
by r. ozgur doruk 07 Jul '10

07 Jul '10

Hi folks, does anyone have the datasheets and related technical documents of SIS645DX and SIS962 chipset. Or at least the technical documents concerning the chipset SIS761 and SIS966 which are the member of the chipsets supported by coreboot. Thanx for all, Ozgur

1 0

[PATCH] warnings -> errors
by Stefan Reinauer 07 Jul '10

07 Jul '10

Hi, I suggest applying the following patch to encourage folks to get their warnings fixed and cleaned up. Stefan

1 0

[commit] r5656 - in trunk/src: mainboard/intel/d810e2cb mainboard/kontron/986lcd-m northbridge/intel/i82810 southbridge/intel/i82801bx
by repository service 07 Jul '10

07 Jul '10

Author: myles Date: Wed Jul 7 17:09:09 2010 New Revision: 5656 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5656 Log: Kill a few more warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/intel/d810e2cb/Kconfig trunk/src/mainboard/kontron/986lcd-m/mptable.c trunk/src/northbridge/intel/i82810/raminit.c trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Modified: trunk/src/mainboard/intel/d810e2cb/Kconfig ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/Kconfig Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/mainboard/intel/d810e2cb/Kconfig Wed Jul 7 17:09:09 2010 (r5656) @@ -25,6 +25,8 @@ select SOUTHBRIDGE_INTEL_I82801BX select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE + select HAVE_HARD_RESET + select USE_WATCHDOG_ON_BOOT select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select HAVE_MAINBOARD_RESOURCES Modified: trunk/src/mainboard/kontron/986lcd-m/mptable.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mptable.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/mainboard/kontron/986lcd-m/mptable.c Wed Jul 7 17:09:09 2010 (r5656) @@ -32,7 +32,6 @@ static const char productid[12] = "986LCD-M "; struct mp_config_table *mc; struct device *riser = NULL, *firewire = NULL; - int i; int firewire_bus = 0, riser_bus = 0, isa_bus; int ioapic_id; Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/northbridge/intel/i82810/raminit.c Wed Jul 7 17:09:09 2010 (r5656) @@ -365,7 +365,7 @@ static void sdram_set_registers(void) { u8 reg8; - u16 reg16, did; + u16 did; did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Wed Jul 7 17:09:09 2010 (r5656) @@ -65,17 +65,3 @@ { return do_smbus_read_byte(device, address); } - -static void smbus_write_byte(unsigned device, unsigned address, - unsigned char val) -{ - print_err("Unimplemented smbus_write_byte() called\n"); - return; -} - -static inline int smbus_write_block(unsigned device, unsigned length, - unsigned cmd, unsigned data1, - unsigned data2) -{ - return do_smbus_write_block(device, length, cmd, data1, data2); -} Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Wed Jul 7 17:09:09 2010 (r5656) @@ -72,7 +72,7 @@ * specific IRQ values in your mainboards Config.lb. */ -void i82801bx_enable_apic(struct device *dev) +static void i82801bx_enable_apic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; @@ -106,7 +106,7 @@ *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } -void i82801bx_enable_serial_irqs(struct device *dev) +static void i82801bx_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit. */ pci_write_config8(dev, SERIRQ_CNTL, @@ -211,7 +211,7 @@ pci_write_config8(dev, GPIO_CNTL, 0x10); } -void i82801bx_rtc_init(struct device *dev) +static void i82801bx_rtc_init(struct device *dev) { uint8_t reg8; uint32_t reg32; @@ -231,7 +231,7 @@ pci_write_config8(dev, RTC_CONF, 0x04); } -void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) +static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) { uint16_t reg16; int i; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c Wed Jul 7 17:09:09 2010 (r5656) @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <reset.h> void hard_reset(void) { Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Wed Jul 7 17:09:09 2010 (r5656) @@ -110,74 +110,3 @@ return byte; } -/* This function is neither used nor tested by me (Corey Osgood), the author -(Yinghai) probably tested/used it on i82801er */ -static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, - unsigned data1, unsigned data2) -{ -#warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\n"); -#if 0 - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - unsigned char stat; - int i; - - /* Clear the PM timeout flags, SECOND_TO_STS */ - outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { - return -2; - } - - /* Setup transaction */ - /* Obtain ownership */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for (stat = 0; (stat & 0x40) == 0;) { - stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - /* Clear the done bit */ - outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); - /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - - /* Set the command address */ - outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); - - /* Set the block length */ - outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); - - /* Try sending out the first byte of data here */ - byte = (data1 >> (0)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - /* Issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, - SMBUS_IO_BASE + SMBHSTCTL); - - for (i = 0; i < length; i++) { - - /* Poll for transaction completion */ - if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { - return -3; - } - - /* Load the next byte */ - if (i > 3) - byte = (data2 >> (i % 4)) & 0x0ff; - else - byte = (data1 >> (i)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - - /* Clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - - print_debug("SMBUS Block complete\n"); - return 0; -#endif -} Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Tue Jul 6 23:40:11 2010 (r5655) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Wed Jul 7 17:09:09 2010 (r5656) @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> +#include <watchdog.h> /* TODO: I'm fairly sure the same functionality is provided elsewhere. */

1 0

Re: [coreboot] Position Independent Code
by Stefan Reinauer 07 Jul '10

07 Jul '10

* anders(a)jenbo.dk <anders(a)jenbo.dk> [100707 15:47]: > If you want to do this to test out an image before flashing it, I think that > you will run in to some issues since a lot of the stuff that coreboot performs > will already have been done and so could fail or misbehave. Yes. Testing a BIOS image in GRUB will not give you any reliable results. If you want to test payloads or some such, look at simnow or qemu. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

1 0

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coreboot July 2010