coreboot July 2010

coreboot@coreboot.org

57 participants
142 discussions

payload bayou can not be compiled.
by baiyin cai 06 Jul '10

06 Jul '10

/home/work/coreboot-work/payloads/bayou/build/libpayload/bin/lpgcc -Wall -Werror -Os -DCONFIG_BUILTIN_LAR -DCONFIG_LZMA -DCONFIG_NRV2B -I/home/work/coreboot-work/payloads/bayou/build/libpayload/include -c -o main.o main.c basename: missing operand Try `basename --help' for more information. In file included from main.c:20: hi all, i am trying to use bayou as an payload. but i find it can not be build. the error message seems like: > bayou.h:60: error: field ‘stat’ has incomplete type > cc1: warnings being treated as errors > bayou.h:85: error: ‘struct LAR’ declared inside parameter list > bayou.h:85: error: its scope is only this definition or declaration, which > is probably not what you want > main.c: In function ‘main’: > main.c:34: error: implicit declaration of function ‘openlar’ > main.c:34: error: assignment makes pointer from integer without a cast > main.c:41: error: passing argument 1 of ‘get_configuration’ from > incompatible pointer type > bayou.h:85: note: expected ‘struct LAR *’ but argument is of type ‘struct > LAR *’ > make: *** [main.o] Error 1 > any suggestions ?

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The firmware traps in SIS6xx/7xx/96x type chipsets
by r. ozgur doruk 06 Jul '10

06 Jul '10

Hello, I have Pentium4 laptop motherboard of which BIOS chip is soldered out by some guys and it doesn't read newly programmed bios chip (a SST49lf080a) as far as I understand since it even does not beep. And no harddisk signal, no video and so on. In order to diagnose I have written a VHDL code (citing Andy Green's Milksop experiment) and then program my code on a Xilinx CPLD and connect it to the LPC debug board connector on the motherboard which has the signals LAD0 - 3, LRST, LFRAME, LCLK. The job of my VHDL code is to convert the LPC protocol to a parallel address and data combination so that I can at least trace what the motherboard responds. When I do that, if I give a long sync to the motherboard after the first address is received by the PLD I understand that the motherboard starts to fetch the flash codes from the adress 0xFFFFFFD0. In fact this conforms to the script written by the current coreboot developer as the SIS 966 has a firmware trap in the memory region starting from 0xFFFFFFD0. When I operate the system giving a ready sync after each address reception to the PLD the system runs until showing 0xFFFFFFDF and the value stays in the CPLD address output busses. The same thing is observed when the board is operated without the CPU in its socket. I operate the mainboard without the CPU using a small hack connecting one of the VID pins to the ground, thermal diode output to the vcc core, sckocc to the ground and thermtrip to the vcc core. By that board thinks that CPU is connected. The interesting thing is that, when I measure the powergood and the reset inputs to the processor (by plugging the wires to the wholes as no processor is there). After the PLD address output is 0xFFFFFFDF both RESET and POWERGOOD inputs become active so I think that the southbridge/northbridge mechanism is alive. I also measured all of the processor socket holes one by one and found no problematic conditions on the socket contacts. The processor is heating up when operated without the heat sink and I also noticed that thermtrip mechanism is also working as it shutdown after a high value of temperature. Because of that I think that the processor is defective but again I can not be sure about that because of this firmware trap feature of the chipsets I mention. So are those firmware traps in the SIS chipsets are effective on the boot process of the processor? Or any other reasons? Can I hear about your ideas? Thanks for all considerations Ozgur

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H8DME-2
by Daniel J. Celta 06 Jul '10

06 Jul '10

Has anyone updated this Supermicro server Board BIOS for the H8DME-2...... I have installed FC10, (i was able to complete this installation by turning of the RAID configuration in the BIOS), and now I am having trouble when trying to upgrade the Operating system to FC13. I suspect, if I update the BIOS, I currently have the version of the BIOS that came pre-installed with the server, I may be able to upgrade to FC13. One thing I like to mention, when running "make menuconfig" I was not sure of the ROM Chip size, and used the largest available setting 4MB. - How can I check the proper setting for this parameter???? So now, I have created the coreboot.rom, and think I am ready to run "flashrom"....... - Is there anything else I need to check before I pull the trigger??? - Has anyone had any problems I should be aware of???? Thanks Daniel

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Re: [coreboot] minimum linuxbios
by anders＠jenbo.dk 06 Jul '10

06 Jul '10

You could remove RAM and probably also CPU from the system then, and you wouldn't need to start the south or north bridge, just the super io. Just find the first debug message after serial init and change it to what you want to output. Mvh Anders ----- Reply message ----- Fra: "Masoud Fatollahy" <masoudf(a)t2data.se> Dato: tir., jul. 6, 2010 10:47 Emne: [coreboot] minimum linuxbios Til: <coreboot(a)coreboot.org>

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Re: [coreboot] Re H8DME-2
by Daniel J. Celta 06 Jul '10

06 Jul '10

Anders, Thanks you, I can see how to flash as long as I can boot the machine, otherwise I am in trouble. I wiould have no means to get to that chip and flash it back with the original BIOS........ :( Is there a way to test if the LinuxBIOS would work, without locking myself out....... ???? Has anyone done this on this board????? Thanks On Mon, Jul 5, 2010 at 8:59 PM, Anders Jenbo <anders(a)jenbo.dk> wrote: > You can flash the original image in the same way as you are going to do > with the coreboot image. flashrom -w imagename.rom > > But if you board fails to boot then you will need to have access to some > thing else that can flash that chip, one option is another motherboard > that uses the same type of chip, or a rom flasher for the type of chip > you have. This requires that the chip is socketed, so that you can > remove it from the board as you write back the old image. > > Another option is to use what is known as a tophat, it will allow you to > install a second flash rom on top of the once that is soldered on to the > board (this only works with plcc32 chips as fare as i know). > > -Anders > > man, 05 07 2010 kl. 20:53 -0500, skrev Daniel J. Celta: > > Ok I was able to determine the ROM chip of the server..... Thank you > > very much... > > > > Now, I did save the original BIOS information using "flashrom -r > > <filename>" > > > > But, not sure I know how to rebuild back the BIOS from this file in > > case needed. > > > > Do you have any suggestions???? > > > > Thanks > > > > On Mon, Jul 5, 2010 at 7:12 PM, anders(a)jenbo.dk <anders(a)jenbo.dk> > > wrote: > > Run flashrom with no parameters and it should tell you what > > Rom chip you have. > > > > Before you pull the trigger you should make sure that you have > > a way to recover the original BIOS (with out the use of the > > computer you are doing this to). > > > > Mvh Anders > > > > ----- Reply message ----- > > Fra: "Daniel J. Celta" <dcelta(a)gmail.com> > > Dato: man., jul. 5, 2010 23:02 > > Emne: [coreboot] H8DME-2 > > Til: <coreboot(a)coreboot.org> > > > > > > Has anyone updated this Supermicro server Board BIOS for the > > H8DME-2...... > > > > I have installed FC10, (i was able to complete this > > installation by turning of the RAID configuration in the > > BIOS), and now I am having trouble when trying to upgrade the > > Operating system to FC13. > > > > > > I suspect, if I update the BIOS, I currently have the version > > of the BIOS that came pre-installed with the server, I may be > > able to upgrade to FC13. > > > > One thing I like to mention, when running "make menuconfig" I > > was not sure of the ROM Chip size, and used the largest > > available setting 4MB. > > > > - How can I check the proper setting for this parameter???? > > > > > > > > So now, I have created the coreboot.rom, and think I am ready > > to run "flashrom"....... > > > > - Is there anything else I need to check before I pull the > > trigger??? > > > > - Has anyone had any problems I should be aware of???? > > > > > > Thanks > > > > Daniel > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > > >

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minimum linuxbios
by Masoud Fatollahy 06 Jul '10

06 Jul '10

Hi, I am working to make a minimal linuxbios without any payload or linux kernel, I just want to see a nice hello word string on the serial port and nothing else. is it possible to make such a bios? also to setup only the necessary HW registers and memory to see the printout message. how should i do this? thanks, /Masoud

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Fwd: Re H8DME-2
by Daniel J. Celta 06 Jul '10

06 Jul '10

Ok I was able to determine the ROM chip of the server..... Thank you very much... Now, I did save the original BIOS information using "flashrom -r <filename>" But, not sure I know how to rebuild back the BIOS from this file in case needed. Do you have any suggestions???? Thanks On Mon, Jul 5, 2010 at 7:12 PM, anders(a)jenbo.dk <anders(a)jenbo.dk> wrote: > Run flashrom with no parameters and it should tell you what Rom chip you > have. > > Before you pull the trigger you should make sure that you have a way to > recover the original BIOS (with out the use of the computer you are doing > this to). > > Mvh Anders > > ----- Reply message ----- > Fra: "Daniel J. Celta" <dcelta(a)gmail.com> > Dato: man., jul. 5, 2010 23:02 > Emne: [coreboot] H8DME-2 > Til: <coreboot(a)coreboot.org> > > Has anyone updated this Supermicro server Board BIOS for the H8DME-2...... > > I have installed FC10, (i was able to complete this installation by turning > of the RAID configuration in the BIOS), and now I am having trouble when > trying to upgrade the Operating system to FC13. > > > I suspect, if I update the BIOS, I currently have the version of the BIOS > that came pre-installed with the server, I may be able to upgrade to FC13. > > One thing I like to mention, when running "make menuconfig" I was not sure > of the ROM Chip size, and used the largest available setting 4MB. > > - How can I check the proper setting for this parameter???? > > > > So now, I have created the coreboot.rom, and think I am ready to run > "flashrom"....... > > - Is there anything else I need to check before I pull the trigger??? > > - Has anyone had any problems I should be aware of???? > > > Thanks > > Daniel > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re H8DME-2
by anders＠jenbo.dk 06 Jul '10

06 Jul '10

Run flashrom with no parameters and it should tell you what Rom chip you have. Before you pull the trigger you should make sure that you have a way to recover the original BIOS (with out the use of the computer you are doing this to). Mvh Anders ----- Reply message ----- Fra: "Daniel J. Celta" <dcelta(a)gmail.com> Dato: man., jul. 5, 2010 23:02 Emne: [coreboot] H8DME-2 Til: <coreboot(a)coreboot.org>

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Trac reminder: list of new ticket(s)
by coreboot tracker 05 Jul '10

05 Jul '10

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About undocumented i945gm+ich7m registers
by QJ Miao 03 Jul '10

03 Jul '10

Hi, When reading coreboot i945gm+ich7m code, I found many configured registers are not existed in intel published datasheets. Where I can get these register definitions? and these registers must be initialized? Thanks

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coreboot July 2010