coreboot May 2010

coreboot@coreboot.org

59 participants
300 discussions

by Stefan Reinauer

A while back I sent a fix for the MCP55 azalia driver which prevented coreboot from hanging and at the same time allowed per-board Azalia VERBs. The attached patch implements per-board VERBs for all MCP55 boards, and as I don't have the correct VERBs for all boards, uses the default MCP55 VERB for all of them. Stefan

10 years, 9 months

[commit] r5600 - in trunk/src: cpu/x86/smm southbridge/intel/i82801dx southbridge/intel/i82801gx

by repository service

Author: stepan Date: Sun May 30 15:44:32 2010 New Revision: 5600 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5600 Log: don't generate C source code file but use objcopy to include the SMM blob. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/x86/smm/Makefile.inc trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c Modified: trunk/src/cpu/x86/smm/Makefile.inc ============================================================================== --- trunk/src/cpu/x86/smm/Makefile.inc Sun May 30 14:56:17 2010 (r5599) +++ trunk/src/cpu/x86/smm/Makefile.inc Sun May 30 15:44:32 2010 (r5600) @@ -1,12 +1,11 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008 coresystems GmbH +## Copyright (C) 2008-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. +## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -19,7 +18,7 @@ ## obj-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.o -obj-$(CONFIG_HAVE_SMI_HANDLER) += smm_bin.o +obj-$(CONFIG_HAVE_SMI_HANDLER) += smm_wrap.o smmobj-y += smmhandler.o smmobj-y += smihandler.o @@ -33,10 +32,9 @@ $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm -$(obj)/cpu/x86/smm/smm_bin.c: $(obj)/cpu/x86/smm/smm - (echo 'unsigned char smm[] = {'; od -vtx1 $(obj)/cpu/x86/smm/smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c $(obj)/cpu/x86/smm/smm |awk '{print $$1;}' ; echo ';') > $@ - -$(obj)/cpu/x86/smm/smm_bin.o: $(obj)/cpu/x86/smm/smm_bin.c - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(CFLAGS) -c -o $@ $< +# change to the target path because objcopy will use the path name in its +# ELF symbol names. +$(obj)/cpu/x86/smm/smm_wrap.o: $(obj)/cpu/x86/smm/smm + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(obj)/cpu/x86/smm; $(OBJCOPY) -I binary smm -O elf32-i386 -B i386 smm_wrap.o Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c Sun May 30 14:56:17 2010 (r5599) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c Sun May 30 15:44:32 2010 (r5600) @@ -30,8 +30,8 @@ #include <string.h> #include "i82801dx.h" -extern unsigned char smm[]; -extern unsigned int smm_len; +extern unsigned char _binary_smm_start; +extern unsigned char _binary_smm_size; /* I945 */ #define SMRAM 0x90 @@ -325,7 +325,7 @@ D_OPEN | G_SMRAME | C_BASE_SEG); /* copy the real SMM handler */ - memcpy((void *)0xa0000, smm, smm_len); + memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size); wbinvd(); /* close the SMM memory window and enable normal SMM */ Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c Sun May 30 14:56:17 2010 (r5599) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c Sun May 30 15:44:32 2010 (r5600) @@ -30,8 +30,8 @@ #include <string.h> #include "i82801gx.h" -extern unsigned char smm[]; -extern unsigned int smm_len; +extern unsigned char _binary_smm_start; +extern unsigned char _binary_smm_size; /* I945 */ #define SMRAM 0x9d @@ -325,7 +325,7 @@ D_OPEN | G_SMRAME | C_BASE_SEG); /* copy the real SMM handler */ - memcpy((void *)0xa0000, smm, smm_len); + memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size); wbinvd(); /* close the SMM memory window and enable normal SMM */

10 years, 9 months

Can I run coreboot on my motherboard <P35-DS3R>

by Sebastian Rust

Hey guys, I watched the presentation at the 26C3 and I'm really impressed by your work. So I wonder if i can run coreboot on my board. Forgive in case this is the wrong mailinglist. Okay here are the information: It's a GA-P35-DS3R from GYGABYTE, currently running a Intel Q8400 cpu, here the link to the vendor http://www.gigabyte.us/Support/Motherboard/BIOS_Model.aspx?ProductID=2746&v… Here is the output of lspci output: > -[0000:00]-+-00.0 Intel Corporation 82G33/G31/P35/P31 Express DRAM > Controller [8086:29c0] > +-01.0-[01]----00.0 nVidia Corporation NV43 [GeForce 6600 > GT] [10de:0140] > +-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI > Controller #4 [8086:2937] > +-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI > Controller #5 [8086:2938] > +-1a.2 Intel Corporation 82801I (ICH9 Family) USB UHCI > Controller #6 [8086:2939] > +-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI > Controller #2 [8086:293c] > +-1c.0-[02]-- > +-1c.3-[03]--+-00.0 JMicron Technology Corp. JMB362/JMB363 > Serial ATA Controller [197b:2363] > | \-00.1 JMicron Technology Corp. JMB362/JMB363 > Serial ATA Controller [197b:2363] > +-1c.4-[04]----00.0 Realtek Semiconductor Co., Ltd. > RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] > +-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI > Controller #1 [8086:2934] > +-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI > Controller #2 [8086:2935] > +-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI > Controller #3 [8086:2936] > +-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI > Controller #1 [8086:293a] > +-1e.0-[05]--+-02.0 Creative Labs SB Audigy [1102:0004] > | +-02.1 Creative Labs SB Audigy Game Port > [1102:7003] > | \-02.2 Creative Labs SB Audigy FireWire Port > [1102:4001] > +-1f.0 Intel Corporation 82801IR (ICH9R) LPC Interface > Controller [8086:2916] > +-1f.2 Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 4 > port SATA IDE Controller [8086:2920] > +-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus > Controller [8086:2930] > \-1f.5 Intel Corporation 82801I (ICH9 Family) 2 port SATA > IDE Controller [8086:2926] the superio output: > superiotool r5549 > Probing for ALi Super I/O at 0x3f0... > Failed. Returned data: id=0xffff, rev=0xff > Probing for ALi Super I/O at 0x370... > Failed. Returned data: id=0xffff, rev=0xff > Probing for Fintek Super I/O at 0x2e... > Failed. Returned data: vid=0xffff, id=0xffff > Probing for Fintek Super I/O at 0x4e... > Failed. Returned data: vid=0xffff, id=0xffff > Probing for ITE Super I/O (init=standard) at 0x2e... > Found ITE IT8718F (id=0x8718, rev=0x4) at 0x2e > Register dump: > idx 20 21 22 23 24 2b > val 87 18 04 10 00 00 > def 87 18 01 00 00 00 > LDN 0x00 (Floppy) > idx 30 60 61 70 74 f0 f1 > val 01 03 f0 06 02 00 80 > def 00 03 f0 06 02 00 00 > LDN 0x01 (COM1) > idx 30 60 61 70 f0 f1 f2 f3 > val 01 03 f8 04 00 50 00 7f > def 00 03 f8 04 00 50 00 7f > LDN 0x02 (COM2) > idx 30 60 61 70 f0 f1 f2 f3 > val 00 00 00 00 00 50 00 7f > def 00 02 f8 03 00 50 00 7f > LDN 0x03 (Parallel port) > idx 30 60 61 62 63 70 74 f0 > val 01 03 78 00 00 07 04 08 > def 00 03 78 07 78 07 03 03 > LDN 0x04 (Environment controller) > idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 > val 01 02 90 00 00 00 00 00 0e 80 8a 20 42 > def 00 02 90 02 30 09 00 00 00 00 00 NA NA > LDN 0x05 (Keyboard) > idx 30 60 61 62 63 70 71 f0 > val 01 00 60 00 64 01 02 68 > def 01 00 60 00 64 01 02 00 > LDN 0x06 (Mouse) > idx 30 70 71 f0 > val 01 0c 02 00 > def 00 0c 02 00 > LDN 0x07 (GPIO) > idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 > b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc e0 e1 > e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff > val 41 df 00 03 88 01 1d 00 00 08 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 81 c0 00 00 01 00 40 1f 00 03 08 00 00 11 00 03 08 00 00 > 00 00 00 00 00 00 10 40 00 00 00 00 08 00 00 00 00 00 52 32 01 00 > def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 > 00 00 00 00 00 00 00 00 00 01 00 00 40 00 00 01 00 00 40 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 00 00 > LDN 0x0a (Consumer IR) > idx 30 60 61 70 f0 > val 00 03 10 0b 06 > def 00 03 10 0b 00 > Probing for ITE Super I/O (init=it8761e) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8228e) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=standard) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8761e) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8228e) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... > Failed. Returned data: id=0xffff, rev=0xf > Probing for NSC Super I/O at 0x2e... > Failed. Returned data: port=0xff, port+1=0xff > Probing for NSC Super I/O at 0x4e... > Failed. Returned data: port=0xff, port+1=0xff > Probing for NSC Super I/O at 0x15c... > Failed. Returned data: port=0xff, port+1=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... > Failed. Returned data: id=0xff, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for VIA Super I/O at 0x3f0... > PCI device 1106:0686 not found. and last but not least the output from flashrom: > flashrom v0.9.2-r1017 on Linux 2.6.33-ARCH (x86_64), built with libpci > 3.1.7, GCC 4.5.0 20100520 (prerelease), little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... 3130M loops per second, 10 myus = 10 us, 100 > myus = 98 us, 1000 myus = 981 us, 10000 myus = 9896 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string system-product-name: "P35-DS3R" > DMI string system-version: " " > DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string baseboard-product-name: "P35-DS3R" > DMI string baseboard-version: "x.x" > DMI string chassis-type: "Desktop" > Found ITE Super I/O, id 8718 > Found chipset "Intel ICH9R", enabling flash write... chipset PCI ID is > 8086:2916, > 0xfff80000/0xffb80000 FWH IDSEL: 0x0 > 0xfff00000/0xffb00000 FWH IDSEL: 0x0 > 0xffe80000/0xffa80000 FWH IDSEL: 0x1 > 0xffe00000/0xffa00000 FWH IDSEL: 0x1 > 0xffd80000/0xff980000 FWH IDSEL: 0x2 > 0xffd00000/0xff900000 FWH IDSEL: 0x2 > 0xffc80000/0xff880000 FWH IDSEL: 0x3 > 0xffc00000/0xff800000 FWH IDSEL: 0x3 > 0xff700000/0xff300000 FWH IDSEL: 0x4 > 0xff600000/0xff200000 FWH IDSEL: 0x5 > 0xff500000/0xff100000 FWH IDSEL: 0x6 > 0xff400000/0xff000000 FWH IDSEL: 0x7 > 0xfff80000/0xffb80000 FWH decode enabled > 0xfff00000/0xffb00000 FWH decode enabled > 0xffe80000/0xffa80000 FWH decode disabled > 0xffe00000/0xffa00000 FWH decode disabled > 0xffd80000/0xff980000 FWH decode disabled > 0xffd00000/0xff900000 FWH decode disabled > 0xffc80000/0xff880000 FWH decode disabled > 0xffc00000/0xff800000 FWH decode disabled > 0xff700000/0xff300000 FWH decode disabled > 0xff600000/0xff200000 FWH decode disabled > 0xff500000/0xff100000 FWH decode disabled > 0xff400000/0xff000000 FWH decode disabled > Maximum FWH chip size: 0x100000 bytes > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 > (SPI) > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0x2000 (HSFS) > FLOCKDN 0, FDV 0, FDOPSS 1, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 > 0x50: 0x00000202 (FRAP) > BMWAG 0, BMRAG 0, BRWA 2, BRRA 2 > 0x54: 0x00001fff (FREG0) > 0x58: 0x00001fff (FREG1) > 0x5C: 0x00001fff (FREG2) > 0x60: 0x00001fff (FREG3) > 0x64: 0x00001fff (FREG4) > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x00414004 (SSFS, SSFC) > 0x94: 0x5006 (PREOP) > 0x96: 0x463b (OPTYPE) > 0x98: 0x05d80302 (OPMENU) > 0x9C: 0xc79f0190 (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xB0: 0x00000000 (FDOC) > Programming OPCODES... > program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 > done > SPI Read Configuration: prefetching disabled, caching enabled, OK. > This chipset supports the following protocols: FWH,SPI. > No IT87* serial flash segment enabled. > Probing for AMD Am29F010A/B, 128 KB: skipped. > Probing for AMD Am29F002(N)BB, 256 KB: skipped. > Probing for AMD Am29F002(N)BT, 256 KB: skipped. > Probing for AMD Am29F016D, 2048 KB: skipped. > Probing for AMD Am29F040B, 512 KB: skipped. > Probing for AMD Am29F080B, 1024 KB: skipped. > Probing for AMD Am29LV040B, 512 KB: skipped. > Probing for AMD Am29LV081B, 1024 KB: skipped. > Probing for ASD AE49F2008, 256 KB: skipped. > Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Atmel AT29C512, 64 KB: skipped. > Probing for Atmel AT29C010A, 128 KB: skipped. > Probing for Atmel AT29C020, 256 KB: skipped. > Probing for Atmel AT29C040A, 512 KB: skipped. > Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Atmel AT49BV512, 64 KB: skipped. > Probing for Atmel AT49F002(N), 256 KB: skipped. > Probing for Atmel AT49F002(N)T, 256 KB: skipped. > Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for AMIC A29002B, 256 KB: skipped. > Probing for AMIC A29002T, 256 KB: skipped. > Probing for AMIC A29040B, 512 KB: skipped. > Probing for AMIC A49LF040A, 512 KB: skipped. > Probing for EMST F49B002UA, 256 KB: skipped. > Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Eon EN29F010, 128 KB: skipped. > Probing for EON EN29F002(A)(N)B, 256 KB: skipped. > Probing for EON EN29F002(A)(N)T, 256 KB: skipped. > Probing for Fujitsu MBM29F004BC, 512 KB: skipped. > Probing for Fujitsu MBM29F004TC, 512 KB: skipped. > Probing for Fujitsu MBM29F400BC, 512 KB: skipped. > Probing for Fujitsu MBM29F400TC, 512 KB: skipped. > Probing for Intel 28F001BX-B, 128 KB: skipped. > Probing for Intel 28F001BX-T, 128 KB: skipped. > Probing for Intel 28F004S5, 512 KB: skipped. > Probing for Intel 28F004BV/BE-B, 512 KB: skipped. > Probing for Intel 28F004BV/BE-T, 512 KB: skipped. > Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. > Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. > Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x24, id2 0x23, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x00, id2 0x00, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Chip status register is 00 > Chip status register: Status Register Write Disable (SRWD) is not set > Chip status register: Bit 6 is not set > Chip status register: Bit 5 / Block Protect 3 (BP3) is not set > Chip status register: Bit 4 / Block Protect 2 (BP2) is not set > Chip status register: Bit 3 / Block Protect 1 (BP1) is not set > Chip status register: Bit 2 / Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address > 0xfff00000. > Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Macronix MX29F001B, 128 KB: skipped. > Probing for Macronix MX29F001T, 128 KB: skipped. > Probing for Macronix MX29F002B, 256 KB: skipped. > Probing for Macronix MX29F002T, 256 KB: skipped. > Probing for Macronix MX29LV040, 512 KB: skipped. > Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for PMC Pm29F002T, 256 KB: skipped. > Probing for PMC Pm29F002B, 256 KB: skipped. > Probing for PMC Pm39LV010, 128 KB: skipped. > Probing for PMC Pm39LV020, 256 KB: skipped. > Probing for PMC Pm39LV040, 512 KB: skipped. > Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x8b, id2 > 0x3e, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x24, id2 > 0x23, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x00, id2 > 0x00, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 > 0x13 > Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, > id2 0x13 > Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for SST SST28SF040A, 512 KB: skipped. > Probing for SST SST29EE010, 128 KB: skipped. > Probing for SST SST29LE010, 128 KB: skipped. > Probing for SST SST29EE020A, 256 KB: skipped. > Probing for SST SST29LE020, 256 KB: skipped. > Probing for SST SST39SF512, 64 KB: skipped. > Probing for SST SST39SF010A, 128 KB: skipped. > Probing for SST SST39SF020A, 256 KB: skipped. > Probing for SST SST39SF040, 512 KB: skipped. > Probing for SST SST39VF512, 64 KB: skipped. > Probing for SST SST39VF010, 128 KB: skipped. > Probing for SST SST39VF020, 256 KB: skipped. > Probing for SST SST39VF040, 512 KB: skipped. > Probing for SST SST39VF080, 1024 KB: skipped. > Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x8b, > id2 0x3e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x84, > id2 0x65, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x24, > id2 0x23, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x24, id2 > 0x23, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0x00, > id2 0x00, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x00, id2 > 0x00, id1 parity violation, id1 is normal flash content, id2 is normal > flash content > Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than > supported size 1024 kB of chipset/board/programmer for FWH interface, > probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for SST SST49LF020, 256 KB: skipped. > Probing for SST SST49LF020A, 256 KB: skipped. > Probing for SST SST49LF040, 512 KB: skipped. > Probing for SST SST49LF040B, 512 KB: skipped. > Probing for SST SST49LF080A, 1024 KB: skipped. > Probing for SST SST49LF160C, 2048 KB: skipped. > Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. > Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. > Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. > Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 > 0x2014 > Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for ST M29F002B, 256 KB: skipped. > Probing for ST M29F002T/NT, 256 KB: skipped. > Probing for ST M29F040B, 512 KB: skipped. > Probing for ST M29F400BT, 512 KB: skipped. > Probing for ST M29W010B, 128 KB: skipped. > Probing for ST M29W040B, 512 KB: skipped. > Probing for ST M29W512B, 64 KB: skipped. > Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x24, id2 0x23, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x24, id2 0x23, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x00, id2 0x00, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x00, id2 0x00, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x8b, id2 0x3e, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than > supported size 1024 kB of chipset/board/programmer for FWH interface, > probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x24, id2 0x23, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x00, id2 0x00, > id1 parity violation, id1 is normal flash content, id2 is normal flash > content > Probing for ST M50LPW116, 2048 KB: skipped. > Probing for SyncMOS S29C31004T, 512 KB: skipped. > Probing for SyncMOS S29C51001T, 128 KB: skipped. > Probing for SyncMOS S29C51002T, 256 KB: skipped. > Probing for SyncMOS S29C51004T, 512 KB: skipped. > Probing for TI TMS29F002RB, 256 KB: skipped. > Probing for TI TMS29F002RT, 256 KB: skipped. > Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, > id2 0x2014 > Probing for Winbond W29C011, 128 KB: skipped. > Probing for Winbond W29C020C, 256 KB: skipped. > Probing for Winbond W29C040P, 512 KB: skipped. > Probing for Winbond W29EE011, 128 KB: skipped. > Probing for Winbond W39V040A, 512 KB: skipped. > Probing for Winbond W39V040B, 512 KB: skipped. > Probing for Winbond W39V040C, 512 KB: skipped. > Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x24, > id2 0x23, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V080A, 1024 KB: skipped. > Probing for Winbond W49F002U, 256 KB: skipped. > Probing for Winbond W49V002A, 256 KB: skipped. > Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x8b, > id2 0x3e, id1 parity violation, id1 is normal flash content, id2 is > normal flash content > Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe > timing information, using default 10mS/40uS. probe_jedec_common: id1 > 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 > is normal flash content > Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct > probe timing information, using default 10mS/40uS. probe_jedec_common: > id1 0x24, id2 0x23, id1 parity violation, id1 is normal flash content, > id2 is normal flash content > Probing for Atmel unknown Atmel SPI chip, 0 KB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for EON unknown EON SPI chip, 0 KB: probe_spi_rdid_generic: > id1 0xc2, id2 0x2014 > Probing for Macronix unknown Macronix SPI chip, 0 KB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: > id1 0xc2, id2 0x2014 > Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: > id1 0xc2, id2 0x2014 > Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2014 > Probing for Sanyo unknown Sanyo SPI chip, 0 KB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Generic unknown SPI chip (RDID), 0 KB: > probe_spi_rdid_generic: id1 0xc2, id2 0x2014 > Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 > 0xc2, id2 0x13 > === > This flash part has status UNTESTED for operations: ERASE > The test status of this chip may have been updated in the latest > development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested > (-V, -Vr, > -Vw, -VE), and mention which mainboard or programmer you tested. > Thanks for your help! > === > No operations were specified. So please keep up your great work and thanks in advance for any replies

10 years, 9 months

Nokia IP530 finally fully working

by mbertens

hi all, This is the final patch for the Nokia IP530.

10 years, 9 months

Trac reminder: list of new ticket(s)

by coreboot tracker

10 years, 9 months

Re: [coreboot] [Re: coreboot] Wyse S10 Information

by Oliver Schinagl

On 05/28/2010 10:13 PM, Nils wrote: > Oliver wrote: > >> I know of the MTD driver yes, I did actually disable it in my kernel >> that I built using openwrt 'doh'. Could you give me more information >> int his regard? >> > I also don`t know that much about it,sorry. > At one point i used an openwrt squashfs? image and that worked but was > missing some drivers. > Well I get it all to work, just from USB and not MTD/IDE :) >> What flash is being used though, something from the board? Or is the >> IDE disk used as an MTD device? >> > As far as i know the flashboard is a MTD device. > You have to be careful with write access for the operating system > because the write and erase cycles are limited. > It is not an real ide disk. > Well the docs mention there's 2 ports, and it is either flash, or IDE based on a bios setting. The real question is, what is the mini-IDE port wired too. I'll look up the specs of the chip and try to follow some lines and maybe I can see. Probably not. I actually got a Transcend 1GB Disk on Chip module; It has firmware and everything, I think it's like a compact flash device, but since I haven't been able to access it via the IDE port; I don't know. If it is an MTD device, I suppose hdparm/smartctl won't work on an mtd device. >> I get a message from the pata_cs5536 driver that IDE is disabled by >> the bios; and of course no option to enable it. >> > I use linux kernel 2.6.24 witch is the only one i found that works > with the flashboard with ide driver.(maybe a bug in 2.6.24?) > I wil send you my config. > I use it on a 2.5` laptop hdd connected to the ide port. > I wil also send you a working version of coreboot + seabios you can > play with. > It is configured for ide. > You wil need the geode video driver in the kernel to see something. > Or you could use a serial connection. > Beware there are some issues most notably loading fallback/coreboot_ram > takes ~35 seconds so you have to be a little patience while booting. > > Nils > > Hmm, maybe 2.6.24 does do something? I'll try to confirm it on 2.6.24 (maybe it's only an option?) and then bisect/diff with a more recent kernel to see if they changed something. That coreboot image sounds _Very_ interesting, would I be able to build it myself? That file you sent me, is coreboot +seabios elf image combined so 'ready' but without any video output until the kernel is loaded? So the only way to choose a different boot option would be via serial console? How about USB keyboard support; that in there as well? As our S*0's only speak usb and not ps/2 :) I guess i just flash it and I'm 'done', no VSA or video rom needs to be added? Oliver

10 years, 9 months

[commit] r5599 - in trunk/src/mainboard: . ibase ibase/mb899 ibase/mb899/acpi

by repository service

Author: stepan Date: Sun May 30 14:56:17 2010 New Revision: 5599 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5599 Log: This patch adds support for mainboard iBASE:MB899 based on Kontron 986LCD-M changed superIO chip to w83627ehg, dropping MIDI dropped second superIO at 4e changed superIO-addr from 2e to 4e adjusted irq_tables.c and devicetree.cb dropped setup of 3xGBit-Ethernet adjusted IRQ-map (using values from mainboard/intel/d945gclf) disabled parts about HD-audio (missing on that board) Signed-off-by: Bernhard M. Wiedemann <corebootbmw(a)lsmod.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/mainboard/ibase/ trunk/src/mainboard/ibase/Kconfig trunk/src/mainboard/ibase/mb899/ trunk/src/mainboard/ibase/mb899/Kconfig trunk/src/mainboard/ibase/mb899/Makefile.inc trunk/src/mainboard/ibase/mb899/acpi/ trunk/src/mainboard/ibase/mb899/acpi/ec.asl trunk/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl trunk/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl trunk/src/mainboard/ibase/mb899/acpi/platform.asl trunk/src/mainboard/ibase/mb899/acpi/superio.asl trunk/src/mainboard/ibase/mb899/acpi/thermal.asl trunk/src/mainboard/ibase/mb899/acpi/video.asl trunk/src/mainboard/ibase/mb899/acpi_tables.c trunk/src/mainboard/ibase/mb899/chip.h trunk/src/mainboard/ibase/mb899/cmos.layout trunk/src/mainboard/ibase/mb899/devicetree.cb trunk/src/mainboard/ibase/mb899/dmi.h trunk/src/mainboard/ibase/mb899/dsdt.asl trunk/src/mainboard/ibase/mb899/fadt.c trunk/src/mainboard/ibase/mb899/irq_tables.c trunk/src/mainboard/ibase/mb899/mainboard.c trunk/src/mainboard/ibase/mb899/mainboard_smi.c trunk/src/mainboard/ibase/mb899/mptable.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/ibase/mb899/rtl8168.c Modified: trunk/src/mainboard/Kconfig Modified: trunk/src/mainboard/Kconfig ============================================================================== --- trunk/src/mainboard/Kconfig Sun May 30 14:35:39 2010 (r5598) +++ trunk/src/mainboard/Kconfig Sun May 30 14:56:17 2010 (r5599) @@ -48,6 +48,8 @@ bool "GIGABYTE" config VENDOR_HP bool "HP" +config VENDOR_IBASE + bool "iBase" config VENDOR_IBM bool "IBM" config VENDOR_IEI @@ -221,6 +223,11 @@ config MAINBOARD_VENDOR string + default "iBase" + depends on VENDOR_IBASE + +config MAINBOARD_VENDOR + string default "IBM" depends on VENDOR_IBM @@ -421,6 +428,7 @@ source "src/mainboard/getac/Kconfig" source "src/mainboard/gigabyte/Kconfig" source "src/mainboard/hp/Kconfig" +source "src/mainboard/ibase/Kconfig" source "src/mainboard/ibm/Kconfig" source "src/mainboard/iei/Kconfig" source "src/mainboard/intel/Kconfig" Added: trunk/src/mainboard/ibase/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/Kconfig Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,8 @@ +choice + prompt "Mainboard model" + depends on VENDOR_IBASE + +source "src/mainboard/ibase/mb899/Kconfig" + +endchoice + Added: trunk/src/mainboard/ibase/mb899/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/Kconfig Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,73 @@ +config BOARD_IBASE_MB899 + bool "MB899" + select ARCH_X86 + select CPU_INTEL_CORE + select CPU_INTEL_SOCKET_MFCPGA478 + select NORTHBRIDGE_INTEL_I945 + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select BOARD_HAS_FADT + select GENERATE_ACPI_TABLES + select GENERATE_PIRQ_TABLE + select GENERATE_MP_TABLE + select HAVE_HARD_RESET + select HAVE_ACPI_RESUME + select HAVE_MAINBOARD_RESOURCES + select MMCONF_SUPPORT + select USE_PRINTK_IN_CAR + select HAVE_SMI_HANDLER + select BOARD_ROMSIZE_KB_512 + select USE_DCACHE_RAM + select GFXUMA + select TINY_BOOTBLOCK + +config MAINBOARD_DIR + string + default ibase/mb899 + depends on BOARD_IBASE_MB899 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_IBASE_MB899 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_IBASE_MB899 + +config MAINBOARD_PART_NUMBER + string + default "MB899" + depends on BOARD_IBASE_MB899 + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + depends on BOARD_IBASE_MB899 + +config IRQ_SLOT_COUNT + int + default 18 + depends on BOARD_IBASE_MB899 + +config MAX_CPUS + int + default 4 + depends on BOARD_IBASE_MB899 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_IBASE_MB899 + +config FALLBACK_VGA_BIOS_FILE + string + default "amipci_01.20" + depends on BOARD_IBASE_MB899 + +config HAVE_ACPI_SLIC + bool + default n + depends on BOARD_IBASE_MB899 + Added: trunk/src/mainboard/ibase/mb899/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/Makefile.inc Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += rtl8168.o + +smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o Added: trunk/src/mainboard/ibase/mb899/acpi/ec.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi/ec.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} Added: trunk/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + Package() { 0x0001ffff, 1, 0, 17 }, + Package() { 0x0001ffff, 2, 0, 18 }, + Package() { 0x0001ffff, 3, 0, 19 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 17 }, + Package() { 0x001effff, 1, 0, 20 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 19}, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} + Added: trunk/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + Added: trunk/src/mainboard/ibase/mb899/acpi/platform.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi/platform.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} + Added: trunk/src/mainboard/ibase/mb899/acpi/superio.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi/superio.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} + Added: trunk/src/mainboard/ibase/mb899/acpi/thermal.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi/thermal.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU1, \_PR.CPU2}) + } + Return (Package() {\_PR.CPU1}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + Added: trunk/src/mainboard/ibase/mb899/acpi/video.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi/video.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + Added: trunk/src/mainboard/ibase/mb899/acpi_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/acpi_tables.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include "dmi.h" + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfed00000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, "COREBOOT"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n"); + memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); +#if CONFIG_WRITE_HIGH_TABLES == 1 + memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); + current += DMI_TABLE_SIZE; + ALIGN_CURRENT; +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} Added: trunk/src/mainboard/ibase/mb899/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/chip.h Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config { + int nothing; +}; Added: trunk/src/mainboard/ibase/mb899/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/cmos.layout Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,194 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (�C/�F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + Added: trunk/src/mainboard/ibase/mb899/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/devicetree.cb Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,101 @@ +chip northbridge/intel/i945 + + device lapic_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 01.0 off end # i945 PCIe root port + device pci 02.0 on end # vga controller + device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x07" + register "pirqc_routing" = "0x05" + register "pirqd_routing" = "0x07" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x06" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + + #device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627ehg + device pnp 4e.0 off # Floppy + end + device pnp 4e.1 off # Parport + end + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + end + device pnp 4e.5 on # Keyboard+Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 # HW accel A20. + end + device pnp 4e.7 on # GPIO1, GAME, MIDI + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 4e.8 on # GPIO2 + # all default + end + device pnp 4e.9 on # GPIO3/4 + irq 0x30 = 0x03 # does this work? + irq 0xf0 = 0xfb # set inputs/outputs + irq 0xf1 = 0x66 + end + device pnp 4e.a on # ACPI + end + device pnp 4e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + end + + end + + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + #device pci 1f.4 off end # Realtek ID Codec + end + end +end Added: trunk/src/mainboard/ibase/mb899/dmi.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/dmi.h Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DMI_TABLE_SIZE 0x55 + +static u8 dmi_table[DMI_TABLE_SIZE] = { + 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, + 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, + 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, + 0x30, 0x30, 0x38, 0x00, 0x00 +}; Added: trunk/src/mainboard/ibase/mb899/dsdt.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/dsdt.asl Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv2", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + + // General Purpose Events + //#include "acpi/gpe.asl" + + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include "../../../northbridge/intel/i945/acpi/i945.asl" + #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + } + } + + /* Chipset specific sleep states */ + #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" +} Added: trunk/src/mainboard/ibase/mb899/fadt.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/fadt.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0xb2 +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 2; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} Added: trunk/src/mainboard/ibase/mb899/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/irq_tables.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b9, /* Device */ + 0, /* miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf, /* u8 checksum. */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 + {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} + Added: trunk/src/mainboard/ibase/mb899/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/mainboard.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <boot/tables.h> +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <arch/coreboot_tables.h> +#include "chip.h" + +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) +{ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + + switch (M.x86.R_AX) { + case 0x5f35: /* Boot Display */ + M.x86.R_AX = 0x005f; // Success + M.x86.R_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + M.x86.R_AX = 0x005f; // Success + M.x86.R_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} + +static void int15_install(void) +{ + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +} +#endif + +/* Hardware Monitor */ + +static u16 hwm_base = 0x290; + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, hwm_base + 0x05); + outb(value, hwm_base + 0x06); +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x4e, bank); +} + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +static void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") < 0) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") < 0) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") < 0) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") < 0) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} + +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif + verb_setup(); + hwm_setup(); +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("iBASE MB899 Mainboard") + .enable_dev = mainboard_enable, +}; + Added: trunk/src/mainboard/ibase/mb899/mainboard_smi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/mainboard_smi.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + + Added: trunk/src/mainboard/ibase/mb899/mptable.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/mptable.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "MB899 "; + struct mp_config_table *mc; + struct device *riser = NULL, *firewire = NULL; + int i; + int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus; + int ioapic_id; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + max_pci_bus=0; + + firewire = dev_find_device(0x104c, 0x8023, 0); + if (firewire) { + firewire_bus = firewire->bus->secondary; + printk(BIOS_SPEW, "Firewire device is on bus %x\n", + firewire_bus); + max_pci_bus = firewire_bus; + } + + // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the + // highest bus number on the pci bus. + riser = dev_find_device(0x3388, 0x0021, 0); + if (!riser) + riser = dev_find_device(0x3388, 0x0022, 0); + if (riser) { + riser_bus = riser->link[0].secondary; + printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus); + max_pci_bus = riser_bus; + } + + /* ISA bus follows */ + isa_bus = max_pci_bus + 1; + + /* Bus: Bus ID Type */ + for (i=0; i <= max_pci_bus; i++) + smp_write_bus(mc, i, "PCI "); + + smp_write_bus(mc, isa_bus, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + ioapic_id = 2; + smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000); + + /* Legacy Interrupts */ + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf); + + /* Builtin devices on Bus 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11); + + /* Internal PCI bus (Firewire, PCI slot) */ + if (firewire) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14); + } + + if (riser) { + /* Old riser card */ + // riser slot top 5:8.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); + // riser slot middle 5:9.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); + // riser slot bottom 5:a.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16); + + /* New Riser Card */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16); + } + + /* PCIe slot */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11); + + /* Onboard Ethernet */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); + + return smp_next_mpe_entry(mc); +} + +/* MP table generation in coreboot is not very well designed; + * One of the issues is that it knows nothing about Virtual + * Wire mode, which everyone uses since a decade or so. This + * function fixes up our floating table. This spares us doing + * a half-baked fix of adding a new parameter to 200+ calls + * to smp_write_floating_table() + */ +static void fixup_virtual_wire(void *v) +{ + struct intel_mp_floating *mf = v; + + mf->mpf_checksum = 0; + mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE; + mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + fixup_virtual_wire(v); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/romstage.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,382 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +/* Configuration of the i945 driver */ +#define CHIPSET_I945GM 1 +//#define OVERRIDE_CLOCK_DISABLE 1 +#define CHANNEL_XOR_RANDOMIZATION 1 + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> + +#include "superio/winbond/w83627ehg/w83627ehg.h" + +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" + +#include <console/console.h> +#include <cpu/x86/bist.h> + +#if CONFIG_USBDEBUG +#define DBGP_DEFAULT 1 +#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" +#include "pc80/usbdebug_serial.c" +#endif + +#include "lib/ramtest.c" +#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" + +#include "northbridge/intel/i945/udelay.c" + +#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) + +#include "southbridge/intel/i82801gx/i82801gx.h" +static void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + /* General Registers */ + outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ +} + +#include "northbridge/intel/i945/early_init.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i945/raminit.h" +#include "northbridge/intel/i945/raminit.c" +#include "northbridge/intel/i945/errata.c" +#include "northbridge/intel/i945/debug.c" + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + // Enable HWM at 0x290 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); +} + +/* This box has one superio + * Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +static void early_superio_config_w83627ehg(void) +{ + device_t dev; + + dev=PNP_DEV(0x4e, W83627EHG_SP1); + pnp_enter_ext_func_mode(dev); + + pnp_write_config(dev, 0x24, 0xc4); // PNPCSV + + pnp_write_config(dev, 0x29, 0x01); // GPIO settings + pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 + pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? + pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? + pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? + + dev=PNP_DEV(0x4e, W83627EHG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627EHG_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + //pnp_write_config(dev, 0xf0, 0x82); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627EHG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); // Just enable it + + dev=PNP_DEV(0x4e, W83627EHG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 + pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + + dev=PNP_DEV(0x4e, W83627EHG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x4e, W83627EHG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + /* Enable HWM */ + dev=PNP_DEV(0x4e, W83627EHG_HWM); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); + pnp_set_enable(dev, 1); + + pnp_exit_ext_func_mode(dev); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x0146; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x0146; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +#include <cbmem.h> + +// Now, this needs to be included because it relies on the symbol +// __PRE_RAM__ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + +void main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + + if (bist == 0) { + enable_lapic(); + } + + ich7_enable_lpc(); + early_superio_config_w83627ehg(); + + /* Set up the console */ + uart_init(); + +#if CONFIG_USBDEBUG + i82801gx_enable_usbdebug(DBGP_DEFAULT); + early_usbdebug_init(); +#endif + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + sdram_initialize(boot_mode); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +#if !CONFIG_HAVE_ACPI_RESUME +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEBUG_RAM_SETUP + sdram_dump_mchbar_registers(); +#endif + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + + printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + //ram_check(0x00100000, tom); + } +#endif +#endif + + quick_ram_check(); + + MCHBAR16(SSKPD) = 0xCAFE; + +#if CONFIG_HAVE_ACPI_RESUME + /* Start address of high memory tables */ + unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } +#endif +} + Added: trunk/src/mainboard/ibase/mb899/rtl8168.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/ibase/mb899/rtl8168.c Sun May 30 14:56:17 2010 (r5599) @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8169_nic __pci_driver = { + .ops = &nic_ops, + .vendor = 0x11ab, + .device = 0x4362, +}; + +

10 years, 9 months

[commit] r5598 - trunk/util/inteltool

by repository service

Author: stepan Date: Sun May 30 14:35:39 2010 New Revision: 5598 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5598 Log: whitespace cleanup inteltool cpu.c Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/cpu.c Modified: trunk/util/inteltool/cpu.c ============================================================================== --- trunk/util/inteltool/cpu.c Sun May 30 14:33:12 2010 (r5597) +++ trunk/util/inteltool/cpu.c Sun May 30 14:35:39 2010 (r5598) @@ -33,12 +33,12 @@ uint32_t ret; #if defined(__DARWIN__) && !defined(__LP64__) - asm volatile ( - "pushl %%ebx \n" - "cpuid \n" - "popl %%ebx \n" - : "=a" (ret) : "a" (op) : "%ecx", "%edx" - ); + asm volatile ( + "pushl %%ebx\n" + "cpuid\n" + "popl %%ebx\n" + : "=a" (ret) : "a" (op) : "%ecx", "%edx" + ); #else asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx"); #endif

10 years, 9 months

[commit] r5597 - trunk/util/inteltool

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Author: stepan Date: Sun May 30 14:33:12 2010 New Revision: 5597 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5597 Log: Added support to ICH9 chipset family Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/gpio.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c trunk/util/inteltool/powermgt.c trunk/util/inteltool/rootcmplx.c Modified: trunk/util/inteltool/gpio.c ============================================================================== --- trunk/util/inteltool/gpio.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/gpio.c Sun May 30 14:33:12 2010 (r5597) @@ -114,6 +114,24 @@ { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" } }; +static const io_register_t ich9_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "RESERVED" } +}; int print_gpios(struct pci_dev *sb) { @@ -124,6 +142,16 @@ printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich9_gpio_registers; + size = ARRAY_SIZE(ich9_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH8M: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich8_gpio_registers; Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/inteltool.c Sun May 30 14:33:12 2010 (r5597) @@ -45,7 +45,14 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME-GMCH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/inteltool.h Sun May 30 14:33:12 2010 (r5597) @@ -44,6 +44,12 @@ #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 +#define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9R 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9 0x2918 +#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 +#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 #define PCI_DEVICE_ID_INTEL_82810 0x7120 @@ -58,10 +64,10 @@ #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 +#define PCI_DEVICE_ID_INTEL_GS45 0x2a40 #define PCI_DEVICE_ID_INTEL_X58 0x3405 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 - /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ #define PCI_DEVICE_ID_INTEL_82443BX 0x7190 #define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 Modified: trunk/util/inteltool/memory.c ============================================================================== --- trunk/util/inteltool/memory.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/memory.c Sun May 30 14:33:12 2010 (r5597) @@ -54,6 +54,10 @@ case PCI_DEVICE_ID_INTEL_82830M: printf("This northbrigde does not have MCHBAR.\n"); return 1; + case PCI_DEVICE_ID_INTEL_GS45: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); return 1; Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/pcie.c Sun May 30 14:33:12 2010 (r5597) @@ -43,6 +43,7 @@ case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_GS45: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -95,12 +96,12 @@ case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_GS45: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: - case PCI_DEVICE_ID_INTEL_82830M: printf("This northbrigde does not have DMIBAR.\n"); return 1; default: @@ -149,6 +150,7 @@ case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_GS45: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; Modified: trunk/util/inteltool/powermgt.c ============================================================================== --- trunk/util/inteltool/powermgt.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/powermgt.c Sun May 30 14:33:12 2010 (r5597) @@ -21,47 +21,47 @@ #include <stdio.h> #include "inteltool.h" -static const io_register_t ich7_pm_registers[] = { - { 0x00, 2, "PM1_STS" }, - { 0x02, 2, "PM1_EN" }, - { 0x04, 4, "PM1_CNT" }, - { 0x08, 4, "PM1_TMR" }, +static const io_register_t ich9_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK + { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 + { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK + { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK { 0x0c, 4, "RESERVED" }, - { 0x10, 4, "PROC_CNT" }, + { 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK #if DANGEROUS_REGISTERS /* These registers return 0 on read, but reading them may cause - * the system to enter C2/C3/C4 state, which might hang the system. + * the system to enter Cx states, which might hang the system. */ - { 0x14, 1, "LV2 (Mobile/Ultra Mobile)" }, - { 0x15, 1, "LV3 (Mobile/Ultra Mobile)" }, - { 0x16, 1, "LV4 (Mobile/Ultra Mobile)" }, + { 0x14, 1, "LV2 (Mobile)" }, + { 0x15, 1, "LV3 (Mobile)" }, + { 0x16, 1, "LV4 (Mobile)" }, + { 0x17, 1, "LV5 (Mobile)" }, + { 0x18, 1, "LV6 (Mobile)" }, #endif - { 0x17, 1, "RESERVED" }, - { 0x18, 4, "RESERVED" }, + { 0x19, 1, "RESERVED" }, + { 0x1a, 2, "RESERVED" }, { 0x1c, 4, "RESERVED" }, - { 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" }, - { 0x21, 1, "RESERVED" }, - { 0x22, 2, "RESERVED" }, - { 0x24, 4, "RESERVED" }, - { 0x28, 4, "GPE0_STS" }, - { 0x2C, 4, "GPE0_EN" }, + { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK + { 0x2C, 4, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8 { 0x30, 4, "SMI_EN" }, { 0x34, 4, "SMI_STS" }, { 0x38, 2, "ALT_GP_SMI_EN" }, { 0x3a, 2, "ALT_GP_SMI_STS" }, - { 0x3c, 4, "RESERVED" }, + { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control; + { 0x3d, 2, "RESERVED" }, + { 0x3f, 1, "RESERVED" }, { 0x40, 2, "RESERVED" }, { 0x42, 1, "GPE_CNTL" }, { 0x43, 1, "RESERVED" }, - { 0x44, 2, "DEVACT_STS" }, + { 0x44, 2, "DEVACT_STS" }, // Device Activity Status { 0x46, 2, "RESERVED" }, { 0x48, 4, "RESERVED" }, { 0x4c, 4, "RESERVED" }, - { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, + { 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK { 0x51, 1, "RESERVED" }, { 0x52, 2, "RESERVED" }, - { 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" }, - { 0x58, 4, "RESERVED" }, + { 0x54, 4, "C3_RES (Mobile)" }, + { 0x58, 4, "C5_RES (Mobile)" }, { 0x5c, 4, "RESERVED" }, /* Here start the TCO registers */ { 0x60, 2, "TCO_RLD" }, @@ -145,6 +145,67 @@ { 0x7c, 4, "RESERVED" }, }; +static const io_register_t ich7_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, +#if DANGEROUS_REGISTERS + /* These registers return 0 on read, but reading them may cause + * the system to enter C2/C3/C4 state, which might hang the system. + */ + { 0x14, 1, "LV2 (Mobile/Ultra Mobile)" }, + { 0x15, 1, "LV3 (Mobile/Ultra Mobile)" }, + { 0x16, 1, "LV4 (Mobile/Ultra Mobile)" }, +#endif + { 0x17, 1, "RESERVED" }, + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" }, + { 0x21, 1, "RESERVED" }, + { 0x22, 2, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2C, 4, "GPE0_EN" }, + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 2, "RESERVED" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x43, 1, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, + { 0x51, 1, "RESERVED" }, + { 0x52, 2, "RESERVED" }, + { 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + /* * INTEL I/O Controller Hub 6 Family * http://www.intel.com/assets/pdf/datasheet/301473.pdf @@ -357,6 +418,16 @@ pm_registers = ich7_pm_registers; size = ARRAY_SIZE(ich7_pm_registers); break; + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich9_pm_registers; + size = ARRAY_SIZE(ich9_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH8M: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich8_pm_registers; Modified: trunk/util/inteltool/rootcmplx.c ============================================================================== --- trunk/util/inteltool/rootcmplx.c Fri May 28 18:21:21 2010 (r5596) +++ trunk/util/inteltool/rootcmplx.c Sun May 30 14:33:12 2010 (r5597) @@ -36,6 +36,12 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH8M: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break;

10 years, 9 months

Indtast Bcc Re Will coreboot work on my machine?

by anders＠jenbo.dk

Yes two of there boards, but what is your point? The board you asked about was ASUS, E2938. Do you also have another board? Mvh Anders ----- Reply message ----- Fra: "am kara" <am_kara(a)yahoo.com> Dato: søn., maj 30, 2010 08:57 Emne: Re [coreboot] Will coreboot work on my machine? Til: "anders(a)jenbo.dk" <anders(a)jenbo.dk>

10 years, 9 months

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coreboot May 2010